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Cache.h
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1 //===------------------------------------------------------------*- C++ -*-===//
2 //
3 // T-EMU: The Terma Emulator
4 // (c) Terma 2015
5 // Authors: Mattias Holm <maho (at) terma.com>
6 //
7 //===----------------------------------------------------------------------===//
8 
9 /*
10  * WARNING: The interfaces defined in this header are at present
11  * considered: EXPERIMENTAL!!! In particularly, this means
12  * that there is no guaranteed API stability for the cache
13  * interfaces at the moment.
14  */
15 
16 #ifndef TEMU_CACHE_H
17 #define TEMU_CACHE_H
18 
19 #include "temu-c/Support/Objsys.h"
20 #include "temu-c/Memory/Memory.h"
21 
22 #include <stdint.h>
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 // List of cache algorithms and corresponding numbers, numbers 0
29 // through 128 are reserved. Note that NONE implies that the cache is
30 // directly mapped, i.e. sets should be 1.
31 #define TEMU_CACHE_NONE 0
32 #define TEMU_CACHE_LRU 1
33 #define TEMU_CACHE_LRR 2
34 #define TEMU_CACHE_RND 3
35 
36 // Caches implement the memory access interface and the cache control
37 // interface. For invalidate and evict operation the address given is
38 // a physical address which should be mapped to a line. For Harward
39 // style caches, the cache model would typically implement the
40 // interface twice, once for instructions and once for data.
41 
42 // Invalidation: cache line will be tagged as invalid (i.e. flushed)
43 // Eviction: cache line will be invalidated and in writeBack caches
44 // the content will be written back to memory.
45 
46 typedef struct temu_CacheIface {
47  // Control cache status
48  void (*enable)(void *Obj);
49  void (*disable)(void *Obj);
50  void (*freeze)(void *Obj);
51 
52  void (*lockLine)(void *Obj, uint64_t Addr);
53  void (*unlockLine)(void *Obj, uint64_t Addr);
54 
55 
56  void (*invalidateAll)(void *Obj);
57  void (*invalidateLine)(void *Obj, uint64_t Addr);
58 
59  void (*evictAll)(void *Obj);
60  void (*evictLine)(void *Obj, uint64_t Addr);
61 
62  // Inerrogation of cache properties
63  // - A directly mapped cache has 1 way, but typically several sets
64  // - A fully associative cache has 1 set, but typically several ways
65  // - Total cache size in bytes is sets * ways * linesize
66  uint32_t (*getReplacementPolicy)(void *Obj);
67  uint32_t (*getSets)(void *Obj);
68  uint32_t (*getWays)(void *Obj);
69  uint32_t (*getLineSize)(void *Obj);
70 
71  // Check if an address belong to a cached line
72  int (*isValid)(void *Obj, uint64_t Addr);
73 
74  // Access the flags data, the format is cache model specific and can
75  // for specific models include also the tag. Typically, this is used
76  // for diagnostic access for more accurate cache models. Note that
77  // addr is not a physical address, but rather an address interpreted
78  // differently for different caches. I.e. the address is in a cache
79  // local address space.
80  uint64_t (*readFlags)(void *Obj, uint64_t Addr);
81  void (*writeFlags)(void *Obj, uint64_t Addr, uint64_t Flags);
82 
83  // Get cached data for the given address. The data returned comes
84  // from RAM using a normal memory transaction in case the cache is
85  // modelled for timing only, otherwise it comes from the cache
86  // model. Addr is a cache local address space, which depends on the
87  // cache implementation. The functions are intended for diagnostic
88  // cache access which is implemented in some systems. Note that on
89  // writes, the data will NOT be written to memory except in the case
90  // the cache line would be evicted in an accurate cache model. All
91  // reads from valid addresses succeed, other addresses are
92  // undefined. writeData returns non-zero on failure (e.g. invalid
93  // address).
94  uint64_t (*readData)(void *Obj, uint64_t Addr);
95  int (*writeData)(void *Obj, uint64_t Addr, uint64_t Data);
97 #define TEMU_CACHE_IFACE_TYPE "CacheIface"
98 TEMU_IFACE_REFERENCE_TYPE(temu_Cache);
99 
100 // The cache control interface can be implemented by a cache
101 // controller. Which may be emdedded in a CPU or device
102 // model. Typically, the assumption is that the cache controller will
103 // turn on and off the cache and that it may need to be notified on
104 // global eviction operations, which may or may not be reflected in
105 // the cache controllers status registers.
106 typedef struct temu_CacheCtrlIface {
107  // Global evict operation ongoing
108  void (*evictionInProgress)(void *Obj);
109 
110  // Global evict operation completed
111  void (*evictionCompleted)(void *Obj);
113 #define TEMU_CACHE_CTRL_IFACE_TYPE "CacheCtrlIface"
114 TEMU_IFACE_REFERENCE_TYPE(temu_CacheCtrl);
115 
116 #ifdef __cplusplus
117 }
118 #endif
119 
120 #endif /* ! TEMU_CACHE_H */
void(* disable)(void *Obj)
Definition: Cache.h:49
int(* writeData)(void *Obj, uint64_t Addr, uint64_t Data)
Definition: Cache.h:95
void(* lockLine)(void *Obj, uint64_t Addr)
Definition: Cache.h:52
void(* writeFlags)(void *Obj, uint64_t Addr, uint64_t Flags)
Definition: Cache.h:81
uint64_t(* readData)(void *Obj, uint64_t Addr)
Definition: Cache.h:94
void(* evictionCompleted)(void *Obj)
Definition: Cache.h:111
void(* invalidateAll)(void *Obj)
Definition: Cache.h:56
void(* invalidateLine)(void *Obj, uint64_t Addr)
Definition: Cache.h:57
struct temu_CacheCtrlIface temu_CacheCtrlIface
#define TEMU_IFACE_REFERENCE_TYPE(N)
Definition: Objsys.h:129
uint32_t(* getLineSize)(void *Obj)
Definition: Cache.h:69
void(* unlockLine)(void *Obj, uint64_t Addr)
Definition: Cache.h:53
uint32_t(* getReplacementPolicy)(void *Obj)
Definition: Cache.h:66
void(* evictLine)(void *Obj, uint64_t Addr)
Definition: Cache.h:60
void(* enable)(void *Obj)
Definition: Cache.h:48
int(* isValid)(void *Obj, uint64_t Addr)
Definition: Cache.h:72
void(* freeze)(void *Obj)
Definition: Cache.h:50
uint64_t(* readFlags)(void *Obj, uint64_t Addr)
Definition: Cache.h:80
void(* evictionInProgress)(void *Obj)
Definition: Cache.h:108
uint32_t(* getWays)(void *Obj)
Definition: Cache.h:68
void(* evictAll)(void *Obj)
Definition: Cache.h:59
uint32_t(* getSets)(void *Obj)
Definition: Cache.h:67
struct temu_CacheIface temu_CacheIface