PCI.h

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//===------------------------------------------------------------*- C++ -*-===//
//
// T-EMU: The Terma Emulator
// (c) Terma 2019
// Authors: Mattias Holm <maho (at) terma.com>
//
//===----------------------------------------------------------------------===//

#ifndef TEMU_BUS_PCI_H
#define TEMU_BUS_PCI_H
#include <assert.h>
#include <stdint.h>

#include "temu-c/Memory/Memory.h"
#include "temu-c/Support/Logging.h"
#include "temu-c/Support/Objsys.h"

// Base and subclass codes
#define tePciBc_Pre 0x00
#define tePciSc_Any 0x00
#define tePciSc_Vga 0x01

#define tePciBc_MassStorageController 0x01
#define tePciSc_ScsiBusController 0x00
#define tePciSc_IdeController 0x01
#define tePciSc_FloppyDiskController 0x02
#define tePciSc_IpiBusController 0x03
#define tePciSc_RaidController 0x04
#define tePciSc_AtaController 0x05
#define tePciSc_SataController 0x06 // Serial ATA
#define tePciSc_SasController 0x07  // Serial attached SCSI
#define tePciSc_OtherMassStorageController 0x80

#define tePciBc_NetworkController 0x02
#define tePciSc_EthernetController 0x00
#define tePciSc_TokenRingController 0x01
#define tePciSc_FddiController 0x02
#define tePciSc_AtmController 0x03
#define tePciSc_IsdnController 0x04
#define tePciSc_WorldFipController 0x05
#define tePciSc_PicmgMultiComputing 0x06
#define tePciSc_OtherNetworkController 0x80

#define tePciBc_DisplayController 0x03
#define tePciSc_VgaController 0x00
#define tePciSc_XgaController 0x01
#define tePciSc_3dController 0x02
#define tePciSc_OtherDisplayController 0x80

#define tePciBc_MultimedaiDevice 0x04
#define tePciSc_VideoDevice 0x00
#define tePciSc_AudioDevice 0x01
#define tePciSc_ComptuterTelephonyDevice 0x02
#define tePciSc_OtherMultimediaDevice 0x80

#define tePciBc_MemoryController 0x05
#define tePciSc_RAM 0x00
#define tePciSc_Flash 0x01
#define tePciSc_OtherMemoryController 0x80

#define tePciBc_BridgeDevice 0x06
#define tePciSc_HostBridge 0x00
#define tePciSc_IsaBridge 0x01
#define tePciSc_EisaBridge 0x02
#define tePciSc_McaBridge 0x03
#define tePciSc_PciToPciBridge 0x04
#define tePciSc_PcmciaBridge 0x05
#define tePciSc_NuBusBridge 0x06
#define tePciSc_CardBusBridge 0x07
#define tePciSc_RaceWayBridge 0x08
#define tePciSc_SemiTransparentPciToPciBridge 0x09
#define tePciSc_InfiniBandToPciHostBridge 0x0a
#define tePciSc_OtherBridgeDevice 0x80

#define tePciBc_SimpleCommunicationController 0x07
#define tePciSc_SerialController 0x00
#define tePciSc_ParallelPort 0x01
#define tePciSc_MultiPortSerialController 0x02
#define tePciSc_Modem 0x03
#define tePciSc_GpibController 0x04
#define tePciSc_SmartCard 0x05
#define tePciSc_OtherCommunicationsDevice 0x80

#define tePciBc_BaseSystemPeripheral 0x08
#define tePciSc_Pic 0x00
#define tePciSc_DmaController 0x01
#define tePciSc_SystemTimer 0x02
#define tePciSc_RtcController 0x03
#define tePciSc_PciHotPlugController 0x04
#define tePciSc_SdHostController 0x05
#define tePciSc_OtherSystemPeripheral 0x80

#define tePciBc_InputDevice 0x09
#define tePciSc_KeyboardController 0x00
#define tePciSc_Digitizer 0x01
#define tePciSc_MouseController 0x02
#define tePciSc_ScannerController 0x03
#define tePciSc_GameportController 0x04
#define tePciSc_OtherInputController 0x80

#define tePciBc_DockingStation 0x0a
#define tePciSc_GenericDockingStation 0x00
#define tePciSc_OtherDockingStation 0x80

#define tePciBc_Processor 0x0b
#define tePciSc_386 0x00
#define tePciSc_486 0x01
#define tePciSc_Pentium 0x02
#define tePciSc_Alpha 0x10
#define tePciSc_PowerPC 0x20
#define tePciSc_MIPS 0x30
#define tePciSc_CoProcessor 0x40

#define tePciBc_SerialBusController 0x0c
#define tePciSc_FireWire 0x00
#define tePciSc_Ieee1394 0x00
#define tePciSc_AccessBus 0x01
#define tePciSc_Ssa 0x02
#define tePciSc_Usb 0x03
#define tePciSc_FibreChannel 0x04
#define tePciSc_SystemManagementBus 0x05
#define tePciSc_InfiniBand 0x06
#define tePciSc_Ipmi 0x07
#define tePciSc_SercosInterfaceStandard 0x08
#define tePciSc_CanBus 0x09

#define tePciBc_WirelessController 0x0d
#define tePciSc_IrdaCompatibleController 0x00
#define tePciSc_ConsumerIrController 0x01
#define tePciSc_RfController 0x10
#define tePciSc_BluetoothController 0x11
#define tePciSc_BroadbandController 0x12
#define tePciSc_Ethernet802_11aController 0x20
#define tePciSc_Ethernet802_11bController 0x20
#define tePciSc_OtherWirelessController 0x80

#define tePciBc_IntellegentIoController 0x0e

#define tePciBc_SatelliteCommunicationController 0x0f
#define tePciSc_Tv 0x01
#define tePciSc_Audio 0x02
#define tePciSc_Voice 0x03
#define tePciSc_Data 0x04

#define tePciBc_EncryptionDecryptionController 0x10
#define tePciSc_NetworkAndComputingCrypto 0x00
#define tePciSc_EntertainmentCrypto 0x10
#define tePciSc_OtherCrypto 0x80

#define tePciBc_DataAcquisitionAndSignalProcessingController 0x11
#define tePciSc_DpioModules 0x00
#define tePciSc_PerformanceCounters 0x01
#define tePciSc_CommSyncPlusTimeAndFreq 0x10
#define tePciSc_ManagementCard 0x20
#define tePciSc_OtherDataAcquisitionSignalProcessingController 0x80

#define tePciBc_Unknown 0xff

typedef struct {
  temu_MemAccessIface ConfigAccess;
  temu_MemAccessIface IoAccess;
  temu_MemAccessIface MemAccess;
  temu_MemoryIface ConfigBlock;
  temu_MemoryIface IoBlock;
  temu_MemoryIface MemBlock;
} temu_PCIDeviceVTable;

typedef struct {
  uint32_t DeviceVendorID;
  uint32_t StatusCommand;
  uint32_t ClassCodeRevID;
  uint32_t BISTHeaderTypeLatencyTimerCacheLineSize;
  uint32_t BAR[6];
  uint32_t CardbusCISPointer;
  uint32_t SubsystemVendorID;
  uint32_t ExpansionROMBaseAddress;
  uint32_t CapPointer;
  uint32_t MaxLatMinGntIntPinLine;
} temu_PCIConfig;

typedef struct {
  uint8_t Reserved;
  uint8_t Length;
  uint8_t NextPointer;
  uint8_t CapabilityID;
  uint32_t PCItoAHBAddressMapping[6];
  uint32_t AHBBaseAndPCIBusCfg;
  uint32_t PCIBARSizeAndPrefetch;
  uint32_t AHBMasterPrefetchBurstLimit;
} temu_PCIAMBAExtConfig;

typedef struct {
  void (*raiseReset)(temu_Object_ *);
  void (*lowerReset)(temu_Object_ *);
  void (*connect)(temu_Object_ *, temu_Object_ *);
  void (*disconnect)(temu_Object_ *, temu_Object_ *);
} temu_PCIBridgeIface;
TEMU_IFACE_REFERENCE_TYPE(temu_PCIBridge)
#define TEMU_PCI_BRIDGE_IFACE_TYPE "temu::PCIBridgeIface"

typedef struct {
  void (*startSelfTest)(
      temu_Object_ *); // Optional, called when BIST bit 6 is set
  temu_PCIConfig *(*getPciConfig)(void *);
  // Writes to config space forwarded here
  void (*writeConfig)(temu_Object_ *, temu_MemTransaction *MT);
  uint64_t (*getPciBarSize)(temu_Object_ *, unsigned bar);
  uint64_t (*getPciExpansionROMSize)(temu_Object_ *);
} temu_PCIDeviceIface;
TEMU_IFACE_REFERENCE_TYPE(temu_PCIDevice)
#define TEMU_PCI_DEVICE_IFACE_TYPE "temu::PCIDeviceIface"

typedef struct {
  temu_Object Super;
  temu_PCIConfig Conf;
} temu_PCIDevice;

static inline void
temu_pciDeviceRegister(temu_Class *C)
{
  temu_addProperty(C, "pciConfigDeviceVendorID",
                   offsetof(temu_PCIDevice, Conf.DeviceVendorID),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Device and Vendor ID");


  temu_addProperty(C, "pciConfigStatusCommand",
                   offsetof(temu_PCIDevice, Conf.StatusCommand),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Status and Command Register");

  temu_addProperty(C, "pciConfigClassCodeRevID",
                   offsetof(temu_PCIDevice, Conf.ClassCodeRevID),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Class Code and Revision ID");

  temu_addProperty(C, "pciConfigBistHeaderLatencyCacheLineAndSize",
                   offsetof(temu_PCIDevice, Conf.BISTHeaderTypeLatencyTimerCacheLineSize),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI BIST, Header Type, Latency and cache line size");

  temu_addProperty(C, "pciConfigBAR",
                   offsetof(temu_PCIDevice, Conf.BAR),
                   teTY_U32,
                   6, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Base Address Registers");

  temu_addProperty(C, "pciConfigCardbusCISPointer",
                   offsetof(temu_PCIDevice, Conf.CardbusCISPointer),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Cardbus CIS Pointer");

  temu_addProperty(C, "pciConfigSubsystemVendorID",
                   offsetof(temu_PCIDevice, Conf.SubsystemVendorID),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Subsystem and Subsystem Vendor ID");

  temu_addProperty(C, "pciConfigExpansionROMBaseAddress",
                   offsetof(temu_PCIDevice, Conf.ExpansionROMBaseAddress),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Expansion ROM base address");

  temu_addProperty(C, "pciConfigCapabilityPointer",
                   offsetof(temu_PCIDevice, Conf.CapPointer),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Capability list pointer");

  temu_addProperty(C, "pciConfigMaxLatMinGntIntPinLine",
                   offsetof(temu_PCIDevice, Conf.MaxLatMinGntIntPinLine),
                   teTY_U32,
                   1, // Number of elements (1 = scalar)
                   NULL, NULL,
                   "PCI Max latency, min gnt, int pin and int line");
}

static inline void
temu_pciSetDeviceId(temu_PCIConfig *C, uint16_t Val)
{
  C->DeviceVendorID = ((uint32_t)Val << 16) | (C->DeviceVendorID & 0xffff);
}

static inline void
temu_pciSetVendorId(temu_PCIConfig *C, uint16_t Val)
{
  C->DeviceVendorID = (uint32_t)Val | (C->DeviceVendorID & 0xffff0000);
}

static inline void
temu_pciSetStatus(temu_PCIConfig *C, uint16_t Val)
{
  C->StatusCommand = ((uint32_t)Val << 16) | (C->StatusCommand & 0xffff);
}

static inline void
temu_pciSetClassCode(temu_PCIConfig *C, uint32_t Val)
{
  C->ClassCodeRevID &= 0x000000ff;
  C->ClassCodeRevID |= Val << 8;
}

static inline void
temu_pciSetRevId(temu_PCIConfig *C, uint8_t Val)
{
  C->ClassCodeRevID &= 0xffffff00;
  C->ClassCodeRevID |= Val;
}

static inline void
temu_pciSetBist(temu_PCIConfig *C, uint8_t Val)
{
  C->BISTHeaderTypeLatencyTimerCacheLineSize =
      ((uint32_t)Val << 24) |
      (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0x00ffffff);
}

static inline void
temu_pciSetHeaderType(temu_PCIConfig *C, uint8_t Val)
{
  C->BISTHeaderTypeLatencyTimerCacheLineSize =
      ((uint32_t)Val << 16) |
      (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xff00ffff);
}

static inline void
temu_pciSetLatencyTimer(temu_PCIConfig *C, uint8_t Val)
{
  C->BISTHeaderTypeLatencyTimerCacheLineSize =
      ((uint32_t)Val << 8) |
      (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffff00ff);
}

static inline void
temu_pciSetCacheLineSize(temu_PCIConfig *C, uint8_t Val)
{
  C->BISTHeaderTypeLatencyTimerCacheLineSize =
      ((uint32_t)Val << 0) |
      (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffffff00);
}

static inline void
temu_pciSetInterruptPin(temu_PCIConfig *C, uint8_t Val)
{
  assert(Val < 0x05);
  C->MaxLatMinGntIntPinLine =
      ((uint32_t)Val << 8) | (C->MaxLatMinGntIntPinLine & 0xffff00ff);
}

static inline void
temu_pciSetSubsystemId(temu_PCIConfig *C, uint16_t Val)
{
  C->SubsystemVendorID =
      (uint32_t)Val << 16 | (C->SubsystemVendorID & 0x0000ffff);
}

static inline void
temu_pciSetSubsystemVendorId(temu_PCIConfig *C, uint16_t Val)
{
  C->SubsystemVendorID =
      (uint32_t)Val << 0 | (C->SubsystemVendorID & 0xffff0000);
}

#endif // !TEMU_BUS_PCI_H