10 #define TEMU_BUS_PCI_H 42 void (*mapPciIo)(
temu_Object *Obj,
unsigned Device,
unsigned Bar,
43 uint64_t Addr, uint64_t Len);
45 void (*mapPciMem)(
temu_Object *Obj,
unsigned Device,
unsigned Bar,
46 uint64_t Addr, uint64_t Len);
50 #define TEMU_PCI_BUS_IFACE_TYPE "temu::PCIBusIface" 59 #define TEMU_PCI_BRIDGE_IFACE_TYPE "temu::PCIBridgeIface" 62 void (*startSelfTest)(
66 void (*writeConfig)(
temu_Object *, uint32_t offset, uint32_t value);
73 #define TEMU_PCI_DEVICE_IFACE_TYPE "temu::PCIDeviceIface" 86 NULL, NULL,
"PCI Device and Vendor ID");
91 NULL, NULL,
"PCI Status and Command Register");
96 NULL, NULL,
"PCI Class Code and Revision ID");
99 C,
"pciConfigBistHeaderLatencyCacheLineAndSize",
100 offsetof(
temu_PCIDevice, Conf.BISTHeaderTypeLatencyTimerCacheLineSize),
103 NULL, NULL,
"PCI BIST, Header Type, Latency and cache line size");
108 NULL, NULL,
"PCI Base Address Registers");
113 NULL, NULL,
"PCI Cardbus CIS Pointer");
118 NULL, NULL,
"PCI Subsystem and Subsystem Vendor ID");
124 NULL, NULL,
"PCI Expansion ROM base address");
129 NULL, NULL,
"PCI Capability list pointer");
132 C,
"pciConfigMaxLatMinGntIntPinLine",
135 NULL, NULL,
"PCI Max latency, min gnt, int pin and int line");
174 ((uint32_t)Val << 24) |
182 ((uint32_t)Val << 16) |
190 ((uint32_t)Val << 8) |
198 ((uint32_t)Val << 0) |
224 #endif // !TEMU_BUS_PCI_H #define TEMU_IFACE_REFERENCE_TYPE(N)
Definition: Objsys.h:180
uint32_t MaxLatMinGntIntPinLine
Definition: PCI.h:38
temu_MemoryIface ConfigBlock
Definition: PCI.h:23
uint32_t StatusCommand
Definition: PCI.h:30
TEMU_API void temu_addProperty(temu_Class *Cls, const char *PropName, int Offset, temu_Type Typ, int Count, temu_PropWriter Wr, temu_PropReader Rd, const char *Doc)
uint32_t ExpansionROMBaseAddress
Definition: PCI.h:36
temu_MemAccessIface ConfigAccess
Definition: PCI.h:20
uint32_t DeviceVendorID
Definition: PCI.h:29
uint32_t CapPointer
Definition: PCI.h:37
uint32_t CardbusCISPointer
Definition: PCI.h:34
uint32_t ClassCodeRevID
Definition: PCI.h:31
uint32_t BISTHeaderTypeLatencyTimerCacheLineSize
Definition: PCI.h:32
temu_MemoryIface MemBlock
Definition: PCI.h:25
temu_Object Super
Definition: PCI.h:76
32-bit fixed width unsigned integer
Definition: Objsys.h:296
temu_MemAccessIface MemAccess
Definition: PCI.h:22
temu_PCIConfig Conf
Definition: PCI.h:77
temu_MemAccessIface IoAccess
Definition: PCI.h:21
uint32_t SubsystemVendorID
Definition: PCI.h:35
temu_MemoryIface IoBlock
Definition: PCI.h:24