9 #ifndef TEMU_BUS_PCIe_H 10 #define TEMU_BUS_PCIe_H 138 uint32_t HeaderLogReg[4];
150 uint64_t Addr, uint64_t Len);
152 void (*mapPciMem)(
temu_Object *Obj,
unsigned Device,
unsigned Bar,
153 uint64_t Addr, uint64_t Len);
157 #define TEMU_PCIe_BUS_IFACE_TYPE "temu::PCIExpressBusIface" 168 #define TEMU_PCIe_BRIDGE_IFACE_TYPE "temu::PCIExpressBridgeIface" 173 void (*writeConfig)(
temu_Object *, uint32_t offset, uint32_t value);
180 #define TEMU_PCIe_DEVICE_IFACE_TYPE "temu::PCIExpressDeviceIface" 255 static inline uint16_t
279 ((uint32_t)Val << 24) |
287 ((uint32_t)Val << 16) |
295 ((uint32_t)Val << 8) |
303 ((uint32_t)Val << 0) |
312 ((uint32_t)Val << 8) |
340 ((uint32_t)Val << 8) |
347 ((uint32_t)Val << 16) |
361 ((uint32_t)Val << 8) |
368 ((uint32_t)Val << 16) |
394 ((uint32_t)Val << 16) |
413 ((uint32_t)Val << 16) |
417 static inline uint16_t
423 static inline uint32_t
438 #endif // !TEMU_BUS_PCIe_H uint32_t CorrectableErrorStatusReg
Definition: PCIExpress.h:135
uint32_t AdvancedErrorCapabilitiesControlReg
Definition: PCIExpress.h:137
uint32_t UncorrectableErrorSeverityReg
Definition: PCIExpress.h:134
#define TEMU_IFACE_REFERENCE_TYPE(N)
Definition: Objsys.h:180
uint32_t LTSSMStateStatusReg
Definition: PCIExpress.h:106
uint32_t DataPowerMgmtStatusControl
Definition: PCIExpress.h:87
temu_Object Super
Definition: PCIExpress.h:186
uint32_t SlotCapabilities
Definition: PCIExpress.h:94
uint8_t PrimBusId
Definition: PCIExpress.h:202
Definition: PCIExpress.h:33
Definition: PCIExpress.h:199
uint32_t SubsystemVendorID
Definition: PCIExpress.h:64
uint32_t LatencyTimer2SubBusNumBusNum2PrimBusNum
Definition: PCIExpress.h:73
Definition: PCIExpress.h:34
temu_PCIeMessageTypes
Definition: PCIExpress.h:28
Definition: PCIExpress.h:51
uint32_t MsgControlPointerMsgCapabilityID
Definition: PCIExpress.h:99
Definition: PCIExpress.h:61
Definition: PCIExpress.h:185
Definition: PCIExpress.h:105
uint32_t UpperIOLimitIOBase
Definition: PCIExpress.h:79
uint32_t ControllerCoreClockRatioReg
Definition: PCIExpress.h:107
uint32_t CardbusCISPointer
Definition: PCIExpress.h:63
temu_PCIExpressBus * PrimaryBus
Definition: PCIExpress.h:188
uint32_t CorrectableErrorMaskReg
Definition: PCIExpress.h:136
uint32_t SlotStatusControl
Definition: PCIExpress.h:95
Definition: PCIExpress.h:39
uint8_t BusId
Definition: PCIExpress.h:193
uint32_t UncorrectableErrorMaskReg
Definition: PCIExpress.h:133
temu_PCIExpressDevice Super
Definition: PCIExpress.h:200
uint32_t LinkCapabilities
Definition: PCIExpress.h:92
temu_Object Super
Definition: PCIExpress.h:192
Definition: PCIExpress.h:31
Definition: PCIExpress.h:47
uint32_t RootControl
Definition: PCIExpress.h:96
uint32_t DeviceStatusControl
Definition: PCIExpress.h:91
uint32_t SecondaryStatusIrqMaskReg
Definition: PCIExpress.h:113
uint32_t BISTHeaderTypeLatencyTimerCacheLineSize
Definition: PCIExpress.h:124
Definition: PCIExpress.h:119
Definition: PCIExpress.h:159
Definition: PCIExpress.h:48
uint32_t CapPointer
Definition: PCIExpress.h:125
temu_PCIeDeviceSpecificConfigSpace PCIeDevConfig
Definition: PCIExpress.h:144
Definition: PCIExpress.h:170
uint32_t MessageAddress
Definition: PCIExpress.h:100
Definition: PCIExpress.h:49
uint32_t PMETimeOutReg
Definition: PCIExpress.h:109
uint32_t CorrectableErrorSourceIdReg
Definition: PCIExpress.h:141
Definition: PCIExpress.h:38
uint32_t RootErrorStatusReg
Definition: PCIExpress.h:140
Definition: PCIExpress.h:30
uint32_t SubsystemVendorIDUpdateReg
Definition: PCIExpress.h:110
temu_PCIeConfigType0 ConfigType0
Definition: PCIExpress.h:127
uint32_t PrefetchableBaseUpper
Definition: PCIExpress.h:77
uint32_t DeviceCapabilities
Definition: PCIExpress.h:90
Definition: PCIExpress.h:54
uint32_t ConfigurationReadyReg
Definition: PCIExpress.h:111
Definition: PCIExpress.h:35
uint32_t RootStatus
Definition: PCIExpress.h:97
Definition: PCIExpress.h:71
uint32_t PrefetchableMemoryLimitBase
Definition: PCIExpress.h:76
uint32_t LinkStatusControl
Definition: PCIExpress.h:93
uint16_t AdvancedErrorReportingCapIdReg
Definition: PCIExpress.h:131
uint32_t RootErrorCommandReg
Definition: PCIExpress.h:139
Definition: PCIExpress.h:37
temu_PCIExpressBus * SecondaryBus
Definition: PCIExpress.h:201
uint32_t PrefetchableLimitUpper
Definition: PCIExpress.h:78
uint32_t PowerManagementTimerReg
Definition: PCIExpress.h:108
Definition: PCIExpress.h:40
uint32_t ExpansionROMBaseAddress
Definition: PCIExpress.h:126
Definition: PCIExpress.h:53
Definition: PCIExpress.h:29
Definition: PCIExpress.h:50
uint32_t BAR0
Definition: PCIExpress.h:72
uint8_t SubBusId
Definition: PCIExpress.h:204
Definition: PCIExpress.h:46
uint32_t MemoryLimitBase
Definition: PCIExpress.h:75
uint32_t ClassCodeRevID
Definition: PCIExpress.h:123
Definition: PCIExpress.h:45
Definition: PCIExpress.h:32
Definition: PCIExpress.h:83
temu_PCIeControllerInternalCSRs PCIeController
Definition: PCIExpress.h:145
uint32_t MessageData
Definition: PCIExpress.h:102
Definition: PCIExpress.h:52
Definition: PCIExpress.h:43
Definition: PCIExpress.h:42
uint32_t PCIePointerCapabilities
Definition: PCIExpress.h:89
uint32_t UpperMessageAddress
Definition: PCIExpress.h:101
uint32_t PowerMgmtPointerCapabilities
Definition: PCIExpress.h:85
uint32_t SecondaryStatusIOLimitBase
Definition: PCIExpress.h:74
uint32_t DeviceVendorID
Definition: PCIExpress.h:121
Definition: PCIExpress.h:36
uint32_t StatusCommand
Definition: PCIExpress.h:122
uint8_t SecBusId
Definition: PCIExpress.h:203
uint32_t MaxLatMinGntIntPinLine
Definition: PCIExpress.h:65
uint32_t UncorrectableErrorStatusReg
Definition: PCIExpress.h:132
uint32_t BridgeCntrIntPinLine
Definition: PCIExpress.h:80
Definition: PCIExpress.h:41
temu_PCIExpressDeviceIfaceRefArray ChildrenDevs
Definition: PCIExpress.h:196
Definition: PCIExpress.h:44
temu_PCIExpressBridge * ParentDev
Definition: PCIExpress.h:195
temu_PCIeConfigType1 ConfigType1
Definition: PCIExpress.h:128
Definition: PCIExpress.h:191
Definition: PCIExpress.h:148
temu_PCIExpressConfig ExpressConf
Definition: PCIExpress.h:187
uint32_t FlowControlUpdateTimeoutReg
Definition: PCIExpress.h:112