TEMU  3.0
The Terma Emulator
PCIExpress.h
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1 //===------------------------------------------------------------*- C++ -*-===//
2 //
3 // TEMU: The Terma Emulator
4 // (c) Terma 2021
5 // Authors: Daria Vorotnikova <davo (at) terma.com>
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef TEMU_BUS_PCIe_H
10 #define TEMU_BUS_PCIe_H
11 #include <assert.h>
12 #include <stddef.h>
13 #include <stdint.h>
14 
15 #include "temu-c/Bus/PCIDefines.h"
16 #include "temu-c/Memory/Memory.h"
17 #include "temu-c/Support/Logging.h"
18 #include "temu-c/Support/Objsys.h"
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
28 typedef enum {
56 
61 typedef struct {
62  uint32_t BAR[6];
71 typedef struct {
72  uint32_t BAR0;
75  uint32_t MemoryLimitBase;
82 
83 typedef struct {
84  // Power Mgmt Capabilities |Next Pointer (0x4C)| Power Mgmt Capability ID
86  // Data | .. | Power Management Status & Control
88  // PCI Express Capabilities | Next Pointer | PCI Express Capability ID
92  uint32_t LinkCapabilities;
94  uint32_t SlotCapabilities; // RC mode only
95  uint32_t SlotStatusControl; // RC mode only
96  uint32_t RootControl; // RC mode only
97  uint32_t RootStatus;
98  // MSI Message Control | Next Pointer (NULL)| MSI Message Capability ID
100  uint32_t MessageAddress;
102  uint32_t MessageData;
104 
105 typedef struct {
109  uint32_t PMETimeOutReg;
119 typedef struct {
120  // PCI Compatible Configuration Header
121  uint32_t DeviceVendorID;
122  uint32_t StatusCommand;
123  uint32_t ClassCodeRevID;
125  uint32_t CapPointer;
129 
130  // PCI Express Extended Configuration Registers
138  uint32_t HeaderLogReg[4];
142 
144  PCIeDevConfig; // 0x40 to 0xFF via capabilities
147 
148 typedef struct {
149  void (*mapPciIo)(temu_Object *Obj, unsigned Device, unsigned Bar,
150  uint64_t Addr, uint64_t Len);
151  void (*unmapPciIo)(temu_Object *Obj, unsigned Device);
152  void (*mapPciMem)(temu_Object *Obj, unsigned Device, unsigned Bar,
153  uint64_t Addr, uint64_t Len);
154  void (*unmapPciMem)(temu_Object *Obj, unsigned Device);
157 #define TEMU_PCIe_BUS_IFACE_TYPE "temu::PCIExpressBusIface"
158 
159 typedef struct {
160  void (*raiseReset)(temu_Object *);
161  void (*lowerReset)(temu_Object *);
162  void (*connect)(temu_Object *, temu_Object *);
163  void (*disconnect)(temu_Object *, temu_Object *);
164  void (*sendMessage)(void *, temu_PCIeMessageTypes msgType, uint8_t *payload);
165  void (*setUpstreamBridge)(temu_Object *);
168 #define TEMU_PCIe_BRIDGE_IFACE_TYPE "temu::PCIExpressBridgeIface"
169 
170 typedef struct {
171  temu_PCIExpressConfig *(*getPciExpressConfig)(temu_Object *);
172  // Writes to config space forwarded here
173  void (*writeConfig)(temu_Object *, uint32_t offset, uint32_t value);
174  uint32_t (*readConfig)(temu_Object *, uint32_t offset);
175  uint64_t (*getPciExpressExpansionROMSize)(temu_Object *);
176  temu_MemAccessIface *(*getBARInterface)(temu_Object *, uint32_t index,
177  uint8_t type);
180 #define TEMU_PCIe_DEVICE_IFACE_TYPE "temu::PCIExpressDeviceIface"
181 
184 
185 typedef struct {
190 
193  uint8_t BusId;
194 
196  temu_PCIExpressDeviceIfaceRefArray ChildrenDevs;
197 };
198 
202  uint8_t PrimBusId;
203  uint8_t SecBusId;
204  uint8_t SubBusId;
205 };
206 
207 static inline temu_PCIExpressBus *
208 temu_pciGetRootBus(temu_PCIExpressDevice *device)
209 {
210  temu_PCIExpressBus *bus = device->PrimaryBus;
211 
212  while (bus->ParentDev != NULL) {
213  device = &bus->ParentDev->Super;
214  bus = device->PrimaryBus;
215  }
216  return bus;
217 }
218 static inline void
219 temu_pcieSetPrimaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
220 {
221  C->PrimBusId = Val;
222 }
223 static inline void
224 temu_pcieSetSecondaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
225 {
226  C->SecBusId = Val;
227 }
228 static inline void
229 temu_pcieSetSubordinaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
230 {
231  C->SubBusId = Val;
232 }
233 static inline void
234 temu_pcieSetBusId(temu_PCIExpressBus *C, uint8_t Val)
235 {
236  C->BusId = Val;
237 }
238 static inline void
239 temu_pcieSetDeviceId(temu_PCIExpressConfig *C, uint16_t Val)
240 {
241  C->DeviceVendorID = ((uint32_t)Val << 16) | (C->DeviceVendorID & 0xffff);
242 }
243 
244 static inline void
245 temu_pcieSetVendorId(temu_PCIExpressConfig *C, uint16_t Val)
246 {
247  C->DeviceVendorID = (uint32_t)Val | (C->DeviceVendorID & 0xffff0000);
248 }
249 
250 static inline void
251 temu_pcieSetStatus(temu_PCIExpressConfig *C, uint16_t Val)
252 {
253  C->StatusCommand = ((uint32_t)Val << 16) | (C->StatusCommand & 0xffff);
254 }
255 static inline uint16_t
256 temu_pcieReadStatus(temu_PCIExpressConfig *C)
257 {
258  return (uint16_t)((C->StatusCommand & 0xffff0000) >> 16);
259 }
260 
261 static inline void
262 temu_pcieSetClassCode(temu_PCIExpressConfig *C, uint32_t Val)
263 {
264  C->ClassCodeRevID &= 0x000000ff;
265  C->ClassCodeRevID |= Val << 8;
266 }
267 
268 static inline void
269 temu_pcieSetRevId(temu_PCIExpressConfig *C, uint8_t Val)
270 {
271  C->ClassCodeRevID &= 0xffffff00;
272  C->ClassCodeRevID |= Val;
273 }
274 
275 static inline void
276 temu_pcieSetBist(temu_PCIExpressConfig *C, uint8_t Val)
277 {
279  ((uint32_t)Val << 24) |
280  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0x00ffffff);
281 }
282 
283 static inline void
284 temu_pcieSetHeaderType(temu_PCIExpressConfig *C, uint8_t Val)
285 {
287  ((uint32_t)Val << 16) |
288  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xff00ffff);
289 }
290 
291 static inline void
292 temu_pcieSetLatencyTimer(temu_PCIExpressConfig *C, uint8_t Val)
293 {
295  ((uint32_t)Val << 8) |
296  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffff00ff);
297 }
298 
299 static inline void
300 temu_pcieSetCacheLineSize(temu_PCIExpressConfig *C, uint8_t Val)
301 {
303  ((uint32_t)Val << 0) |
304  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffffff00);
305 }
306 
307 static inline void
308 temu_pcieSetInterruptPin0(temu_PCIExpressConfig *C, uint8_t Val)
309 {
310  assert(Val < 0x05);
312  ((uint32_t)Val << 8) |
313  (C->ConfigType0.MaxLatMinGntIntPinLine & 0xffff00ff);
314 }
315 
316 static inline void
317 temu_pcieSetSubsystemId(temu_PCIExpressConfig *C, uint16_t Val)
318 {
320  (uint32_t)Val << 16 | (C->ConfigType0.SubsystemVendorID & 0x0000ffff);
321 }
322 
323 static inline void
324 temu_pcieSetSubsystemVendorId(temu_PCIExpressConfig *C, uint16_t Val)
325 {
327  (uint32_t)Val << 0 | (C->ConfigType0.SubsystemVendorID & 0xffff0000);
328 }
329 static inline void
330 temu_pcieSetPrimaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
331 {
333  (uint32_t)Val |
335 }
336 static inline void
337 temu_pcieSetSecondaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
338 {
340  ((uint32_t)Val << 8) |
342 }
343 static inline void
344 temu_pcieSetSubordinateBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
345 {
347  ((uint32_t)Val << 16) |
349 }
350 static inline void
351 temu_pcieSetIOBase(temu_PCIExpressConfig *C, uint8_t Val)
352 {
354  ((uint32_t)Val) |
355  (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffffff00);
356 }
357 static inline void
358 temu_pcieSetIOLimit(temu_PCIExpressConfig *C, uint8_t Val)
359 {
361  ((uint32_t)Val << 8) |
362  (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffff00ff);
363 }
364 static inline void
365 temu_pcieSetSecondaryStatus(temu_PCIExpressConfig *C, uint16_t Val)
366 {
368  ((uint32_t)Val << 16) |
369  (C->ConfigType1.SecondaryStatusIOLimitBase & 0x0000ffff);
370 }
371 static inline void
372 temu_pcieSetMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
373 {
375  ((uint32_t)Val) | (C->ConfigType1.MemoryLimitBase & 0xffff0000);
376 }
377 static inline void
378 temu_pcieSetMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
379 {
381  ((uint32_t)Val << 16) | (C->ConfigType1.MemoryLimitBase & 0x0000ffff);
382 }
383 static inline void
384 temu_pcieSetPrefetchableMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
385 {
387  ((uint32_t)Val) |
388  (C->ConfigType1.PrefetchableMemoryLimitBase & 0xffff0000);
389 }
390 static inline void
391 temu_pcieSetPrefetchableMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
392 {
394  ((uint32_t)Val << 16) |
395  (C->ConfigType1.PrefetchableMemoryLimitBase & 0x0000ffff);
396 }
397 static inline void
398 temu_pcieSetInterruptLine(temu_PCIExpressConfig *C, uint8_t Val)
399 {
401  ((uint32_t)Val) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffffff00);
402 }
403 static inline void
404 temu_pcieSetInterruptPin1(temu_PCIExpressConfig *C, uint8_t Val)
405 {
407  ((uint32_t)Val << 8) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffff00ff);
408 }
409 static inline void
410 temu_pcieSetBridgeControl(temu_PCIExpressConfig *C, uint16_t Val)
411 {
413  ((uint32_t)Val << 16) |
414  (C->ConfigType1.BridgeCntrIntPinLine & 0x0000ffff);
415 }
416 
417 static inline uint16_t
418 temu_pcieReadBridgeControl(temu_PCIExpressConfig *C)
419 {
420  return (uint16_t)((C->ConfigType1.BridgeCntrIntPinLine & 0xffff0000) >> 16);
421 }
422 
423 static inline uint32_t
424 temu_pcieReadConfigurationReadyReg(temu_PCIExpressConfig *C)
425 {
427 }
428 
429 static inline void
430 temu_pcieSetConfigurationReadyReg(temu_PCIExpressConfig *C, uint32_t Val)
431 {
433 }
434 
435 #ifdef __cplusplus
436 }
437 #endif
438 #endif // !TEMU_BUS_PCIe_H
uint32_t CorrectableErrorStatusReg
Definition: PCIExpress.h:135
uint32_t AdvancedErrorCapabilitiesControlReg
Definition: PCIExpress.h:137
uint32_t UncorrectableErrorSeverityReg
Definition: PCIExpress.h:134
#define TEMU_IFACE_REFERENCE_TYPE(N)
Definition: Objsys.h:180
uint32_t LTSSMStateStatusReg
Definition: PCIExpress.h:106
uint32_t DataPowerMgmtStatusControl
Definition: PCIExpress.h:87
temu_Object Super
Definition: PCIExpress.h:186
uint32_t SlotCapabilities
Definition: PCIExpress.h:94
uint8_t PrimBusId
Definition: PCIExpress.h:202
Definition: PCIExpress.h:33
Definition: PCIExpress.h:199
uint32_t SubsystemVendorID
Definition: PCIExpress.h:64
uint32_t LatencyTimer2SubBusNumBusNum2PrimBusNum
Definition: PCIExpress.h:73
Definition: PCIExpress.h:34
temu_PCIeMessageTypes
Definition: PCIExpress.h:28
Definition: PCIExpress.h:51
uint32_t MsgControlPointerMsgCapabilityID
Definition: PCIExpress.h:99
Definition: PCIExpress.h:61
Definition: PCIExpress.h:185
Definition: PCIExpress.h:105
uint32_t UpperIOLimitIOBase
Definition: PCIExpress.h:79
uint32_t ControllerCoreClockRatioReg
Definition: PCIExpress.h:107
uint32_t CardbusCISPointer
Definition: PCIExpress.h:63
temu_PCIExpressBus * PrimaryBus
Definition: PCIExpress.h:188
uint32_t CorrectableErrorMaskReg
Definition: PCIExpress.h:136
uint32_t SlotStatusControl
Definition: PCIExpress.h:95
Definition: PCIExpress.h:39
uint8_t BusId
Definition: PCIExpress.h:193
uint32_t UncorrectableErrorMaskReg
Definition: PCIExpress.h:133
temu_PCIExpressDevice Super
Definition: PCIExpress.h:200
uint32_t LinkCapabilities
Definition: PCIExpress.h:92
temu_Object Super
Definition: PCIExpress.h:192
Definition: PCIExpress.h:31
Definition: PCIExpress.h:47
uint32_t RootControl
Definition: PCIExpress.h:96
uint32_t DeviceStatusControl
Definition: PCIExpress.h:91
uint32_t SecondaryStatusIrqMaskReg
Definition: PCIExpress.h:113
uint32_t BISTHeaderTypeLatencyTimerCacheLineSize
Definition: PCIExpress.h:124
Definition: PCIExpress.h:119
Definition: PCIExpress.h:159
Definition: PCIExpress.h:48
uint32_t CapPointer
Definition: PCIExpress.h:125
temu_PCIeDeviceSpecificConfigSpace PCIeDevConfig
Definition: PCIExpress.h:144
Definition: PCIExpress.h:170
Definition: Memory.h:212
uint32_t MessageAddress
Definition: PCIExpress.h:100
Definition: PCIExpress.h:49
uint32_t PMETimeOutReg
Definition: PCIExpress.h:109
uint32_t CorrectableErrorSourceIdReg
Definition: PCIExpress.h:141
Definition: PCIExpress.h:38
uint32_t RootErrorStatusReg
Definition: PCIExpress.h:140
Definition: PCIExpress.h:30
uint32_t SubsystemVendorIDUpdateReg
Definition: PCIExpress.h:110
temu_PCIeConfigType0 ConfigType0
Definition: PCIExpress.h:127
uint32_t PrefetchableBaseUpper
Definition: PCIExpress.h:77
uint32_t DeviceCapabilities
Definition: PCIExpress.h:90
Definition: PCIExpress.h:54
uint32_t ConfigurationReadyReg
Definition: PCIExpress.h:111
Definition: PCIExpress.h:35
uint32_t RootStatus
Definition: PCIExpress.h:97
Definition: PCIExpress.h:71
uint32_t PrefetchableMemoryLimitBase
Definition: PCIExpress.h:76
uint32_t LinkStatusControl
Definition: PCIExpress.h:93
uint16_t AdvancedErrorReportingCapIdReg
Definition: PCIExpress.h:131
uint32_t RootErrorCommandReg
Definition: PCIExpress.h:139
Definition: PCIExpress.h:37
temu_PCIExpressBus * SecondaryBus
Definition: PCIExpress.h:201
uint32_t PrefetchableLimitUpper
Definition: PCIExpress.h:78
uint32_t PowerManagementTimerReg
Definition: PCIExpress.h:108
Definition: Objsys.h:82
Definition: PCIExpress.h:40
uint32_t ExpansionROMBaseAddress
Definition: PCIExpress.h:126
Definition: PCIExpress.h:53
Definition: PCIExpress.h:29
Definition: PCIExpress.h:50
uint32_t BAR0
Definition: PCIExpress.h:72
uint8_t SubBusId
Definition: PCIExpress.h:204
Definition: PCIExpress.h:46
uint32_t MemoryLimitBase
Definition: PCIExpress.h:75
uint32_t ClassCodeRevID
Definition: PCIExpress.h:123
Definition: PCIExpress.h:45
Definition: PCIExpress.h:32
Definition: PCIExpress.h:83
temu_PCIeControllerInternalCSRs PCIeController
Definition: PCIExpress.h:145
uint32_t MessageData
Definition: PCIExpress.h:102
Definition: PCIExpress.h:52
Definition: PCIExpress.h:43
Definition: PCIExpress.h:42
uint32_t PCIePointerCapabilities
Definition: PCIExpress.h:89
uint32_t UpperMessageAddress
Definition: PCIExpress.h:101
uint32_t PowerMgmtPointerCapabilities
Definition: PCIExpress.h:85
uint32_t SecondaryStatusIOLimitBase
Definition: PCIExpress.h:74
uint32_t DeviceVendorID
Definition: PCIExpress.h:121
Definition: PCIExpress.h:36
uint32_t StatusCommand
Definition: PCIExpress.h:122
uint8_t SecBusId
Definition: PCIExpress.h:203
uint32_t MaxLatMinGntIntPinLine
Definition: PCIExpress.h:65
uint32_t UncorrectableErrorStatusReg
Definition: PCIExpress.h:132
uint32_t BridgeCntrIntPinLine
Definition: PCIExpress.h:80
Definition: PCIExpress.h:41
temu_PCIExpressDeviceIfaceRefArray ChildrenDevs
Definition: PCIExpress.h:196
Definition: PCIExpress.h:44
temu_PCIExpressBridge * ParentDev
Definition: PCIExpress.h:195
temu_PCIeConfigType1 ConfigType1
Definition: PCIExpress.h:128
Definition: PCIExpress.h:191
Definition: PCIExpress.h:148
temu_PCIExpressConfig ExpressConf
Definition: PCIExpress.h:187
uint32_t FlowControlUpdateTimeoutReg
Definition: PCIExpress.h:112