10 #ifndef TEMU_TARGET_ARM_H 11 #define TEMU_TARGET_ARM_H 36 uint32_t (*getBankedRegister)(
void *Obj,
temu_ARMMode Mode,
unsigned Reg);
41 uint32_t (*getAPSR)(
void *Obj);
42 void (*setAPSR)(
void *Obj, uint32_t Value);
44 uint32_t (*getFpscr)(
const void *Cpu);
45 void (*setFpscr)(
void *Cpu, uint32_t Value);
47 uint32_t (*getFpexc)(
const void *Cpu);
48 void (*setFpexc)(
void *Cpu, uint32_t Value);
50 uint32_t (*getFpinst)(
const void *Cpu,
int idx);
51 void (*setFpinst)(
void *Cpu,
int idx, uint32_t Value);
53 #define TEMU_ARM_CPU_IFACE_TYPE "ARMCpu" 58 uint8_t (*accepts)(
void *Obj, uint32_t cp, uint32_t instr);
60 uint32_t (*getOneWord)(
void *Obj, uint32_t cp, uint32_t instr);
62 uint64_t (*getTwoWords)(
void *Obj, uint32_t cp, uint32_t instr);
63 void (*sendOneWord)(
void *Obj, uint32_t t, uint32_t cp, uint32_t instr);
64 void (*sendTwoWords)(
void *Obj, uint32_t t2, uint32_t t, uint32_t cp, uint32_t instr);
67 #define TEMU_ARM_COPROC_IFACE_TYPE "ARMCoProcessor" Undefined 0b11011 0b1b 27.
Definition: ARM.h:23
User 0b10000 0x10 16.
Definition: ARM.h:16
Processor is in Jazelle mode.
Definition: ARM.h:30
Fast irq 0b10001 0x11 17.
Definition: ARM.h:17
Processor is in ARM mode.
Definition: ARM.h:28
Processor is in Thumb mode.
Definition: ARM.h:29
Supervisor 0b10011 0x13 19.
Definition: ARM.h:19
Processor is in Thumb EE mode.
Definition: ARM.h:31
Hypervisor 0b11010 0x1a 26.
Definition: ARM.h:22
System 0b11111 0b1f 31.
Definition: ARM.h:24
Interrupt 0b10010 0x12 18.
Definition: ARM.h:18
Abort 0b10111 0x15 21.
Definition: ARM.h:21
temu_ARMMode
Definition: ARM.h:15
Monitor 0b10110 0x14 20.
Definition: ARM.h:20
temu_ARMExecMode
Definition: ARM.h:27
TEMU_IFACE_REFERENCE_TYPE(temu_ARMCpu)