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TEMU
4.0
The Terma Emulator
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9 #ifndef TEMU_BUS_PCIe_H
10 #define TEMU_BUS_PCIe_H
15 #include "temu-c/Bus/PCIDefines.h"
16 #include "temu-c/Memory/Memory.h"
17 #include "temu-c/Support/Logging.h"
18 #include "temu-c/Support/Objsys.h"
55 } temu_PCIeMessageTypes;
66 } temu_PCIeConfigType0;
81 } temu_PCIeConfigType1;
103 } temu_PCIeDeviceSpecificConfigSpace;
114 } temu_PCIeControllerInternalCSRs;
143 temu_PCIeDeviceSpecificConfigSpace
146 } temu_PCIExpressConfig;
149 void (*
mapPciIo)(temu_Object *Obj,
unsigned Device,
unsigned Bar,
150 uint64_t Addr, uint64_t Len);
152 void (*
mapPciMem)(temu_Object *Obj,
unsigned Device,
unsigned Bar,
153 uint64_t Addr, uint64_t Len);
155 } temu_PCIExpressBusIface;
156 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressBus)
157 #define TEMU_PCIe_BUS_IFACE_TYPE "temu::PCIExpressBusIface"
164 void (*
sendMessage)(
void *, temu_PCIeMessageTypes msgType, uint8_t *payload);
166 } temu_PCIExpressBridgeIface;
167 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressBridge)
168 #define TEMU_PCIe_BRIDGE_IFACE_TYPE "temu::PCIExpressBridgeIface"
171 temu_PCIExpressConfig *(*getPciExpressConfig)(temu_Object *);
174 uint32_t (*readConfig)(temu_Object *, uint32_t offset);
175 uint64_t (*getPciExpressExpansionROMSize)(temu_Object *);
178 } temu_PCIExpressDeviceIface;
179 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressDevice)
180 #define TEMU_PCIe_DEVICE_IFACE_TYPE "temu::PCIExpressDeviceIface"
189 } temu_PCIExpressDevice;
207 static inline temu_PCIExpressBus *
208 temu_pciGetRootBus(temu_PCIExpressDevice *device)
210 temu_PCIExpressBus *bus = device->PrimaryBus;
212 while (bus->ParentDev != NULL) {
213 device = &bus->ParentDev->Super;
214 bus = device->PrimaryBus;
220 temu_pcieSetPrimaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
225 temu_pcieSetSecondaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
230 temu_pcieSetSubordinaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
236 temu_pcieSetBusId(temu_PCIExpressBus *C, uint8_t Val)
241 temu_pcieSetDeviceId(temu_PCIExpressConfig *C, uint16_t Val)
243 C->DeviceVendorID = ((uint32_t)Val << 16) | (C->DeviceVendorID & 0xffff);
247 temu_pcieSetVendorId(temu_PCIExpressConfig *C, uint16_t Val)
249 C->DeviceVendorID = (uint32_t)Val | (C->DeviceVendorID & 0xffff0000);
253 temu_pcieSetStatus(temu_PCIExpressConfig *C, uint16_t Val)
255 C->StatusCommand = ((uint32_t)Val << 16) | (C->StatusCommand & 0xffff);
257 static inline uint16_t
258 temu_pcieReadStatus(temu_PCIExpressConfig *C)
260 return (uint16_t)((C->StatusCommand & 0xffff0000) >> 16);
264 temu_pcieSetClassCode(temu_PCIExpressConfig *C, uint32_t Val)
266 C->ClassCodeRevID &= 0x000000ff;
267 C->ClassCodeRevID |= Val << 8;
271 temu_pcieSetRevId(temu_PCIExpressConfig *C, uint8_t Val)
273 C->ClassCodeRevID &= 0xffffff00;
274 C->ClassCodeRevID |= Val;
278 temu_pcieSetBist(temu_PCIExpressConfig *C, uint8_t Val)
280 C->BISTHeaderTypeLatencyTimerCacheLineSize =
281 ((uint32_t)Val << 24) |
282 (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0x00ffffff);
286 temu_pcieSetHeaderType(temu_PCIExpressConfig *C, uint8_t Val)
288 C->BISTHeaderTypeLatencyTimerCacheLineSize =
289 ((uint32_t)Val << 16) |
290 (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xff00ffff);
294 temu_pcieSetLatencyTimer(temu_PCIExpressConfig *C, uint8_t Val)
296 C->BISTHeaderTypeLatencyTimerCacheLineSize =
297 ((uint32_t)Val << 8) |
298 (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffff00ff);
302 temu_pcieSetCacheLineSize(temu_PCIExpressConfig *C, uint8_t Val)
304 C->BISTHeaderTypeLatencyTimerCacheLineSize =
305 ((uint32_t)Val << 0) |
306 (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffffff00);
310 temu_pcieSetInterruptPin0(temu_PCIExpressConfig *C, uint8_t Val)
313 C->ConfigType0.MaxLatMinGntIntPinLine =
314 ((uint32_t)Val << 8) |
315 (C->ConfigType0.MaxLatMinGntIntPinLine & 0xffff00ff);
319 temu_pcieSetSubsystemId(temu_PCIExpressConfig *C, uint16_t Val)
321 C->ConfigType0.SubsystemVendorID =
322 (uint32_t)Val << 16 | (C->ConfigType0.SubsystemVendorID & 0x0000ffff);
326 temu_pcieSetSubsystemVendorId(temu_PCIExpressConfig *C, uint16_t Val)
328 C->ConfigType0.SubsystemVendorID =
329 (uint32_t)Val << 0 | (C->ConfigType0.SubsystemVendorID & 0xffff0000);
332 temu_pcieSetPrimaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
334 C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
336 (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xffffff00);
339 temu_pcieSetSecondaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
341 C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
342 ((uint32_t)Val << 8) |
343 (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xffff00ff);
346 temu_pcieSetSubordinateBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
348 C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
349 ((uint32_t)Val << 16) |
350 (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xff00ffff);
353 temu_pcieSetIOBase(temu_PCIExpressConfig *C, uint8_t Val)
355 C->ConfigType1.SecondaryStatusIOLimitBase =
357 (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffffff00);
360 temu_pcieSetIOLimit(temu_PCIExpressConfig *C, uint8_t Val)
362 C->ConfigType1.SecondaryStatusIOLimitBase =
363 ((uint32_t)Val << 8) |
364 (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffff00ff);
367 temu_pcieSetSecondaryStatus(temu_PCIExpressConfig *C, uint16_t Val)
369 C->ConfigType1.SecondaryStatusIOLimitBase =
370 ((uint32_t)Val << 16) |
371 (C->ConfigType1.SecondaryStatusIOLimitBase & 0x0000ffff);
374 temu_pcieSetMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
376 C->ConfigType1.MemoryLimitBase =
377 ((uint32_t)Val) | (C->ConfigType1.MemoryLimitBase & 0xffff0000);
380 temu_pcieSetMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
382 C->ConfigType1.MemoryLimitBase =
383 ((uint32_t)Val << 16) | (C->ConfigType1.MemoryLimitBase & 0x0000ffff);
386 temu_pcieSetPrefetchableMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
388 C->ConfigType1.PrefetchableMemoryLimitBase =
390 (C->ConfigType1.PrefetchableMemoryLimitBase & 0xffff0000);
393 temu_pcieSetPrefetchableMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
395 C->ConfigType1.PrefetchableMemoryLimitBase =
396 ((uint32_t)Val << 16) |
397 (C->ConfigType1.PrefetchableMemoryLimitBase & 0x0000ffff);
400 temu_pcieSetInterruptLine(temu_PCIExpressConfig *C, uint8_t Val)
402 C->ConfigType1.BridgeCntrIntPinLine =
403 ((uint32_t)Val) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffffff00);
406 temu_pcieSetInterruptPin1(temu_PCIExpressConfig *C, uint8_t Val)
408 C->ConfigType1.BridgeCntrIntPinLine =
409 ((uint32_t)Val << 8) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffff00ff);
412 temu_pcieSetBridgeControl(temu_PCIExpressConfig *C, uint16_t Val)
414 C->ConfigType1.BridgeCntrIntPinLine =
415 ((uint32_t)Val << 16) |
416 (C->ConfigType1.BridgeCntrIntPinLine & 0x0000ffff);
419 static inline uint16_t
420 temu_pcieReadBridgeControl(temu_PCIExpressConfig *C)
422 return (uint16_t)((C->ConfigType1.BridgeCntrIntPinLine & 0xffff0000) >> 16);
425 static inline uint32_t
426 temu_pcieReadConfigurationReadyReg(temu_PCIExpressConfig *C)
428 return C->PCIeController.ConfigurationReadyReg;
432 temu_pcieSetConfigurationReadyReg(temu_PCIExpressConfig *C, uint32_t Val)
434 C->PCIeController.ConfigurationReadyReg = Val;
uint32_t ConfigurationReadyReg
Definition: PCIExpress.h:111
void(* unmapPciMem)(temu_Object *Obj, unsigned Device)
Definition: PCIExpress.h:154
uint32_t UpperIOLimitIOBase
Definition: PCIExpress.h:79
void(* disconnect)(temu_Object *, temu_Object *)
Definition: PCIExpress.h:163
uint32_t MsgControlPointerMsgCapabilityID
Definition: PCIExpress.h:99
uint32_t PMETimeOutReg
Definition: PCIExpress.h:109
uint8_t SecBusId
Definition: PCIExpress.h:203
uint32_t SlotStatusControl
Definition: PCIExpress.h:95
uint32_t LinkStatusControl
Definition: PCIExpress.h:93
uint32_t BAR0
Definition: PCIExpress.h:72
void(* raiseReset)(temu_Object *)
Definition: PCIExpress.h:160
void(* mapPciMem)(temu_Object *Obj, unsigned Device, unsigned Bar, uint64_t Addr, uint64_t Len)
Definition: PCIExpress.h:152
void(* writeConfig)(temu_Object *, uint32_t offset, uint32_t value)
Definition: PCIExpress.h:173
uint32_t BISTHeaderTypeLatencyTimerCacheLineSize
Definition: PCIExpress.h:124
uint32_t StatusCommand
Definition: PCIExpress.h:122
@ tePMT_PowerIndicatorOn
Definition: PCIExpress.h:51
@ tePMT_DeassertIntA
Definition: PCIExpress.h:33
uint32_t UncorrectableErrorMaskReg
Definition: PCIExpress.h:133
void(* mapPciIo)(temu_Object *Obj, unsigned Device, unsigned Bar, uint64_t Addr, uint64_t Len)
Definition: PCIExpress.h:149
temu_PCIeDeviceSpecificConfigSpace PCIeDevConfig
Definition: PCIExpress.h:144
uint8_t PrimBusId
Definition: PCIExpress.h:202
temu_MemAccessIface *(* getBARInterface)(temu_Object *, uint32_t index, uint8_t type)
Definition: PCIExpress.h:176
uint32_t PowerMgmtPointerCapabilities
Definition: PCIExpress.h:85
uint32_t DeviceStatusControl
Definition: PCIExpress.h:91
@ tePMT_DeassertIntB
Definition: PCIExpress.h:34
temu_Object Super
Definition: PCIExpress.h:186
uint32_t PCIePointerCapabilities
Definition: PCIExpress.h:89
@ tePMT_VendorDefinedType1
Definition: PCIExpress.h:47
temu_PCIExpressBus * PrimaryBus
Definition: PCIExpress.h:188
void(* lowerReset)(temu_Object *)
Definition: PCIExpress.h:161
void(* unmapPciIo)(temu_Object *Obj, unsigned Device)
Definition: PCIExpress.h:151
uint16_t AdvancedErrorReportingCapIdReg
Definition: PCIExpress.h:131
uint32_t MessageData
Definition: PCIExpress.h:102
uint32_t UncorrectableErrorStatusReg
Definition: PCIExpress.h:132
uint32_t AdvancedErrorCapabilitiesControlReg
Definition: PCIExpress.h:137
uint32_t SecondaryStatusIOLimitBase
Definition: PCIExpress.h:74
uint32_t ControllerCoreClockRatioReg
Definition: PCIExpress.h:107
uint32_t ExpansionROMBaseAddress
Definition: PCIExpress.h:126
temu_PCIExpressDevice Super
Definition: PCIExpress.h:200
uint32_t ClassCodeRevID
Definition: PCIExpress.h:123
@ tePMT_PmPme
Definition: PCIExpress.h:38
temu_PCIeConfigType1 ConfigType1
Definition: PCIExpress.h:128
@ tePMT_AttentionButtonPressed
Definition: PCIExpress.h:54
@ tePMT_DeassertIntC
Definition: PCIExpress.h:35
uint32_t RootErrorCommandReg
Definition: PCIExpress.h:139
uint32_t MemoryLimitBase
Definition: PCIExpress.h:75
@ tePMT_PmActiveStateNak
Definition: PCIExpress.h:37
uint32_t LTSSMStateStatusReg
Definition: PCIExpress.h:106
@ tePMT_PowerIndicatorOff
Definition: PCIExpress.h:53
@ tePMT_PmeTurnOff
Definition: PCIExpress.h:39
uint32_t LatencyTimer2SubBusNumBusNum2PrimBusNum
Definition: PCIExpress.h:73
@ tePMT_VendorDefinedType0
Definition: PCIExpress.h:46
@ tePMT_AssertIntC
Definition: PCIExpress.h:31
uint32_t HeaderLogReg[4]
Definition: PCIExpress.h:138
temu_PCIeControllerInternalCSRs PCIeController
Definition: PCIExpress.h:145
uint32_t DataPowerMgmtStatusControl
Definition: PCIExpress.h:87
uint32_t DeviceCapabilities
Definition: PCIExpress.h:90
void(* setUpstreamBridge)(temu_Object *)
Definition: PCIExpress.h:165
uint32_t PowerManagementTimerReg
Definition: PCIExpress.h:108
@ tePMT_AssertIntB
Definition: PCIExpress.h:30
uint32_t DeviceVendorID
Definition: PCIExpress.h:121
temu_Object Super
Definition: PCIExpress.h:192
@ tePMT_AssertIntA
Definition: PCIExpress.h:29
uint32_t SubsystemVendorIDUpdateReg
Definition: PCIExpress.h:110
@ tePMT_AttentionIndicatorOn
Definition: PCIExpress.h:48
uint32_t PrefetchableLimitUpper
Definition: PCIExpress.h:78
uint32_t CapPointer
Definition: PCIExpress.h:125
uint32_t PrefetchableMemoryLimitBase
Definition: PCIExpress.h:76
uint32_t UncorrectableErrorSeverityReg
Definition: PCIExpress.h:134
@ tePMT_AttentionIndicatorBlink
Definition: PCIExpress.h:49
temu_PCIExpressBus * SecondaryBus
Definition: PCIExpress.h:201
uint32_t CorrectableErrorSourceIdReg
Definition: PCIExpress.h:141
temu_PCIExpressBridge * ParentDev
Definition: PCIExpress.h:195
@ tePMT_AssertIntD
Definition: PCIExpress.h:32
@ tePMT_ErrFatal
Definition: PCIExpress.h:43
uint32_t SubsystemVendorID
Definition: PCIExpress.h:64
void(* sendMessage)(void *, temu_PCIeMessageTypes msgType, uint8_t *payload)
Definition: PCIExpress.h:164
temu_PCIeConfigType0 ConfigType0
Definition: PCIExpress.h:127
uint32_t SlotCapabilities
Definition: PCIExpress.h:94
uint32_t RootControl
Definition: PCIExpress.h:96
uint8_t SubBusId
Definition: PCIExpress.h:204
uint32_t CardbusCISPointer
Definition: PCIExpress.h:63
void(* connect)(temu_Object *, temu_Object *)
Definition: PCIExpress.h:162
struct temu_PCIExpressBridge temu_PCIExpressBridge
Definition: PCIExpress.h:183
struct temu_PCIExpressBus temu_PCIExpressBus
Definition: PCIExpress.h:182
@ tePMT_PmToAck
Definition: PCIExpress.h:40
uint32_t CorrectableErrorMaskReg
Definition: PCIExpress.h:136
@ tePMT_AttentionIndicatorOff
Definition: PCIExpress.h:50
temu_PCIExpressDeviceIfaceRefArray ChildrenDevs
Definition: PCIExpress.h:196
uint32_t PrefetchableBaseUpper
Definition: PCIExpress.h:77
@ tePMT_ErrCor
Definition: PCIExpress.h:41
uint32_t FlowControlUpdateTimeoutReg
Definition: PCIExpress.h:112
uint32_t RootStatus
Definition: PCIExpress.h:97
uint32_t BridgeCntrIntPinLine
Definition: PCIExpress.h:80
temu_PCIExpressConfig ExpressConf
Definition: PCIExpress.h:187
@ tePMT_SetSlotPowerLimit
Definition: PCIExpress.h:45
uint32_t CorrectableErrorStatusReg
Definition: PCIExpress.h:135
uint32_t LinkCapabilities
Definition: PCIExpress.h:92
@ tePMT_PowerIndicatorBlink
Definition: PCIExpress.h:52
uint8_t BusId
Definition: PCIExpress.h:193
uint32_t MaxLatMinGntIntPinLine
Definition: PCIExpress.h:65
@ tePMT_Unlock
Definition: PCIExpress.h:44
uint32_t UpperMessageAddress
Definition: PCIExpress.h:101
uint32_t BAR[6]
Definition: PCIExpress.h:62
uint32_t RootErrorStatusReg
Definition: PCIExpress.h:140
uint32_t MessageAddress
Definition: PCIExpress.h:100
@ tePMT_ErrNonFatal
Definition: PCIExpress.h:42
uint32_t SecondaryStatusIrqMaskReg
Definition: PCIExpress.h:113
@ tePMT_DeassertIntD
Definition: PCIExpress.h:36