TEMU  4.0
The Terma Emulator
PCIExpress.h
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1 //===------------------------------------------------------------*- C++ -*-===//
2 //
3 // TEMU: The Terma Emulator
4 // (c) Terma 2021
5 // Authors: Daria Vorotnikova <davo (at) terma.com>
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef TEMU_BUS_PCIe_H
10 #define TEMU_BUS_PCIe_H
11 #include <assert.h>
12 #include <stddef.h>
13 #include <stdint.h>
14 
15 #include "temu-c/Bus/PCIDefines.h"
16 #include "temu-c/Memory/Memory.h"
17 #include "temu-c/Support/Logging.h"
18 #include "temu-c/Support/Objsys.h"
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 /**
24  * temu_PCIeMessageTypes:
25  * PCI Express Messages
26  * name = code
27  */
28 typedef enum {
55 } temu_PCIeMessageTypes;
56 
57 /**
58  * temu_PCIeConfigType0:
59  * Fields that exists only in config type 0
60  */
61 typedef struct {
62  uint32_t BAR[6];
66 } temu_PCIeConfigType0;
67 /**
68  * temu_PCIeConfigType1:
69  * Fields that exists only in config type 1
70  */
71 typedef struct {
72  uint32_t BAR0;
75  uint32_t MemoryLimitBase;
81 } temu_PCIeConfigType1;
82 
83 typedef struct {
84  // Power Mgmt Capabilities |Next Pointer (0x4C)| Power Mgmt Capability ID
86  // Data | .. | Power Management Status & Control
88  // PCI Express Capabilities | Next Pointer | PCI Express Capability ID
92  uint32_t LinkCapabilities;
94  uint32_t SlotCapabilities; // RC mode only
95  uint32_t SlotStatusControl; // RC mode only
96  uint32_t RootControl; // RC mode only
97  uint32_t RootStatus;
98  // MSI Message Control | Next Pointer (NULL)| MSI Message Capability ID
100  uint32_t MessageAddress;
102  uint32_t MessageData;
103 } temu_PCIeDeviceSpecificConfigSpace;
104 
105 typedef struct {
109  uint32_t PMETimeOutReg;
114 } temu_PCIeControllerInternalCSRs;
115 /**
116  * temu_PCIExpressConfig:
117  * PCI Express configuration space registers
118  */
119 typedef struct {
120  // PCI Compatible Configuration Header
121  uint32_t DeviceVendorID;
122  uint32_t StatusCommand;
123  uint32_t ClassCodeRevID;
125  uint32_t CapPointer;
127  temu_PCIeConfigType0 ConfigType0;
128  temu_PCIeConfigType1 ConfigType1;
129 
130  // PCI Express Extended Configuration Registers
138  uint32_t HeaderLogReg[4];
142 
143  temu_PCIeDeviceSpecificConfigSpace
144  PCIeDevConfig; // 0x40 to 0xFF via capabilities
145  temu_PCIeControllerInternalCSRs PCIeController;
146 } temu_PCIExpressConfig;
147 
148 typedef struct {
149  void (*mapPciIo)(temu_Object *Obj, unsigned Device, unsigned Bar,
150  uint64_t Addr, uint64_t Len);
151  void (*unmapPciIo)(temu_Object *Obj, unsigned Device);
152  void (*mapPciMem)(temu_Object *Obj, unsigned Device, unsigned Bar,
153  uint64_t Addr, uint64_t Len);
154  void (*unmapPciMem)(temu_Object *Obj, unsigned Device);
155 } temu_PCIExpressBusIface;
156 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressBus)
157 #define TEMU_PCIe_BUS_IFACE_TYPE "temu::PCIExpressBusIface"
158 
159 typedef struct {
164  void (*sendMessage)(void *, temu_PCIeMessageTypes msgType, uint8_t *payload);
166 } temu_PCIExpressBridgeIface;
167 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressBridge)
168 #define TEMU_PCIe_BRIDGE_IFACE_TYPE "temu::PCIExpressBridgeIface"
169 
170 typedef struct {
171  temu_PCIExpressConfig *(*getPciExpressConfig)(temu_Object *);
172  // Writes to config space forwarded here
173  void (*writeConfig)(temu_Object *, uint32_t offset, uint32_t value);
174  uint32_t (*readConfig)(temu_Object *, uint32_t offset);
175  uint64_t (*getPciExpressExpansionROMSize)(temu_Object *);
177  uint8_t type);
178 } temu_PCIExpressDeviceIface;
179 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressDevice)
180 #define TEMU_PCIe_DEVICE_IFACE_TYPE "temu::PCIExpressDeviceIface"
181 
182 typedef struct temu_PCIExpressBus temu_PCIExpressBus;
183 typedef struct temu_PCIExpressBridge temu_PCIExpressBridge;
184 
185 typedef struct {
187  temu_PCIExpressConfig ExpressConf;
188  temu_PCIExpressBus *PrimaryBus;
189 } temu_PCIExpressDevice;
190 
193  uint8_t BusId;
194 
195  temu_PCIExpressBridge *ParentDev;
197 };
198 
201  temu_PCIExpressBus *SecondaryBus;
202  uint8_t PrimBusId;
203  uint8_t SecBusId;
204  uint8_t SubBusId;
205 };
206 
207 static inline temu_PCIExpressBus *
208 temu_pciGetRootBus(temu_PCIExpressDevice *device)
209 {
210  temu_PCIExpressBus *bus = device->PrimaryBus;
211 
212  while (bus->ParentDev != NULL) {
213  device = &bus->ParentDev->Super;
214  bus = device->PrimaryBus;
215  }
216  return bus;
217 }
218 
219 static inline void
220 temu_pcieSetPrimaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
221 {
222  C->PrimBusId = Val;
223 }
224 static inline void
225 temu_pcieSetSecondaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
226 {
227  C->SecBusId = Val;
228 }
229 static inline void
230 temu_pcieSetSubordinaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
231 {
232  C->SubBusId = Val;
233 }
234 
235 static inline void
236 temu_pcieSetBusId(temu_PCIExpressBus *C, uint8_t Val)
237 {
238  C->BusId = Val;
239 }
240 static inline void
241 temu_pcieSetDeviceId(temu_PCIExpressConfig *C, uint16_t Val)
242 {
243  C->DeviceVendorID = ((uint32_t)Val << 16) | (C->DeviceVendorID & 0xffff);
244 }
245 
246 static inline void
247 temu_pcieSetVendorId(temu_PCIExpressConfig *C, uint16_t Val)
248 {
249  C->DeviceVendorID = (uint32_t)Val | (C->DeviceVendorID & 0xffff0000);
250 }
251 
252 static inline void
253 temu_pcieSetStatus(temu_PCIExpressConfig *C, uint16_t Val)
254 {
255  C->StatusCommand = ((uint32_t)Val << 16) | (C->StatusCommand & 0xffff);
256 }
257 static inline uint16_t
258 temu_pcieReadStatus(temu_PCIExpressConfig *C)
259 {
260  return (uint16_t)((C->StatusCommand & 0xffff0000) >> 16);
261 }
262 
263 static inline void
264 temu_pcieSetClassCode(temu_PCIExpressConfig *C, uint32_t Val)
265 {
266  C->ClassCodeRevID &= 0x000000ff;
267  C->ClassCodeRevID |= Val << 8;
268 }
269 
270 static inline void
271 temu_pcieSetRevId(temu_PCIExpressConfig *C, uint8_t Val)
272 {
273  C->ClassCodeRevID &= 0xffffff00;
274  C->ClassCodeRevID |= Val;
275 }
276 
277 static inline void
278 temu_pcieSetBist(temu_PCIExpressConfig *C, uint8_t Val)
279 {
280  C->BISTHeaderTypeLatencyTimerCacheLineSize =
281  ((uint32_t)Val << 24) |
282  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0x00ffffff);
283 }
284 
285 static inline void
286 temu_pcieSetHeaderType(temu_PCIExpressConfig *C, uint8_t Val)
287 {
288  C->BISTHeaderTypeLatencyTimerCacheLineSize =
289  ((uint32_t)Val << 16) |
290  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xff00ffff);
291 }
292 
293 static inline void
294 temu_pcieSetLatencyTimer(temu_PCIExpressConfig *C, uint8_t Val)
295 {
296  C->BISTHeaderTypeLatencyTimerCacheLineSize =
297  ((uint32_t)Val << 8) |
298  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffff00ff);
299 }
300 
301 static inline void
302 temu_pcieSetCacheLineSize(temu_PCIExpressConfig *C, uint8_t Val)
303 {
304  C->BISTHeaderTypeLatencyTimerCacheLineSize =
305  ((uint32_t)Val << 0) |
306  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffffff00);
307 }
308 
309 static inline void
310 temu_pcieSetInterruptPin0(temu_PCIExpressConfig *C, uint8_t Val)
311 {
312  assert(Val < 0x05);
313  C->ConfigType0.MaxLatMinGntIntPinLine =
314  ((uint32_t)Val << 8) |
315  (C->ConfigType0.MaxLatMinGntIntPinLine & 0xffff00ff);
316 }
317 
318 static inline void
319 temu_pcieSetSubsystemId(temu_PCIExpressConfig *C, uint16_t Val)
320 {
321  C->ConfigType0.SubsystemVendorID =
322  (uint32_t)Val << 16 | (C->ConfigType0.SubsystemVendorID & 0x0000ffff);
323 }
324 
325 static inline void
326 temu_pcieSetSubsystemVendorId(temu_PCIExpressConfig *C, uint16_t Val)
327 {
328  C->ConfigType0.SubsystemVendorID =
329  (uint32_t)Val << 0 | (C->ConfigType0.SubsystemVendorID & 0xffff0000);
330 }
331 static inline void
332 temu_pcieSetPrimaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
333 {
334  C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
335  (uint32_t)Val |
336  (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xffffff00);
337 }
338 static inline void
339 temu_pcieSetSecondaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
340 {
341  C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
342  ((uint32_t)Val << 8) |
343  (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xffff00ff);
344 }
345 static inline void
346 temu_pcieSetSubordinateBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
347 {
348  C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
349  ((uint32_t)Val << 16) |
350  (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xff00ffff);
351 }
352 static inline void
353 temu_pcieSetIOBase(temu_PCIExpressConfig *C, uint8_t Val)
354 {
355  C->ConfigType1.SecondaryStatusIOLimitBase =
356  ((uint32_t)Val) |
357  (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffffff00);
358 }
359 static inline void
360 temu_pcieSetIOLimit(temu_PCIExpressConfig *C, uint8_t Val)
361 {
362  C->ConfigType1.SecondaryStatusIOLimitBase =
363  ((uint32_t)Val << 8) |
364  (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffff00ff);
365 }
366 static inline void
367 temu_pcieSetSecondaryStatus(temu_PCIExpressConfig *C, uint16_t Val)
368 {
369  C->ConfigType1.SecondaryStatusIOLimitBase =
370  ((uint32_t)Val << 16) |
371  (C->ConfigType1.SecondaryStatusIOLimitBase & 0x0000ffff);
372 }
373 static inline void
374 temu_pcieSetMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
375 {
376  C->ConfigType1.MemoryLimitBase =
377  ((uint32_t)Val) | (C->ConfigType1.MemoryLimitBase & 0xffff0000);
378 }
379 static inline void
380 temu_pcieSetMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
381 {
382  C->ConfigType1.MemoryLimitBase =
383  ((uint32_t)Val << 16) | (C->ConfigType1.MemoryLimitBase & 0x0000ffff);
384 }
385 static inline void
386 temu_pcieSetPrefetchableMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
387 {
388  C->ConfigType1.PrefetchableMemoryLimitBase =
389  ((uint32_t)Val) |
390  (C->ConfigType1.PrefetchableMemoryLimitBase & 0xffff0000);
391 }
392 static inline void
393 temu_pcieSetPrefetchableMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
394 {
395  C->ConfigType1.PrefetchableMemoryLimitBase =
396  ((uint32_t)Val << 16) |
397  (C->ConfigType1.PrefetchableMemoryLimitBase & 0x0000ffff);
398 }
399 static inline void
400 temu_pcieSetInterruptLine(temu_PCIExpressConfig *C, uint8_t Val)
401 {
402  C->ConfigType1.BridgeCntrIntPinLine =
403  ((uint32_t)Val) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffffff00);
404 }
405 static inline void
406 temu_pcieSetInterruptPin1(temu_PCIExpressConfig *C, uint8_t Val)
407 {
408  C->ConfigType1.BridgeCntrIntPinLine =
409  ((uint32_t)Val << 8) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffff00ff);
410 }
411 static inline void
412 temu_pcieSetBridgeControl(temu_PCIExpressConfig *C, uint16_t Val)
413 {
414  C->ConfigType1.BridgeCntrIntPinLine =
415  ((uint32_t)Val << 16) |
416  (C->ConfigType1.BridgeCntrIntPinLine & 0x0000ffff);
417 }
418 
419 static inline uint16_t
420 temu_pcieReadBridgeControl(temu_PCIExpressConfig *C)
421 {
422  return (uint16_t)((C->ConfigType1.BridgeCntrIntPinLine & 0xffff0000) >> 16);
423 }
424 
425 static inline uint32_t
426 temu_pcieReadConfigurationReadyReg(temu_PCIExpressConfig *C)
427 {
428  return C->PCIeController.ConfigurationReadyReg;
429 }
430 
431 static inline void
432 temu_pcieSetConfigurationReadyReg(temu_PCIExpressConfig *C, uint32_t Val)
433 {
434  C->PCIeController.ConfigurationReadyReg = Val;
435 }
436 
437 #ifdef __cplusplus
438 }
439 #endif
440 #endif // !TEMU_BUS_PCIe_H
temu_PCIeControllerInternalCSRs::ConfigurationReadyReg
uint32_t ConfigurationReadyReg
Definition: PCIExpress.h:111
temu_PCIExpressBusIface::unmapPciMem
void(* unmapPciMem)(temu_Object *Obj, unsigned Device)
Definition: PCIExpress.h:154
temu_PCIeConfigType1::UpperIOLimitIOBase
uint32_t UpperIOLimitIOBase
Definition: PCIExpress.h:79
temu_PCIExpressBridgeIface::disconnect
void(* disconnect)(temu_Object *, temu_Object *)
Definition: PCIExpress.h:163
temu_PCIeDeviceSpecificConfigSpace::MsgControlPointerMsgCapabilityID
uint32_t MsgControlPointerMsgCapabilityID
Definition: PCIExpress.h:99
temu_PCIeControllerInternalCSRs::PMETimeOutReg
uint32_t PMETimeOutReg
Definition: PCIExpress.h:109
temu_PCIExpressBridge::SecBusId
uint8_t SecBusId
Definition: PCIExpress.h:203
temu_PCIeDeviceSpecificConfigSpace::SlotStatusControl
uint32_t SlotStatusControl
Definition: PCIExpress.h:95
temu_PCIeDeviceSpecificConfigSpace::LinkStatusControl
uint32_t LinkStatusControl
Definition: PCIExpress.h:93
temu_PCIeConfigType1::BAR0
uint32_t BAR0
Definition: PCIExpress.h:72
temu_PCIExpressBridgeIface::raiseReset
void(* raiseReset)(temu_Object *)
Definition: PCIExpress.h:160
temu_PCIExpressBusIface::mapPciMem
void(* mapPciMem)(temu_Object *Obj, unsigned Device, unsigned Bar, uint64_t Addr, uint64_t Len)
Definition: PCIExpress.h:152
temu_PCIExpressDeviceIface::writeConfig
void(* writeConfig)(temu_Object *, uint32_t offset, uint32_t value)
Definition: PCIExpress.h:173
temu_PCIExpressConfig::BISTHeaderTypeLatencyTimerCacheLineSize
uint32_t BISTHeaderTypeLatencyTimerCacheLineSize
Definition: PCIExpress.h:124
temu_PCIExpressConfig::StatusCommand
uint32_t StatusCommand
Definition: PCIExpress.h:122
tePMT_PowerIndicatorOn
@ tePMT_PowerIndicatorOn
Definition: PCIExpress.h:51
tePMT_DeassertIntA
@ tePMT_DeassertIntA
Definition: PCIExpress.h:33
temu_PCIExpressConfig::UncorrectableErrorMaskReg
uint32_t UncorrectableErrorMaskReg
Definition: PCIExpress.h:133
temu_PCIExpressBusIface::mapPciIo
void(* mapPciIo)(temu_Object *Obj, unsigned Device, unsigned Bar, uint64_t Addr, uint64_t Len)
Definition: PCIExpress.h:149
temu_PCIExpressConfig::PCIeDevConfig
temu_PCIeDeviceSpecificConfigSpace PCIeDevConfig
Definition: PCIExpress.h:144
temu_PCIExpressBridge::PrimBusId
uint8_t PrimBusId
Definition: PCIExpress.h:202
temu_PCIExpressDeviceIface::getBARInterface
temu_MemAccessIface *(* getBARInterface)(temu_Object *, uint32_t index, uint8_t type)
Definition: PCIExpress.h:176
temu_PCIeDeviceSpecificConfigSpace::PowerMgmtPointerCapabilities
uint32_t PowerMgmtPointerCapabilities
Definition: PCIExpress.h:85
temu_PCIeDeviceSpecificConfigSpace::DeviceStatusControl
uint32_t DeviceStatusControl
Definition: PCIExpress.h:91
tePMT_DeassertIntB
@ tePMT_DeassertIntB
Definition: PCIExpress.h:34
temu_PCIExpressDevice::Super
temu_Object Super
Definition: PCIExpress.h:186
temu_PCIeDeviceSpecificConfigSpace::PCIePointerCapabilities
uint32_t PCIePointerCapabilities
Definition: PCIExpress.h:89
tePMT_VendorDefinedType1
@ tePMT_VendorDefinedType1
Definition: PCIExpress.h:47
temu_PCIExpressDevice::PrimaryBus
temu_PCIExpressBus * PrimaryBus
Definition: PCIExpress.h:188
temu_PCIExpressBridgeIface::lowerReset
void(* lowerReset)(temu_Object *)
Definition: PCIExpress.h:161
temu_PCIExpressBusIface::unmapPciIo
void(* unmapPciIo)(temu_Object *Obj, unsigned Device)
Definition: PCIExpress.h:151
temu_PCIExpressConfig::AdvancedErrorReportingCapIdReg
uint16_t AdvancedErrorReportingCapIdReg
Definition: PCIExpress.h:131
temu_PCIeDeviceSpecificConfigSpace::MessageData
uint32_t MessageData
Definition: PCIExpress.h:102
temu_PCIExpressConfig::UncorrectableErrorStatusReg
uint32_t UncorrectableErrorStatusReg
Definition: PCIExpress.h:132
temu_PCIExpressConfig::AdvancedErrorCapabilitiesControlReg
uint32_t AdvancedErrorCapabilitiesControlReg
Definition: PCIExpress.h:137
temu_PCIeConfigType1::SecondaryStatusIOLimitBase
uint32_t SecondaryStatusIOLimitBase
Definition: PCIExpress.h:74
temu_PCIeControllerInternalCSRs::ControllerCoreClockRatioReg
uint32_t ControllerCoreClockRatioReg
Definition: PCIExpress.h:107
temu_PCIExpressConfig::ExpansionROMBaseAddress
uint32_t ExpansionROMBaseAddress
Definition: PCIExpress.h:126
temu_PCIExpressBridge::Super
temu_PCIExpressDevice Super
Definition: PCIExpress.h:200
temu_PCIExpressConfig::ClassCodeRevID
uint32_t ClassCodeRevID
Definition: PCIExpress.h:123
tePMT_PmPme
@ tePMT_PmPme
Definition: PCIExpress.h:38
temu_PCIExpressConfig::ConfigType1
temu_PCIeConfigType1 ConfigType1
Definition: PCIExpress.h:128
tePMT_AttentionButtonPressed
@ tePMT_AttentionButtonPressed
Definition: PCIExpress.h:54
tePMT_DeassertIntC
@ tePMT_DeassertIntC
Definition: PCIExpress.h:35
temu_PCIExpressConfig::RootErrorCommandReg
uint32_t RootErrorCommandReg
Definition: PCIExpress.h:139
temu_PCIeConfigType1::MemoryLimitBase
uint32_t MemoryLimitBase
Definition: PCIExpress.h:75
tePMT_PmActiveStateNak
@ tePMT_PmActiveStateNak
Definition: PCIExpress.h:37
temu_PCIeControllerInternalCSRs::LTSSMStateStatusReg
uint32_t LTSSMStateStatusReg
Definition: PCIExpress.h:106
tePMT_PowerIndicatorOff
@ tePMT_PowerIndicatorOff
Definition: PCIExpress.h:53
tePMT_PmeTurnOff
@ tePMT_PmeTurnOff
Definition: PCIExpress.h:39
temu_PCIeConfigType1::LatencyTimer2SubBusNumBusNum2PrimBusNum
uint32_t LatencyTimer2SubBusNumBusNum2PrimBusNum
Definition: PCIExpress.h:73
tePMT_VendorDefinedType0
@ tePMT_VendorDefinedType0
Definition: PCIExpress.h:46
tePMT_AssertIntC
@ tePMT_AssertIntC
Definition: PCIExpress.h:31
temu_PCIExpressConfig::HeaderLogReg
uint32_t HeaderLogReg[4]
Definition: PCIExpress.h:138
temu_PCIExpressConfig::PCIeController
temu_PCIeControllerInternalCSRs PCIeController
Definition: PCIExpress.h:145
temu_PCIeDeviceSpecificConfigSpace::DataPowerMgmtStatusControl
uint32_t DataPowerMgmtStatusControl
Definition: PCIExpress.h:87
temu_PCIeDeviceSpecificConfigSpace::DeviceCapabilities
uint32_t DeviceCapabilities
Definition: PCIExpress.h:90
temu_PCIExpressBridgeIface::setUpstreamBridge
void(* setUpstreamBridge)(temu_Object *)
Definition: PCIExpress.h:165
temu_PCIeControllerInternalCSRs::PowerManagementTimerReg
uint32_t PowerManagementTimerReg
Definition: PCIExpress.h:108
tePMT_AssertIntB
@ tePMT_AssertIntB
Definition: PCIExpress.h:30
temu_PCIExpressConfig::DeviceVendorID
uint32_t DeviceVendorID
Definition: PCIExpress.h:121
temu_PCIExpressBus::Super
temu_Object Super
Definition: PCIExpress.h:192
tePMT_AssertIntA
@ tePMT_AssertIntA
Definition: PCIExpress.h:29
temu_PCIeControllerInternalCSRs::SubsystemVendorIDUpdateReg
uint32_t SubsystemVendorIDUpdateReg
Definition: PCIExpress.h:110
tePMT_AttentionIndicatorOn
@ tePMT_AttentionIndicatorOn
Definition: PCIExpress.h:48
temu_PCIeConfigType1::PrefetchableLimitUpper
uint32_t PrefetchableLimitUpper
Definition: PCIExpress.h:78
temu_PCIExpressConfig::CapPointer
uint32_t CapPointer
Definition: PCIExpress.h:125
temu_PCIeConfigType1::PrefetchableMemoryLimitBase
uint32_t PrefetchableMemoryLimitBase
Definition: PCIExpress.h:76
temu_PCIExpressConfig::UncorrectableErrorSeverityReg
uint32_t UncorrectableErrorSeverityReg
Definition: PCIExpress.h:134
tePMT_AttentionIndicatorBlink
@ tePMT_AttentionIndicatorBlink
Definition: PCIExpress.h:49
temu_PCIExpressBridge::SecondaryBus
temu_PCIExpressBus * SecondaryBus
Definition: PCIExpress.h:201
temu_PCIExpressConfig::CorrectableErrorSourceIdReg
uint32_t CorrectableErrorSourceIdReg
Definition: PCIExpress.h:141
temu_PCIExpressBus::ParentDev
temu_PCIExpressBridge * ParentDev
Definition: PCIExpress.h:195
tePMT_AssertIntD
@ tePMT_AssertIntD
Definition: PCIExpress.h:32
tePMT_ErrFatal
@ tePMT_ErrFatal
Definition: PCIExpress.h:43
temu_PCIeConfigType0::SubsystemVendorID
uint32_t SubsystemVendorID
Definition: PCIExpress.h:64
temu_PCIExpressBridgeIface::sendMessage
void(* sendMessage)(void *, temu_PCIeMessageTypes msgType, uint8_t *payload)
Definition: PCIExpress.h:164
temu_PCIExpressConfig::ConfigType0
temu_PCIeConfigType0 ConfigType0
Definition: PCIExpress.h:127
temu_PCIeDeviceSpecificConfigSpace::SlotCapabilities
uint32_t SlotCapabilities
Definition: PCIExpress.h:94
temu_PCIeDeviceSpecificConfigSpace::RootControl
uint32_t RootControl
Definition: PCIExpress.h:96
temu_PCIExpressBridge::SubBusId
uint8_t SubBusId
Definition: PCIExpress.h:204
temu_PCIeConfigType0::CardbusCISPointer
uint32_t CardbusCISPointer
Definition: PCIExpress.h:63
temu_PCIExpressBridgeIface::connect
void(* connect)(temu_Object *, temu_Object *)
Definition: PCIExpress.h:162
temu_PCIExpressBridge
struct temu_PCIExpressBridge temu_PCIExpressBridge
Definition: PCIExpress.h:183
temu_PCIExpressBus
struct temu_PCIExpressBus temu_PCIExpressBus
Definition: PCIExpress.h:182
tePMT_PmToAck
@ tePMT_PmToAck
Definition: PCIExpress.h:40
temu_PCIExpressConfig::CorrectableErrorMaskReg
uint32_t CorrectableErrorMaskReg
Definition: PCIExpress.h:136
tePMT_AttentionIndicatorOff
@ tePMT_AttentionIndicatorOff
Definition: PCIExpress.h:50
temu_PCIExpressBus::ChildrenDevs
temu_PCIExpressDeviceIfaceRefArray ChildrenDevs
Definition: PCIExpress.h:196
temu_PCIeConfigType1::PrefetchableBaseUpper
uint32_t PrefetchableBaseUpper
Definition: PCIExpress.h:77
tePMT_ErrCor
@ tePMT_ErrCor
Definition: PCIExpress.h:41
temu_PCIeControllerInternalCSRs::FlowControlUpdateTimeoutReg
uint32_t FlowControlUpdateTimeoutReg
Definition: PCIExpress.h:112
temu_PCIeDeviceSpecificConfigSpace::RootStatus
uint32_t RootStatus
Definition: PCIExpress.h:97
temu_PCIeConfigType1::BridgeCntrIntPinLine
uint32_t BridgeCntrIntPinLine
Definition: PCIExpress.h:80
temu_PCIExpressDevice::ExpressConf
temu_PCIExpressConfig ExpressConf
Definition: PCIExpress.h:187
tePMT_SetSlotPowerLimit
@ tePMT_SetSlotPowerLimit
Definition: PCIExpress.h:45
temu_PCIExpressConfig::CorrectableErrorStatusReg
uint32_t CorrectableErrorStatusReg
Definition: PCIExpress.h:135
temu_PCIeDeviceSpecificConfigSpace::LinkCapabilities
uint32_t LinkCapabilities
Definition: PCIExpress.h:92
tePMT_PowerIndicatorBlink
@ tePMT_PowerIndicatorBlink
Definition: PCIExpress.h:52
temu_PCIExpressBus::BusId
uint8_t BusId
Definition: PCIExpress.h:193
temu_PCIeConfigType0::MaxLatMinGntIntPinLine
uint32_t MaxLatMinGntIntPinLine
Definition: PCIExpress.h:65
tePMT_Unlock
@ tePMT_Unlock
Definition: PCIExpress.h:44
temu_PCIeDeviceSpecificConfigSpace::UpperMessageAddress
uint32_t UpperMessageAddress
Definition: PCIExpress.h:101
temu_PCIeConfigType0::BAR
uint32_t BAR[6]
Definition: PCIExpress.h:62
temu_PCIExpressConfig::RootErrorStatusReg
uint32_t RootErrorStatusReg
Definition: PCIExpress.h:140
temu_PCIeDeviceSpecificConfigSpace::MessageAddress
uint32_t MessageAddress
Definition: PCIExpress.h:100
tePMT_ErrNonFatal
@ tePMT_ErrNonFatal
Definition: PCIExpress.h:42
temu_PCIeControllerInternalCSRs::SecondaryStatusIrqMaskReg
uint32_t SecondaryStatusIrqMaskReg
Definition: PCIExpress.h:113
tePMT_DeassertIntD
@ tePMT_DeassertIntD
Definition: PCIExpress.h:36