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TEMU
4.2
The Terma Emulator
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9 #ifndef TEMU_BUS_PCIe_H
10 #define TEMU_BUS_PCIe_H
15 #include "temu-c/Bus/PCIDefines.h"
16 #include "temu-c/Memory/Memory.h"
17 #include "temu-c/Support/Logging.h"
18 #include "temu-c/Support/Objsys.h"
63 } temu_PCIeMessageTypes;
74 } temu_PCIeConfigType0;
89 } temu_PCIeConfigType1;
111 } temu_PCIeDeviceSpecificConfigSpace;
122 } temu_PCIeControllerInternalCSRs;
151 temu_PCIeDeviceSpecificConfigSpace
154 } temu_PCIExpressConfig;
157 void (*
mapPciIo)(temu_Object *Obj,
unsigned Device,
unsigned Bar,
158 uint64_t Addr, uint64_t Len);
160 void (*
mapPciMem)(temu_Object *Obj,
unsigned Device,
unsigned Bar,
161 uint64_t Addr, uint64_t Len);
163 } temu_PCIExpressBusIface;
164 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressBus)
165 #define TEMU_PCIe_BUS_IFACE_TYPE "temu::PCIExpressBusIface"
172 void (*
sendMessage)(
void *, temu_PCIeMessageTypes msgType, uint8_t *payload);
174 } temu_PCIExpressBridgeIface;
175 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressBridge)
176 #define TEMU_PCIe_BRIDGE_IFACE_TYPE "temu::PCIExpressBridgeIface"
179 temu_PCIExpressConfig *(*getPciExpressConfig)(temu_Object *);
182 uint32_t (*readConfig)(temu_Object *, uint32_t offset);
183 uint64_t (*getPciExpressExpansionROMSize)(temu_Object *);
186 uint64_t (*getBARSize)(temu_Object *,
unsigned index);
187 } temu_PCIExpressDeviceIface;
188 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressDevice)
189 #define TEMU_PCIe_DEVICE_IFACE_TYPE "temu::PCIExpressDeviceIface"
198 } temu_PCIExpressDevice;
216 static inline temu_PCIExpressBus *
217 temu_pciGetRootBus(temu_PCIExpressDevice *device)
219 temu_PCIExpressBus *bus = device->PrimaryBus;
221 while (bus->ParentDev != NULL) {
222 device = &bus->ParentDev->Super;
223 bus = device->PrimaryBus;
229 temu_pcieSetPrimaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
234 temu_pcieSetSecondaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
239 temu_pcieSetSubordinaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
245 temu_pcieSetBusId(temu_PCIExpressBus *C, uint8_t Val)
250 temu_pcieSetDeviceId(temu_PCIExpressConfig *C, uint16_t Val)
252 C->DeviceVendorID = ((uint32_t)Val << 16) | (C->DeviceVendorID & 0xffff);
256 temu_pcieSetVendorId(temu_PCIExpressConfig *C, uint16_t Val)
258 C->DeviceVendorID = (uint32_t)Val | (C->DeviceVendorID & 0xffff0000);
262 temu_pcieSetStatus(temu_PCIExpressConfig *C, uint16_t Val)
264 C->StatusCommand = ((uint32_t)Val << 16) | (C->StatusCommand & 0xffff);
266 static inline uint16_t
267 temu_pcieReadStatus(temu_PCIExpressConfig *C)
269 return (uint16_t)((C->StatusCommand & 0xffff0000) >> 16);
273 temu_pcieSetClassCode(temu_PCIExpressConfig *C, uint32_t Val)
275 C->ClassCodeRevID &= 0x000000ff;
276 C->ClassCodeRevID |= Val << 8;
280 temu_pcieSetRevId(temu_PCIExpressConfig *C, uint8_t Val)
282 C->ClassCodeRevID &= 0xffffff00;
283 C->ClassCodeRevID |= Val;
287 temu_pcieSetBist(temu_PCIExpressConfig *C, uint8_t Val)
289 C->BISTHeaderTypeLatencyTimerCacheLineSize =
290 ((uint32_t)Val << 24) |
291 (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0x00ffffff);
295 temu_pcieSetHeaderType(temu_PCIExpressConfig *C, uint8_t Val)
297 C->BISTHeaderTypeLatencyTimerCacheLineSize =
298 ((uint32_t)Val << 16) |
299 (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xff00ffff);
303 temu_pcieSetLatencyTimer(temu_PCIExpressConfig *C, uint8_t Val)
305 C->BISTHeaderTypeLatencyTimerCacheLineSize =
306 ((uint32_t)Val << 8) |
307 (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffff00ff);
311 temu_pcieSetCacheLineSize(temu_PCIExpressConfig *C, uint8_t Val)
313 C->BISTHeaderTypeLatencyTimerCacheLineSize =
314 ((uint32_t)Val << 0) |
315 (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffffff00);
319 temu_pcieSetInterruptPin0(temu_PCIExpressConfig *C, uint8_t Val)
322 C->ConfigType0.MaxLatMinGntIntPinLine =
323 ((uint32_t)Val << 8) |
324 (C->ConfigType0.MaxLatMinGntIntPinLine & 0xffff00ff);
328 temu_pcieSetSubsystemId(temu_PCIExpressConfig *C, uint16_t Val)
330 C->ConfigType0.SubsystemVendorID =
331 (uint32_t)Val << 16 | (C->ConfigType0.SubsystemVendorID & 0x0000ffff);
335 temu_pcieSetSubsystemVendorId(temu_PCIExpressConfig *C, uint16_t Val)
337 C->ConfigType0.SubsystemVendorID =
338 (uint32_t)Val << 0 | (C->ConfigType0.SubsystemVendorID & 0xffff0000);
341 temu_pcieSetPrimaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
343 C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
345 (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xffffff00);
348 temu_pcieSetSecondaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
350 C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
351 ((uint32_t)Val << 8) |
352 (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xffff00ff);
355 temu_pcieSetSubordinateBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
357 C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
358 ((uint32_t)Val << 16) |
359 (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xff00ffff);
362 temu_pcieSetIOBase(temu_PCIExpressConfig *C, uint8_t Val)
364 C->ConfigType1.SecondaryStatusIOLimitBase =
366 (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffffff00);
369 temu_pcieSetIOLimit(temu_PCIExpressConfig *C, uint8_t Val)
371 C->ConfigType1.SecondaryStatusIOLimitBase =
372 ((uint32_t)Val << 8) |
373 (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffff00ff);
376 temu_pcieSetSecondaryStatus(temu_PCIExpressConfig *C, uint16_t Val)
378 C->ConfigType1.SecondaryStatusIOLimitBase =
379 ((uint32_t)Val << 16) |
380 (C->ConfigType1.SecondaryStatusIOLimitBase & 0x0000ffff);
383 temu_pcieSetMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
385 C->ConfigType1.MemoryLimitBase =
386 ((uint32_t)Val) | (C->ConfigType1.MemoryLimitBase & 0xffff0000);
389 temu_pcieSetMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
391 C->ConfigType1.MemoryLimitBase =
392 ((uint32_t)Val << 16) | (C->ConfigType1.MemoryLimitBase & 0x0000ffff);
395 temu_pcieSetPrefetchableMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
397 C->ConfigType1.PrefetchableMemoryLimitBase =
399 (C->ConfigType1.PrefetchableMemoryLimitBase & 0xffff0000);
402 temu_pcieSetPrefetchableMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
404 C->ConfigType1.PrefetchableMemoryLimitBase =
405 ((uint32_t)Val << 16) |
406 (C->ConfigType1.PrefetchableMemoryLimitBase & 0x0000ffff);
409 temu_pcieSetInterruptLine(temu_PCIExpressConfig *C, uint8_t Val)
411 C->ConfigType1.BridgeCntrIntPinLine =
412 ((uint32_t)Val) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffffff00);
415 temu_pcieSetInterruptPin1(temu_PCIExpressConfig *C, uint8_t Val)
417 C->ConfigType1.BridgeCntrIntPinLine =
418 ((uint32_t)Val << 8) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffff00ff);
421 temu_pcieSetBridgeControl(temu_PCIExpressConfig *C, uint16_t Val)
423 C->ConfigType1.BridgeCntrIntPinLine =
424 ((uint32_t)Val << 16) |
425 (C->ConfigType1.BridgeCntrIntPinLine & 0x0000ffff);
428 static inline uint16_t
429 temu_pcieReadBridgeControl(temu_PCIExpressConfig *C)
431 return (uint16_t)((C->ConfigType1.BridgeCntrIntPinLine & 0xffff0000) >> 16);
434 static inline uint32_t
435 temu_pcieReadConfigurationReadyReg(temu_PCIExpressConfig *C)
437 return C->PCIeController.ConfigurationReadyReg;
441 temu_pcieSetConfigurationReadyReg(temu_PCIExpressConfig *C, uint32_t Val)
443 C->PCIeController.ConfigurationReadyReg = Val;
uint32_t ConfigurationReadyReg
Definition: PCIExpress.h:119
void(* unmapPciMem)(temu_Object *Obj, unsigned Device)
Definition: PCIExpress.h:162
uint32_t UpperIOLimitIOBase
Definition: PCIExpress.h:87
void(* disconnect)(temu_Object *, temu_Object *)
Definition: PCIExpress.h:171
uint32_t MsgControlPointerMsgCapabilityID
Definition: PCIExpress.h:107
uint32_t PMETimeOutReg
Definition: PCIExpress.h:117
uint8_t SecBusId
Definition: PCIExpress.h:212
uint32_t SlotStatusControl
Definition: PCIExpress.h:103
uint32_t LinkStatusControl
Definition: PCIExpress.h:101
uint32_t BAR0
Definition: PCIExpress.h:80
void(* raiseReset)(temu_Object *)
Definition: PCIExpress.h:168
void(* mapPciMem)(temu_Object *Obj, unsigned Device, unsigned Bar, uint64_t Addr, uint64_t Len)
Definition: PCIExpress.h:160
void(* writeConfig)(temu_Object *, uint32_t offset, uint32_t value)
Definition: PCIExpress.h:181
uint32_t BISTHeaderTypeLatencyTimerCacheLineSize
Definition: PCIExpress.h:132
uint32_t StatusCommand
Definition: PCIExpress.h:130
@ tePMT_PowerIndicatorOn
Definition: PCIExpress.h:59
@ tePMT_DeassertIntA
Definition: PCIExpress.h:41
uint32_t UncorrectableErrorMaskReg
Definition: PCIExpress.h:141
void(* mapPciIo)(temu_Object *Obj, unsigned Device, unsigned Bar, uint64_t Addr, uint64_t Len)
Definition: PCIExpress.h:157
temu_PCIeDeviceSpecificConfigSpace PCIeDevConfig
Definition: PCIExpress.h:152
uint8_t PrimBusId
Definition: PCIExpress.h:211
temu_MemAccessIface *(* getBARInterface)(temu_Object *, uint32_t index, uint8_t type)
Definition: PCIExpress.h:184
uint32_t PowerMgmtPointerCapabilities
Definition: PCIExpress.h:93
uint32_t DeviceStatusControl
Definition: PCIExpress.h:99
@ tePMT_DeassertIntB
Definition: PCIExpress.h:42
temu_Object Super
Definition: PCIExpress.h:195
uint32_t PCIePointerCapabilities
Definition: PCIExpress.h:97
@ tePMT_VendorDefinedType1
Definition: PCIExpress.h:55
temu_PCIExpressBus * PrimaryBus
Definition: PCIExpress.h:197
void(* lowerReset)(temu_Object *)
Definition: PCIExpress.h:169
void(* unmapPciIo)(temu_Object *Obj, unsigned Device)
Definition: PCIExpress.h:159
uint16_t AdvancedErrorReportingCapIdReg
Definition: PCIExpress.h:139
uint32_t MessageData
Definition: PCIExpress.h:110
uint32_t UncorrectableErrorStatusReg
Definition: PCIExpress.h:140
uint32_t AdvancedErrorCapabilitiesControlReg
Definition: PCIExpress.h:145
uint32_t SecondaryStatusIOLimitBase
Definition: PCIExpress.h:82
uint32_t ControllerCoreClockRatioReg
Definition: PCIExpress.h:115
uint32_t ExpansionROMBaseAddress
Definition: PCIExpress.h:134
temu_PCIExpressDevice Super
Definition: PCIExpress.h:209
uint32_t ClassCodeRevID
Definition: PCIExpress.h:131
@ tePMT_PmPme
Definition: PCIExpress.h:46
temu_PCIeConfigType1 ConfigType1
Definition: PCIExpress.h:136
@ tePMT_AttentionButtonPressed
Definition: PCIExpress.h:62
@ tePMT_DeassertIntC
Definition: PCIExpress.h:43
uint32_t RootErrorCommandReg
Definition: PCIExpress.h:147
uint32_t MemoryLimitBase
Definition: PCIExpress.h:83
@ tePMT_PmActiveStateNak
Definition: PCIExpress.h:45
uint32_t LTSSMStateStatusReg
Definition: PCIExpress.h:114
@ tePMT_PowerIndicatorOff
Definition: PCIExpress.h:61
@ tePMT_PmeTurnOff
Definition: PCIExpress.h:47
uint32_t LatencyTimer2SubBusNumBusNum2PrimBusNum
Definition: PCIExpress.h:81
@ tePMT_VendorDefinedType0
Definition: PCIExpress.h:54
@ tePMT_AssertIntC
Definition: PCIExpress.h:39
uint32_t HeaderLogReg[4]
Definition: PCIExpress.h:146
temu_PCIeControllerInternalCSRs PCIeController
Definition: PCIExpress.h:153
uint32_t DataPowerMgmtStatusControl
Definition: PCIExpress.h:95
uint32_t DeviceCapabilities
Definition: PCIExpress.h:98
void(* setUpstreamBridge)(temu_Object *)
Definition: PCIExpress.h:173
uint32_t PowerManagementTimerReg
Definition: PCIExpress.h:116
@ tePMT_AssertIntB
Definition: PCIExpress.h:38
uint32_t DeviceVendorID
Definition: PCIExpress.h:129
temu_Object Super
Definition: PCIExpress.h:201
@ tePMT_AssertIntA
Definition: PCIExpress.h:37
uint32_t SubsystemVendorIDUpdateReg
Definition: PCIExpress.h:118
@ tePMT_AttentionIndicatorOn
Definition: PCIExpress.h:56
uint32_t PrefetchableLimitUpper
Definition: PCIExpress.h:86
uint32_t CapPointer
Definition: PCIExpress.h:133
uint32_t PrefetchableMemoryLimitBase
Definition: PCIExpress.h:84
uint32_t UncorrectableErrorSeverityReg
Definition: PCIExpress.h:142
@ tePMT_AttentionIndicatorBlink
Definition: PCIExpress.h:57
temu_PCIExpressBus * SecondaryBus
Definition: PCIExpress.h:210
uint32_t CorrectableErrorSourceIdReg
Definition: PCIExpress.h:149
temu_PCIExpressBridge * ParentDev
Definition: PCIExpress.h:204
@ tePMT_AssertIntD
Definition: PCIExpress.h:40
@ tePMT_ErrFatal
Definition: PCIExpress.h:51
uint32_t SubsystemVendorID
Definition: PCIExpress.h:72
void(* sendMessage)(void *, temu_PCIeMessageTypes msgType, uint8_t *payload)
Definition: PCIExpress.h:172
temu_PCIeConfigType0 ConfigType0
Definition: PCIExpress.h:135
uint32_t SlotCapabilities
Definition: PCIExpress.h:102
uint32_t RootControl
Definition: PCIExpress.h:104
uint8_t SubBusId
Definition: PCIExpress.h:213
uint32_t CardbusCISPointer
Definition: PCIExpress.h:71
void(* connect)(temu_Object *, temu_Object *)
Definition: PCIExpress.h:170
struct temu_PCIExpressBridge temu_PCIExpressBridge
Definition: PCIExpress.h:192
struct temu_PCIExpressBus temu_PCIExpressBus
Definition: PCIExpress.h:191
@ tePMT_PmToAck
Definition: PCIExpress.h:48
uint32_t CorrectableErrorMaskReg
Definition: PCIExpress.h:144
@ tePMT_AttentionIndicatorOff
Definition: PCIExpress.h:58
temu_PCIExpressDeviceIfaceRefArray ChildrenDevs
Definition: PCIExpress.h:205
uint32_t PrefetchableBaseUpper
Definition: PCIExpress.h:85
@ tePMT_ErrCor
Definition: PCIExpress.h:49
uint32_t FlowControlUpdateTimeoutReg
Definition: PCIExpress.h:120
uint32_t RootStatus
Definition: PCIExpress.h:105
uint32_t BridgeCntrIntPinLine
Definition: PCIExpress.h:88
temu_PCIExpressConfig ExpressConf
Definition: PCIExpress.h:196
@ tePMT_SetSlotPowerLimit
Definition: PCIExpress.h:53
uint32_t CorrectableErrorStatusReg
Definition: PCIExpress.h:143
uint32_t LinkCapabilities
Definition: PCIExpress.h:100
@ tePMT_PowerIndicatorBlink
Definition: PCIExpress.h:60
uint8_t BusId
Definition: PCIExpress.h:202
uint32_t MaxLatMinGntIntPinLine
Definition: PCIExpress.h:73
@ tePMT_Unlock
Definition: PCIExpress.h:52
uint32_t UpperMessageAddress
Definition: PCIExpress.h:109
uint32_t BAR[6]
Definition: PCIExpress.h:70
uint32_t RootErrorStatusReg
Definition: PCIExpress.h:148
uint32_t MessageAddress
Definition: PCIExpress.h:108
@ tePMT_ErrNonFatal
Definition: PCIExpress.h:50
uint32_t SecondaryStatusIrqMaskReg
Definition: PCIExpress.h:121
@ tePMT_DeassertIntD
Definition: PCIExpress.h:44