TEMU  4.2
The Terma Emulator
PCIExpress.h
Go to the documentation of this file.
1 //===------------------------------------------------------------*- C++ -*-===//
2 //
3 // TEMU: The Terma Emulator
4 // (c) Terma 2021
5 // Authors: Daria Vorotnikova <davo (at) terma.com>
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef TEMU_BUS_PCIe_H
10 #define TEMU_BUS_PCIe_H
11 #include <assert.h>
12 #include <stddef.h>
13 #include <stdint.h>
14 
15 #include "temu-c/Bus/PCIDefines.h"
16 #include "temu-c/Memory/Memory.h"
17 #include "temu-c/Support/Logging.h"
18 #include "temu-c/Support/Objsys.h"
19 
20 //===----------------------------------------------------------------------===//
21 //
22 // NOTE: PCIe interfaces is an experimental and unstable API
23 // It is subject to change until it is deemed stable enough.
24 //
25 //===----------------------------------------------------------------------===//
26 
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 /**
32  * temu_PCIeMessageTypes:
33  * PCI Express Messages
34  * name = code
35  */
36 typedef enum {
63 } temu_PCIeMessageTypes;
64 
65 /**
66  * temu_PCIeConfigType0:
67  * Fields that exists only in config type 0
68  */
69 typedef struct {
70  uint32_t BAR[6];
74 } temu_PCIeConfigType0;
75 /**
76  * temu_PCIeConfigType1:
77  * Fields that exists only in config type 1
78  */
79 typedef struct {
80  uint32_t BAR0;
83  uint32_t MemoryLimitBase;
89 } temu_PCIeConfigType1;
90 
91 typedef struct {
92  // Power Mgmt Capabilities |Next Pointer (0x4C)| Power Mgmt Capability ID
94  // Data | .. | Power Management Status & Control
96  // PCI Express Capabilities | Next Pointer | PCI Express Capability ID
102  uint32_t SlotCapabilities; // RC mode only
103  uint32_t SlotStatusControl; // RC mode only
104  uint32_t RootControl; // RC mode only
105  uint32_t RootStatus;
106  // MSI Message Control | Next Pointer (NULL)| MSI Message Capability ID
108  uint32_t MessageAddress;
110  uint32_t MessageData;
111 } temu_PCIeDeviceSpecificConfigSpace;
112 
113 typedef struct {
117  uint32_t PMETimeOutReg;
122 } temu_PCIeControllerInternalCSRs;
123 /**
124  * temu_PCIExpressConfig:
125  * PCI Express configuration space registers
126  */
127 typedef struct {
128  // PCI Compatible Configuration Header
129  uint32_t DeviceVendorID;
130  uint32_t StatusCommand;
131  uint32_t ClassCodeRevID;
133  uint32_t CapPointer;
135  temu_PCIeConfigType0 ConfigType0;
136  temu_PCIeConfigType1 ConfigType1;
137 
138  // PCI Express Extended Configuration Registers
146  uint32_t HeaderLogReg[4];
150 
151  temu_PCIeDeviceSpecificConfigSpace
152  PCIeDevConfig; // 0x40 to 0xFF via capabilities
153  temu_PCIeControllerInternalCSRs PCIeController;
154 } temu_PCIExpressConfig;
155 
156 typedef struct {
157  void (*mapPciIo)(temu_Object *Obj, unsigned Device, unsigned Bar,
158  uint64_t Addr, uint64_t Len);
159  void (*unmapPciIo)(temu_Object *Obj, unsigned Device);
160  void (*mapPciMem)(temu_Object *Obj, unsigned Device, unsigned Bar,
161  uint64_t Addr, uint64_t Len);
162  void (*unmapPciMem)(temu_Object *Obj, unsigned Device);
163 } temu_PCIExpressBusIface;
164 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressBus)
165 #define TEMU_PCIe_BUS_IFACE_TYPE "temu::PCIExpressBusIface"
166 
167 typedef struct {
172  void (*sendMessage)(void *, temu_PCIeMessageTypes msgType, uint8_t *payload);
174 } temu_PCIExpressBridgeIface;
175 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressBridge)
176 #define TEMU_PCIe_BRIDGE_IFACE_TYPE "temu::PCIExpressBridgeIface"
177 
178 typedef struct {
179  temu_PCIExpressConfig *(*getPciExpressConfig)(temu_Object *);
180  // Writes to config space forwarded here
181  void (*writeConfig)(temu_Object *, uint32_t offset, uint32_t value);
182  uint32_t (*readConfig)(temu_Object *, uint32_t offset);
183  uint64_t (*getPciExpressExpansionROMSize)(temu_Object *);
185  uint8_t type);
186  uint64_t (*getBARSize)(temu_Object *, unsigned index);
187 } temu_PCIExpressDeviceIface;
188 TEMU_IFACE_REFERENCE_TYPE(temu_PCIExpressDevice)
189 #define TEMU_PCIe_DEVICE_IFACE_TYPE "temu::PCIExpressDeviceIface"
190 
191 typedef struct temu_PCIExpressBus temu_PCIExpressBus;
192 typedef struct temu_PCIExpressBridge temu_PCIExpressBridge;
193 
194 typedef struct {
196  temu_PCIExpressConfig ExpressConf;
197  temu_PCIExpressBus *PrimaryBus;
198 } temu_PCIExpressDevice;
199 
202  uint8_t BusId;
203 
204  temu_PCIExpressBridge *ParentDev;
206 };
207 
210  temu_PCIExpressBus *SecondaryBus;
211  uint8_t PrimBusId;
212  uint8_t SecBusId;
213  uint8_t SubBusId;
214 };
215 
216 static inline temu_PCIExpressBus *
217 temu_pciGetRootBus(temu_PCIExpressDevice *device)
218 {
219  temu_PCIExpressBus *bus = device->PrimaryBus;
220 
221  while (bus->ParentDev != NULL) {
222  device = &bus->ParentDev->Super;
223  bus = device->PrimaryBus;
224  }
225  return bus;
226 }
227 
228 static inline void
229 temu_pcieSetPrimaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
230 {
231  C->PrimBusId = Val;
232 }
233 static inline void
234 temu_pcieSetSecondaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
235 {
236  C->SecBusId = Val;
237 }
238 static inline void
239 temu_pcieSetSubordinaryBusId(temu_PCIExpressBridge *C, uint8_t Val)
240 {
241  C->SubBusId = Val;
242 }
243 
244 static inline void
245 temu_pcieSetBusId(temu_PCIExpressBus *C, uint8_t Val)
246 {
247  C->BusId = Val;
248 }
249 static inline void
250 temu_pcieSetDeviceId(temu_PCIExpressConfig *C, uint16_t Val)
251 {
252  C->DeviceVendorID = ((uint32_t)Val << 16) | (C->DeviceVendorID & 0xffff);
253 }
254 
255 static inline void
256 temu_pcieSetVendorId(temu_PCIExpressConfig *C, uint16_t Val)
257 {
258  C->DeviceVendorID = (uint32_t)Val | (C->DeviceVendorID & 0xffff0000);
259 }
260 
261 static inline void
262 temu_pcieSetStatus(temu_PCIExpressConfig *C, uint16_t Val)
263 {
264  C->StatusCommand = ((uint32_t)Val << 16) | (C->StatusCommand & 0xffff);
265 }
266 static inline uint16_t
267 temu_pcieReadStatus(temu_PCIExpressConfig *C)
268 {
269  return (uint16_t)((C->StatusCommand & 0xffff0000) >> 16);
270 }
271 
272 static inline void
273 temu_pcieSetClassCode(temu_PCIExpressConfig *C, uint32_t Val)
274 {
275  C->ClassCodeRevID &= 0x000000ff;
276  C->ClassCodeRevID |= Val << 8;
277 }
278 
279 static inline void
280 temu_pcieSetRevId(temu_PCIExpressConfig *C, uint8_t Val)
281 {
282  C->ClassCodeRevID &= 0xffffff00;
283  C->ClassCodeRevID |= Val;
284 }
285 
286 static inline void
287 temu_pcieSetBist(temu_PCIExpressConfig *C, uint8_t Val)
288 {
289  C->BISTHeaderTypeLatencyTimerCacheLineSize =
290  ((uint32_t)Val << 24) |
291  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0x00ffffff);
292 }
293 
294 static inline void
295 temu_pcieSetHeaderType(temu_PCIExpressConfig *C, uint8_t Val)
296 {
297  C->BISTHeaderTypeLatencyTimerCacheLineSize =
298  ((uint32_t)Val << 16) |
299  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xff00ffff);
300 }
301 
302 static inline void
303 temu_pcieSetLatencyTimer(temu_PCIExpressConfig *C, uint8_t Val)
304 {
305  C->BISTHeaderTypeLatencyTimerCacheLineSize =
306  ((uint32_t)Val << 8) |
307  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffff00ff);
308 }
309 
310 static inline void
311 temu_pcieSetCacheLineSize(temu_PCIExpressConfig *C, uint8_t Val)
312 {
313  C->BISTHeaderTypeLatencyTimerCacheLineSize =
314  ((uint32_t)Val << 0) |
315  (C->BISTHeaderTypeLatencyTimerCacheLineSize & 0xffffff00);
316 }
317 
318 static inline void
319 temu_pcieSetInterruptPin0(temu_PCIExpressConfig *C, uint8_t Val)
320 {
321  assert(Val < 0x05);
322  C->ConfigType0.MaxLatMinGntIntPinLine =
323  ((uint32_t)Val << 8) |
324  (C->ConfigType0.MaxLatMinGntIntPinLine & 0xffff00ff);
325 }
326 
327 static inline void
328 temu_pcieSetSubsystemId(temu_PCIExpressConfig *C, uint16_t Val)
329 {
330  C->ConfigType0.SubsystemVendorID =
331  (uint32_t)Val << 16 | (C->ConfigType0.SubsystemVendorID & 0x0000ffff);
332 }
333 
334 static inline void
335 temu_pcieSetSubsystemVendorId(temu_PCIExpressConfig *C, uint16_t Val)
336 {
337  C->ConfigType0.SubsystemVendorID =
338  (uint32_t)Val << 0 | (C->ConfigType0.SubsystemVendorID & 0xffff0000);
339 }
340 static inline void
341 temu_pcieSetPrimaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
342 {
343  C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
344  (uint32_t)Val |
345  (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xffffff00);
346 }
347 static inline void
348 temu_pcieSetSecondaryBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
349 {
350  C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
351  ((uint32_t)Val << 8) |
352  (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xffff00ff);
353 }
354 static inline void
355 temu_pcieSetSubordinateBusNumber(temu_PCIExpressConfig *C, uint8_t Val)
356 {
357  C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum =
358  ((uint32_t)Val << 16) |
359  (C->ConfigType1.LatencyTimer2SubBusNumBusNum2PrimBusNum & 0xff00ffff);
360 }
361 static inline void
362 temu_pcieSetIOBase(temu_PCIExpressConfig *C, uint8_t Val)
363 {
364  C->ConfigType1.SecondaryStatusIOLimitBase =
365  ((uint32_t)Val) |
366  (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffffff00);
367 }
368 static inline void
369 temu_pcieSetIOLimit(temu_PCIExpressConfig *C, uint8_t Val)
370 {
371  C->ConfigType1.SecondaryStatusIOLimitBase =
372  ((uint32_t)Val << 8) |
373  (C->ConfigType1.SecondaryStatusIOLimitBase & 0xffff00ff);
374 }
375 static inline void
376 temu_pcieSetSecondaryStatus(temu_PCIExpressConfig *C, uint16_t Val)
377 {
378  C->ConfigType1.SecondaryStatusIOLimitBase =
379  ((uint32_t)Val << 16) |
380  (C->ConfigType1.SecondaryStatusIOLimitBase & 0x0000ffff);
381 }
382 static inline void
383 temu_pcieSetMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
384 {
385  C->ConfigType1.MemoryLimitBase =
386  ((uint32_t)Val) | (C->ConfigType1.MemoryLimitBase & 0xffff0000);
387 }
388 static inline void
389 temu_pcieSetMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
390 {
391  C->ConfigType1.MemoryLimitBase =
392  ((uint32_t)Val << 16) | (C->ConfigType1.MemoryLimitBase & 0x0000ffff);
393 }
394 static inline void
395 temu_pcieSetPrefetchableMemoryBase(temu_PCIExpressConfig *C, uint16_t Val)
396 {
397  C->ConfigType1.PrefetchableMemoryLimitBase =
398  ((uint32_t)Val) |
399  (C->ConfigType1.PrefetchableMemoryLimitBase & 0xffff0000);
400 }
401 static inline void
402 temu_pcieSetPrefetchableMemoryLimit(temu_PCIExpressConfig *C, uint16_t Val)
403 {
404  C->ConfigType1.PrefetchableMemoryLimitBase =
405  ((uint32_t)Val << 16) |
406  (C->ConfigType1.PrefetchableMemoryLimitBase & 0x0000ffff);
407 }
408 static inline void
409 temu_pcieSetInterruptLine(temu_PCIExpressConfig *C, uint8_t Val)
410 {
411  C->ConfigType1.BridgeCntrIntPinLine =
412  ((uint32_t)Val) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffffff00);
413 }
414 static inline void
415 temu_pcieSetInterruptPin1(temu_PCIExpressConfig *C, uint8_t Val)
416 {
417  C->ConfigType1.BridgeCntrIntPinLine =
418  ((uint32_t)Val << 8) | (C->ConfigType1.BridgeCntrIntPinLine & 0xffff00ff);
419 }
420 static inline void
421 temu_pcieSetBridgeControl(temu_PCIExpressConfig *C, uint16_t Val)
422 {
423  C->ConfigType1.BridgeCntrIntPinLine =
424  ((uint32_t)Val << 16) |
425  (C->ConfigType1.BridgeCntrIntPinLine & 0x0000ffff);
426 }
427 
428 static inline uint16_t
429 temu_pcieReadBridgeControl(temu_PCIExpressConfig *C)
430 {
431  return (uint16_t)((C->ConfigType1.BridgeCntrIntPinLine & 0xffff0000) >> 16);
432 }
433 
434 static inline uint32_t
435 temu_pcieReadConfigurationReadyReg(temu_PCIExpressConfig *C)
436 {
437  return C->PCIeController.ConfigurationReadyReg;
438 }
439 
440 static inline void
441 temu_pcieSetConfigurationReadyReg(temu_PCIExpressConfig *C, uint32_t Val)
442 {
443  C->PCIeController.ConfigurationReadyReg = Val;
444 }
445 
446 #ifdef __cplusplus
447 }
448 #endif
449 #endif // !TEMU_BUS_PCIe_H
temu_PCIeControllerInternalCSRs::ConfigurationReadyReg
uint32_t ConfigurationReadyReg
Definition: PCIExpress.h:119
temu_PCIExpressBusIface::unmapPciMem
void(* unmapPciMem)(temu_Object *Obj, unsigned Device)
Definition: PCIExpress.h:162
temu_PCIeConfigType1::UpperIOLimitIOBase
uint32_t UpperIOLimitIOBase
Definition: PCIExpress.h:87
temu_PCIExpressBridgeIface::disconnect
void(* disconnect)(temu_Object *, temu_Object *)
Definition: PCIExpress.h:171
temu_PCIeDeviceSpecificConfigSpace::MsgControlPointerMsgCapabilityID
uint32_t MsgControlPointerMsgCapabilityID
Definition: PCIExpress.h:107
temu_PCIeControllerInternalCSRs::PMETimeOutReg
uint32_t PMETimeOutReg
Definition: PCIExpress.h:117
temu_PCIExpressBridge::SecBusId
uint8_t SecBusId
Definition: PCIExpress.h:212
temu_PCIeDeviceSpecificConfigSpace::SlotStatusControl
uint32_t SlotStatusControl
Definition: PCIExpress.h:103
temu_PCIeDeviceSpecificConfigSpace::LinkStatusControl
uint32_t LinkStatusControl
Definition: PCIExpress.h:101
temu_PCIeConfigType1::BAR0
uint32_t BAR0
Definition: PCIExpress.h:80
temu_PCIExpressBridgeIface::raiseReset
void(* raiseReset)(temu_Object *)
Definition: PCIExpress.h:168
temu_PCIExpressBusIface::mapPciMem
void(* mapPciMem)(temu_Object *Obj, unsigned Device, unsigned Bar, uint64_t Addr, uint64_t Len)
Definition: PCIExpress.h:160
temu_PCIExpressDeviceIface::writeConfig
void(* writeConfig)(temu_Object *, uint32_t offset, uint32_t value)
Definition: PCIExpress.h:181
temu_PCIExpressConfig::BISTHeaderTypeLatencyTimerCacheLineSize
uint32_t BISTHeaderTypeLatencyTimerCacheLineSize
Definition: PCIExpress.h:132
temu_PCIExpressConfig::StatusCommand
uint32_t StatusCommand
Definition: PCIExpress.h:130
tePMT_PowerIndicatorOn
@ tePMT_PowerIndicatorOn
Definition: PCIExpress.h:59
tePMT_DeassertIntA
@ tePMT_DeassertIntA
Definition: PCIExpress.h:41
temu_PCIExpressConfig::UncorrectableErrorMaskReg
uint32_t UncorrectableErrorMaskReg
Definition: PCIExpress.h:141
temu_PCIExpressBusIface::mapPciIo
void(* mapPciIo)(temu_Object *Obj, unsigned Device, unsigned Bar, uint64_t Addr, uint64_t Len)
Definition: PCIExpress.h:157
temu_PCIExpressConfig::PCIeDevConfig
temu_PCIeDeviceSpecificConfigSpace PCIeDevConfig
Definition: PCIExpress.h:152
temu_PCIExpressBridge::PrimBusId
uint8_t PrimBusId
Definition: PCIExpress.h:211
temu_PCIExpressDeviceIface::getBARInterface
temu_MemAccessIface *(* getBARInterface)(temu_Object *, uint32_t index, uint8_t type)
Definition: PCIExpress.h:184
temu_PCIeDeviceSpecificConfigSpace::PowerMgmtPointerCapabilities
uint32_t PowerMgmtPointerCapabilities
Definition: PCIExpress.h:93
temu_PCIeDeviceSpecificConfigSpace::DeviceStatusControl
uint32_t DeviceStatusControl
Definition: PCIExpress.h:99
tePMT_DeassertIntB
@ tePMT_DeassertIntB
Definition: PCIExpress.h:42
temu_PCIExpressDevice::Super
temu_Object Super
Definition: PCIExpress.h:195
temu_PCIeDeviceSpecificConfigSpace::PCIePointerCapabilities
uint32_t PCIePointerCapabilities
Definition: PCIExpress.h:97
tePMT_VendorDefinedType1
@ tePMT_VendorDefinedType1
Definition: PCIExpress.h:55
temu_PCIExpressDevice::PrimaryBus
temu_PCIExpressBus * PrimaryBus
Definition: PCIExpress.h:197
temu_PCIExpressBridgeIface::lowerReset
void(* lowerReset)(temu_Object *)
Definition: PCIExpress.h:169
temu_PCIExpressBusIface::unmapPciIo
void(* unmapPciIo)(temu_Object *Obj, unsigned Device)
Definition: PCIExpress.h:159
temu_PCIExpressConfig::AdvancedErrorReportingCapIdReg
uint16_t AdvancedErrorReportingCapIdReg
Definition: PCIExpress.h:139
temu_PCIeDeviceSpecificConfigSpace::MessageData
uint32_t MessageData
Definition: PCIExpress.h:110
temu_PCIExpressConfig::UncorrectableErrorStatusReg
uint32_t UncorrectableErrorStatusReg
Definition: PCIExpress.h:140
temu_PCIExpressConfig::AdvancedErrorCapabilitiesControlReg
uint32_t AdvancedErrorCapabilitiesControlReg
Definition: PCIExpress.h:145
temu_PCIeConfigType1::SecondaryStatusIOLimitBase
uint32_t SecondaryStatusIOLimitBase
Definition: PCIExpress.h:82
temu_PCIeControllerInternalCSRs::ControllerCoreClockRatioReg
uint32_t ControllerCoreClockRatioReg
Definition: PCIExpress.h:115
temu_PCIExpressConfig::ExpansionROMBaseAddress
uint32_t ExpansionROMBaseAddress
Definition: PCIExpress.h:134
temu_PCIExpressBridge::Super
temu_PCIExpressDevice Super
Definition: PCIExpress.h:209
temu_PCIExpressConfig::ClassCodeRevID
uint32_t ClassCodeRevID
Definition: PCIExpress.h:131
tePMT_PmPme
@ tePMT_PmPme
Definition: PCIExpress.h:46
temu_PCIExpressConfig::ConfigType1
temu_PCIeConfigType1 ConfigType1
Definition: PCIExpress.h:136
tePMT_AttentionButtonPressed
@ tePMT_AttentionButtonPressed
Definition: PCIExpress.h:62
tePMT_DeassertIntC
@ tePMT_DeassertIntC
Definition: PCIExpress.h:43
temu_PCIExpressConfig::RootErrorCommandReg
uint32_t RootErrorCommandReg
Definition: PCIExpress.h:147
temu_PCIeConfigType1::MemoryLimitBase
uint32_t MemoryLimitBase
Definition: PCIExpress.h:83
tePMT_PmActiveStateNak
@ tePMT_PmActiveStateNak
Definition: PCIExpress.h:45
temu_PCIeControllerInternalCSRs::LTSSMStateStatusReg
uint32_t LTSSMStateStatusReg
Definition: PCIExpress.h:114
tePMT_PowerIndicatorOff
@ tePMT_PowerIndicatorOff
Definition: PCIExpress.h:61
tePMT_PmeTurnOff
@ tePMT_PmeTurnOff
Definition: PCIExpress.h:47
temu_PCIeConfigType1::LatencyTimer2SubBusNumBusNum2PrimBusNum
uint32_t LatencyTimer2SubBusNumBusNum2PrimBusNum
Definition: PCIExpress.h:81
tePMT_VendorDefinedType0
@ tePMT_VendorDefinedType0
Definition: PCIExpress.h:54
tePMT_AssertIntC
@ tePMT_AssertIntC
Definition: PCIExpress.h:39
temu_PCIExpressConfig::HeaderLogReg
uint32_t HeaderLogReg[4]
Definition: PCIExpress.h:146
temu_PCIExpressConfig::PCIeController
temu_PCIeControllerInternalCSRs PCIeController
Definition: PCIExpress.h:153
temu_PCIeDeviceSpecificConfigSpace::DataPowerMgmtStatusControl
uint32_t DataPowerMgmtStatusControl
Definition: PCIExpress.h:95
temu_PCIeDeviceSpecificConfigSpace::DeviceCapabilities
uint32_t DeviceCapabilities
Definition: PCIExpress.h:98
temu_PCIExpressBridgeIface::setUpstreamBridge
void(* setUpstreamBridge)(temu_Object *)
Definition: PCIExpress.h:173
temu_PCIeControllerInternalCSRs::PowerManagementTimerReg
uint32_t PowerManagementTimerReg
Definition: PCIExpress.h:116
tePMT_AssertIntB
@ tePMT_AssertIntB
Definition: PCIExpress.h:38
temu_PCIExpressConfig::DeviceVendorID
uint32_t DeviceVendorID
Definition: PCIExpress.h:129
temu_PCIExpressBus::Super
temu_Object Super
Definition: PCIExpress.h:201
tePMT_AssertIntA
@ tePMT_AssertIntA
Definition: PCIExpress.h:37
temu_PCIeControllerInternalCSRs::SubsystemVendorIDUpdateReg
uint32_t SubsystemVendorIDUpdateReg
Definition: PCIExpress.h:118
tePMT_AttentionIndicatorOn
@ tePMT_AttentionIndicatorOn
Definition: PCIExpress.h:56
temu_PCIeConfigType1::PrefetchableLimitUpper
uint32_t PrefetchableLimitUpper
Definition: PCIExpress.h:86
temu_PCIExpressConfig::CapPointer
uint32_t CapPointer
Definition: PCIExpress.h:133
temu_PCIeConfigType1::PrefetchableMemoryLimitBase
uint32_t PrefetchableMemoryLimitBase
Definition: PCIExpress.h:84
temu_PCIExpressConfig::UncorrectableErrorSeverityReg
uint32_t UncorrectableErrorSeverityReg
Definition: PCIExpress.h:142
tePMT_AttentionIndicatorBlink
@ tePMT_AttentionIndicatorBlink
Definition: PCIExpress.h:57
temu_PCIExpressBridge::SecondaryBus
temu_PCIExpressBus * SecondaryBus
Definition: PCIExpress.h:210
temu_PCIExpressConfig::CorrectableErrorSourceIdReg
uint32_t CorrectableErrorSourceIdReg
Definition: PCIExpress.h:149
temu_PCIExpressBus::ParentDev
temu_PCIExpressBridge * ParentDev
Definition: PCIExpress.h:204
tePMT_AssertIntD
@ tePMT_AssertIntD
Definition: PCIExpress.h:40
tePMT_ErrFatal
@ tePMT_ErrFatal
Definition: PCIExpress.h:51
temu_PCIeConfigType0::SubsystemVendorID
uint32_t SubsystemVendorID
Definition: PCIExpress.h:72
temu_PCIExpressBridgeIface::sendMessage
void(* sendMessage)(void *, temu_PCIeMessageTypes msgType, uint8_t *payload)
Definition: PCIExpress.h:172
temu_PCIExpressConfig::ConfigType0
temu_PCIeConfigType0 ConfigType0
Definition: PCIExpress.h:135
temu_PCIeDeviceSpecificConfigSpace::SlotCapabilities
uint32_t SlotCapabilities
Definition: PCIExpress.h:102
temu_PCIeDeviceSpecificConfigSpace::RootControl
uint32_t RootControl
Definition: PCIExpress.h:104
temu_PCIExpressBridge::SubBusId
uint8_t SubBusId
Definition: PCIExpress.h:213
temu_PCIeConfigType0::CardbusCISPointer
uint32_t CardbusCISPointer
Definition: PCIExpress.h:71
temu_PCIExpressBridgeIface::connect
void(* connect)(temu_Object *, temu_Object *)
Definition: PCIExpress.h:170
temu_PCIExpressBridge
struct temu_PCIExpressBridge temu_PCIExpressBridge
Definition: PCIExpress.h:192
temu_PCIExpressBus
struct temu_PCIExpressBus temu_PCIExpressBus
Definition: PCIExpress.h:191
tePMT_PmToAck
@ tePMT_PmToAck
Definition: PCIExpress.h:48
temu_PCIExpressConfig::CorrectableErrorMaskReg
uint32_t CorrectableErrorMaskReg
Definition: PCIExpress.h:144
tePMT_AttentionIndicatorOff
@ tePMT_AttentionIndicatorOff
Definition: PCIExpress.h:58
temu_PCIExpressBus::ChildrenDevs
temu_PCIExpressDeviceIfaceRefArray ChildrenDevs
Definition: PCIExpress.h:205
temu_PCIeConfigType1::PrefetchableBaseUpper
uint32_t PrefetchableBaseUpper
Definition: PCIExpress.h:85
tePMT_ErrCor
@ tePMT_ErrCor
Definition: PCIExpress.h:49
temu_PCIeControllerInternalCSRs::FlowControlUpdateTimeoutReg
uint32_t FlowControlUpdateTimeoutReg
Definition: PCIExpress.h:120
temu_PCIeDeviceSpecificConfigSpace::RootStatus
uint32_t RootStatus
Definition: PCIExpress.h:105
temu_PCIeConfigType1::BridgeCntrIntPinLine
uint32_t BridgeCntrIntPinLine
Definition: PCIExpress.h:88
temu_PCIExpressDevice::ExpressConf
temu_PCIExpressConfig ExpressConf
Definition: PCIExpress.h:196
tePMT_SetSlotPowerLimit
@ tePMT_SetSlotPowerLimit
Definition: PCIExpress.h:53
temu_PCIExpressConfig::CorrectableErrorStatusReg
uint32_t CorrectableErrorStatusReg
Definition: PCIExpress.h:143
temu_PCIeDeviceSpecificConfigSpace::LinkCapabilities
uint32_t LinkCapabilities
Definition: PCIExpress.h:100
tePMT_PowerIndicatorBlink
@ tePMT_PowerIndicatorBlink
Definition: PCIExpress.h:60
temu_PCIExpressBus::BusId
uint8_t BusId
Definition: PCIExpress.h:202
temu_PCIeConfigType0::MaxLatMinGntIntPinLine
uint32_t MaxLatMinGntIntPinLine
Definition: PCIExpress.h:73
tePMT_Unlock
@ tePMT_Unlock
Definition: PCIExpress.h:52
temu_PCIeDeviceSpecificConfigSpace::UpperMessageAddress
uint32_t UpperMessageAddress
Definition: PCIExpress.h:109
temu_PCIeConfigType0::BAR
uint32_t BAR[6]
Definition: PCIExpress.h:70
temu_PCIExpressConfig::RootErrorStatusReg
uint32_t RootErrorStatusReg
Definition: PCIExpress.h:148
temu_PCIeDeviceSpecificConfigSpace::MessageAddress
uint32_t MessageAddress
Definition: PCIExpress.h:108
tePMT_ErrNonFatal
@ tePMT_ErrNonFatal
Definition: PCIExpress.h:50
temu_PCIeControllerInternalCSRs::SecondaryStatusIrqMaskReg
uint32_t SecondaryStatusIrqMaskReg
Definition: PCIExpress.h:121
tePMT_DeassertIntD
@ tePMT_DeassertIntD
Definition: PCIExpress.h:44