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◆ TEMU_CACHE_CTRL_IFACE_TYPE
#define TEMU_CACHE_CTRL_IFACE_TYPE "temu::CacheCtrlIface" |
◆ TEMU_CACHE_IFACE_TYPE
#define TEMU_CACHE_IFACE_TYPE "temu::CacheIface" |
◆ TEMU_CACHE_LRR
◆ TEMU_CACHE_LRU
◆ TEMU_CACHE_NONE
#define TEMU_CACHE_NONE 0 |
◆ TEMU_CACHE_RND
◆ temu_CacheCtrlIface
The cache control interface can be implemented by a cache controller. Which may be embedded in a CPU or device model. Typically, the assumption is that the cache controller will turn on and off the cache and that it may need to be notified on global eviction operations, which may or may not be reflected in the cache controllers status registers.
◆ temu_CacheIface
Caches implement the memory access interface and the cache control interface. For invalidate and evict operation the address given is a physical address which should be mapped to a line. For Harward style caches, the cache model would typically implement the interface twice, once for instructions and once for data. Invalidation: cache line will be tagged as invalid (i.e. flushed) Eviction: cache line will be invalidated and in writeBack caches the content will be written back to memory.
◆ TEMU_IFACE_REFERENCE_TYPE() [1/2]
TEMU_IFACE_REFERENCE_TYPE |
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temu_Cache |
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◆ TEMU_IFACE_REFERENCE_TYPE() [2/2]
TEMU_IFACE_REFERENCE_TYPE |
( |
temu_CacheCtrl |
| ) |
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