TEMU  4.4
The Terma Emulator
Cpu.h
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1 //===-- temu-c/Cpu.h - CPU Interfaces ---------------------------*- C++ -*-===//
2 //
3 // TEMU: The Terma Emulator
4 // (c) Terma 2015
5 // Authors: Mattias Holm <maho (at) terma.com>
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef TEMU_CPU_H
10 #define TEMU_CPU_H
11 
12 #include "temu-c/Models/Power.h"
13 #include "temu-c/Support/Objsys.h"
14 #include <stdint.h>
15 
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19 
20 typedef enum temu_CpuState {
21  teCS_Nominal, //!< Normal all ok CPU state
22  teCS_Halted, //!< Halted CPU (e.g. SPARC error mode), the CPU can go to
23  //!< the normal state using a reset
24  teCS_Idling, //!< The CPU is in idle mode. It will not run
25  //!< instructions, only advance the CPUs event queue
26  //!< (until the CPU moves to another mode).
27 } temu_CpuState;
28 
29 typedef enum temu_CpuExitReason {
30  teCER_Normal = 0, //!< Normal exit (cannot be passed to early exit)
31  teCER_Trap = 2, //!< Exited due to trap (sync trap)
32  teCER_Halt, //!< Exited due to halting (e.g. sparc error mode)
33  teCER_Event, //!< Exited due to synchronised event (internally,
34  //!< returned for any event)
35  teCER_Break, //!< Exited due to breakpoint hit
36  teCER_WatchR, //!< Exited due to watchpoint read hit
37  teCER_WatchW, //!< Exited due to watchpoint write hit
38  teCER_Early, //!< Other early exit reason
39  teCER_Panic, //!< Emulator panic (e.g. illegal mode transition)
40  teCER_Sync, //!< Instruction cache sync operation
41 } temu_CpuExitReason;
42 
43 // ATC flags
44 #define TEMU_ATC_FETCH 1
45 #define TEMU_ATC_READ (1 << 1)
46 #define TEMU_ATC_WRITE (1 << 2)
47 #define TEMU_ATC_USER (1 << 3)
48 #define TEMU_ATC_SUPER (1 << 4)
49 #define TEMU_ATC_HYPER (1 << 5)
50 
51 // Some types for querying CPU info
52 
53 //!< Endianness of target architecture
54 typedef enum temu_Endian {
55  teEN_Little, //!< Always little endian
56  teEN_Big, //!< Always big endian
57  teEN_Dynamic, //!< Can switch at runtime
58 } temu_Endian;
59 
60 /*!
61  CPU architecture info that can be queried by the user.
62  */
63 typedef struct {
64  const char *ArchName; //!< Architecture name
65  const char *ModelName; //!< Processor model name
66 
67  unsigned VASize; //!< Virtual address size in bits
68  unsigned PASize; //!< Physical address size in bits
69  unsigned VATypeSize; //!< Virtual address type size in bytes
70  unsigned PATypeSize; //!< Physical address type size in bytes (i.e. 8 for 36
71  //!< bit PA)
72 
73  unsigned GPRCount; //!< GPR register count
74  unsigned FPRCount; //!< FPR register count
75 
76  temu_Endian InstructionEndianess; //!< Instruction endianness
77  temu_Endian DataEndianess; //!< Data endianness
78 
79  unsigned NumInstructionSets; //!< Number of instruction sets
80 } temu_CpuInfo;
81 
82 // Named struct type here keeps libclang happy
83 
84 /*!
85  Common CPU interface.
86 
87  The CPU interface provides common functionality that all processors
88  must implement. This includes the reset and run methods. But also
89  different register access functions. The register access functions
90  are functions, because registers may be banked and we want some type
91  of common interface that can access the current registers. Note that
92  the interface currently only support 32 bit processors.
93 
94  \warning Some functions will not return and execute longjmps to the
95  emulation loop instead. These functions should NOT be called from
96  any C++ code that needs destructors to be called on exit or from any
97  events handlers.
98 
99  \field reset The function executing a reset. It takes as parameter
100  the reset type, which is 0 for a default cold reset.
101 
102  \field run Run the main emulator loop for a given number of cycles.
103 
104  \field runUntil Run the main emulator loop until its cycle counter
105  reach the end cycles.
106 
107  \field step Run the given number of steps. A step is one
108  instruction, completed or not. E.g. a trapping instruction does not
109  complete but is counted as a step.
110 
111  \field stepUntil Step the emulator, but stop if the step exceeds a
112  certain fixed time.
113 
114  \field raiseTrap Raises a trap on the CPU. THIS FUNCTION DOES NOT
115  RETURN!!! \warning The raiseTrap function will normally be
116  constructed using longjmp, that implies that you should not call
117  this from a model which must properly unwind the stack and call
118  destructors on the way.
119 
120  \field enterIdleMode Will call longjmp and enter idle mode
121  immediately, this is useful for devices that activates power down
122  mode. \warning This function does not return and destructors will
123  not be called when the stack is unwound.
124 
125  \field exitEmuCore Will call longjmp to exit the emulator core. This
126  can be used in certain cases where the other exit functions do not
127  suite well. One being that a reset is called from an MMIO write or
128  read, or from a watchdog event. The reset can otherwise be called
129  when the emulator is not running, so in a model you can call reset
130  and then exitEmuCore.
131 
132  \field getGpr Read the currently visible general purpose
133  registers. For banked registers (e.g. SPARC reg windows), you should
134  look at the arch specific interface instead.
135 
136  \field getFpr32 Read the currently visible floating point
137  registers.
138 
139  \field setSpr Set special purpose registers. The indexes have been
140  explicitly choosen to be equal to what is assumed by the GDB
141  protocol, but re-based at zero.
142 
143  \field getSpr Read special purpose registers. The indexes have been
144  explicitly choosen to be equal to what is assumed by GDB but rebased
145  at zero.
146 
147  \field disassemble This function will disassemble an instruction.
148  The function returns a heap-allocated string (allocated with
149  malloc()). The caller is responsible for calling free() and managing
150  the lifetime.
151 
152  \field invalidateAtc Invalidates the ATC cache for the given address
153  range. Flags can be set to control the invalidation. Bit 0: don't
154  invalidate fetch. Bit 1: don't Invalidate read, bit 2: don't
155  invalidate write, bit 3 don't invalidate user, bit 4 don't
156  invalidate super.
157 
158  \field translateAddress Does a table walk and translates the
159  virtual address to physical page address. For MMU free systems, the
160  function returns the Va masked with ~(page size-1). Otherwise, the
161  return is the translated page address and in the case of failure -1.
162 
163  \field raiseTrapNoJmp Raises a trap without longjmp to emulator
164  core main loop. This can be used in e.g.
165  timed event handlers and when the core isn't
166  running.
167 */
168 typedef struct temu_CpuIface {
169  void (*reset)(void *Cpu, int ResetType);
170  temu_CpuExitReason (*run)(void *Cpu, uint64_t Cycles);
171  temu_CpuExitReason (*runUntil)(void *Cpu, uint64_t Cycles);
172  temu_CpuExitReason (*step)(void *Cpu, uint64_t Steps);
173  temu_CpuExitReason (*stepUntil)(void *Cpu, uint64_t Steps, uint64_t Cycles);
174 
175  void __attribute__((noreturn)) (*raiseTrap)(void *Obj, int Trap);
176  void (*enterIdleMode)(void *Obj);
177  void __attribute__((noreturn)) (*exitEmuCore)(void *Cpu,
178  temu_CpuExitReason Reason);
179 
180  uint64_t (*getFreq)(void *Cpu);
181  int64_t (*getCycles)(void *Cpu);
182  int64_t (*getSteps)(void *Cpu);
183  temu_CpuState (*getState)(void *Cpu);
184  void (*setPc)(void *Cpu, uint64_t Pc);
185  uint64_t (*getPc)(void *Cpu);
186  void (*setGpr)(void *Cpu, int Reg, uint64_t Value);
187  uint64_t (*getGpr)(void *Cpu, unsigned Reg);
188  void (*setFpr32)(void *Cpu, unsigned Reg, uint32_t Value);
189  uint32_t (*getFpr32)(void *Cpu, unsigned Reg);
190  void (*setFpr64)(void *Cpu, unsigned Reg, uint64_t Value);
191  uint64_t (*getFpr64)(void *Cpu, unsigned Reg);
192  void (*setSpr)(void *Cpu, unsigned Reg, uint64_t Value);
193  uint64_t (*getSpr)(void *Cpu, unsigned Reg);
194  int (*getRegId)(void *Cpu, const char *RegName);
195  const char *(*getRegName)(void *Cpu, int RegId);
196  uint32_t (*assemble)(void *Cpu, const char *AsmStr);
197  char *(*disassemble)(void *Cpu, uint32_t Instr);
198  void (*enableTraps)(void *Cpu);
199  void (*disableTraps)(void *Cpu);
200  void (*invalidateAtc)(void *Obj, uint64_t Addr, uint64_t Pages,
201  uint32_t Flags);
202 
203  uint64_t (*translateAddress)(void *Cpu, uint64_t Va, uint32_t *Flags);
204 
206  void (*setPowerState)(void *Cpu, temu_PowerState Ps);
207 
208  void (*enableTrapEvents)(void *Cpu);
209  void (*disableTrapEvents)(void *Cpu);
210 
211  void (*enableErrorModeEvents)(void *Cpu);
212  void (*disableErrorModeEvents)(void *Cpu);
213 
214  void *(*getMachine)(void *Cpu);
215  void (*raiseTrapNoJmp)(void *Cpu, int Trap);
216 
217  const char *(*getTrapName)(void *Cpu, int Trap);
218 
219  const temu_CpuInfo *(*getCPUInfo)(void *Cpu); // Experimental
220 
221  int (*wakeUp)(void *Cpu); //!< Wake up CPU if it is idling, return 1 if woken
222  //!< up 0 if no state change occurred
223 
224  void (*forceEarlyExit)(void *Cpu); //!< Force early return of core (after
225  //!< event cleanup), unless the core
226  //!< returns for normal reasons, the
227  //!< emulator will return teCER_Early after
228  //!< the current instruction.
229  void *(*translateIRAddress)(void *Obj, uint64_t Va);
230 
231  void (*enableModeSwitchEvents)(void *Obj);
232  void (*disableModeSwitchEvents)(void *Obj);
233 
234  void (*enableProfiling)(void *Obj);
235  void (*disableProfiling)(void *Obj);
236  void (*flushProfileCaches)(void *Obj);
237 
238  int64_t (*getIdleSteps)(void *Cpu);
239  int64_t (*getIdleCycles)(void *Cpu);
240  void (*enterHaltedMode)(void *Obj); //!< Make the processor enter halted mode
241  //!< using a stack posted event.
242  void (*forceSpecificExit)(void *Cpu, temu_CpuExitReason reason);
243 
244  void (*purgeDirtyPages)(void *Obj);
245  void (*invalidateFetchAtc)(void *Obj);
246 
247  int (*translateAddressWithRoot)(void *Cpu, uint64_t Va, uint32_t *Flags, uint64_t RootPointer, uint64_t *PA);
248 
249 
250  temu_CpuExitReason (*synchronizingRun)(void *Obj, uint64_t Cycles);
251  temu_CpuExitReason (*synchronizingRunUntil)(void *Obj, uint64_t Cycles);
252  temu_CpuExitReason (*synchronizingStep)(void *Obj, uint64_t Steps);
253  temu_CpuExitReason (*synchronizingStepUntil)(void *Obj, uint64_t Steps, uint64_t Cycles);
254 
255 } temu_CpuIface;
256 #define TEMU_CPU_IFACE_TYPE "temu::CpuIface"
257 TEMU_IFACE_REFERENCE_TYPE(temu_Cpu);
258 
259 typedef struct {
260  uint32_t TrapId; //!< Trap number (architecture specific)
261  uint64_t PC; //!< Program counter when trap occurred
262  uint64_t nPC; //!< Only valid for targets with delay slots
263 } temu_TrapEventInfo;
264 
265 typedef struct {
266  uint32_t OldMode; //!< Old processor privilege level
267  uint32_t NewMode; //!< New processor privilege level
268 } temu_ModeSwitchInfo;
269 
270 typedef struct {
271  int ResetType; //!< 0 == cold, 1 == warm reset
272 } temu_ResetInfo;
273 
274 
275 // Instruction classification bits
276 #define TEMU_INSTR_BRANCH (1 << 0)
277 #define TEMU_INSTR_INDIRECT_BRANCH (1 << 1)
278 #define TEMU_INSTR_LOAD (1 << 2)
279 #define TEMU_INSTR_STORE (1 << 3)
280 #define TEMU_INSTR_INTEGER (1 << 4)
281 #define TEMU_INSTR_FLOAT (1 << 5)
282 #define TEMU_INSTR_ARITHMETIC (1 << 6)
283 #define TEMU_INSTR_ANNULLED (1 << 7)
284 #define TEMU_INSTR_UNCOND (1 << 8)
285 #define TEMU_INSTR_UNCOND_NEVER (1 << 9)
286 #define TEMU_INSTR_ON_PAGE (1 << 10)
287 #define TEMU_INSTR_MODE_SWITCH (1 << 11)
288 #define TEMU_INSTR_ILLEGAL (1 << 12)
289 #define TEMU_INSTR_NO_DBT (1 << 13)
290 
291 // Permanently unimplemented
292 #define TEMU_INSTR_UNIMP (1 << 14)
293 
294 /*!
295  Internal interface for binary translator
296  */
297 typedef struct {
298  //! Profile counter overflow handler
299  void (*profileCounterOverflow)(void *Obj, uint64_t VA);
300  //! Page written (for flushing caches)
301  void (*wrotePage)(void *Obj, uint64_t Va, uint64_t Pa);
302  //! Internal usage
303  void *(*getRawRuntime)(void *Obj);
304 } temu_TargetExecutionIface;
305 #define TEMU_TARGET_EXEC_IFACE_TYPE "temu::TargetExecutionIface"
306 TEMU_IFACE_REFERENCE_TYPE(temu_TargetExecution);
307 
308 #define TEMU_STICKY_DO_NOT_EXIT_AT_HALT 1
309 #define TEMU_STICKY_PROFILE_MODE 2
310 
311 // TEMU_STICKY_DISABLE_IDLE is deprecated
312 #define TEMU_STICKY_DISABLE_IDLE (1 << 2)
313 
314 /*!
315  Interface for controlling the reset address used in a processor.
316 
317  Processors may in some cases have their reset addresses set dynamically.
318  This interface expose such functionality to peripherals.
319  */
320 typedef struct {
321  //! Update reset address in processor
322  void (*setResetAddress)(void *Obj, uint64_t Address);
323  //! Get reset address in processor, optional method
324  uint64_t (*getResetAddress)(void *Obj);
325 } temu_DynamicResetAddressIface;
326 #define TEMU_DYNAMIC_RESET_ADDRESS_IFACE_TYPE "temu::DynamicResetAddressIface"
327 TEMU_IFACE_REFERENCE_TYPE(temu_DynamicResetAddress);
328 
329 /*!
330  Statistics ID for controlling collection of individual statistics.
331  */
332 typedef enum {
333  teBTS_TranslatedInstructions, //!< Number of translated instructions
334  teBTS_ExecutedInstructions, //!< Number of executed instructions
335  teBTS_TranslatedBlocks, //!< Number of translated blocks
336  teBTS_ExecutedBlocks, //!< Number of executed blocks
337  teBTS_CodeSize, //!< Translated code size in bytes
338 } temu_BTStatID;
339 
340 typedef struct {
341  //! Enable translator for processor
342  void (*enableBinaryTranslator)(void *Obj);
343  //! Disable translator for processor
344  void (*disableBinaryTranslator)(void *Obj);
345  //! Set threshold (of call target execution) for triggering translation
346  void (*setThreshold)(void *Obj, unsigned Threshold);
347  //! Translate specific instruction range
348  int (*translateInstructions)(void *Obj, uint64_t VA, uint64_t PA,
349  unsigned NumInstructions);
350  //! Translate block (terminating with a branch, or end of page (special rules
351  //! for delay slots apply)).
352  int (*translateBlock)(void *Obj, uint64_t VA, uint64_t PA);
353  //! Translate a complete function (determined to be statically reachable from
354  //! the PA on this page).
355  int (*translateFunc)(void *Obj, uint64_t VA, uint64_t PA);
356  //! Manually chain blocks.
357  int (*chainBlocks)(void *Obj, uint64_t SourceBlockPA, uint64_t TargetBlockPA,
358  int TakenArm);
359  //! Disassemble block (using the host assembler)
360  const char *(*disassembleBlock)(void *Obj, uint64_t PA);
361 
362  //! Remove a specific block and unlink incoming/outgoing chains
363  int (*clearBlock)(void *Obj, uint64_t PA);
364  //! Remove all translated blocks on a specific physical page
365  int (*clearBlocksOnPage)(void *Obj, uint64_t PA);
366  //! Enable collection of statistic in translated code
367  void (*enableStatistics)(void *Obj, temu_BTStatID ID);
368  //! Disable collection of statistic in translated code
369  void (*disableStatistics)(void *Obj, temu_BTStatID ID);
370  //! Get statistic
371  uint64_t (*getStatistics)(void *Obj, temu_BTStatID ID);
372  //! Reset statistics
373  void (*clearStatistics)(void *Obj, temu_BTStatID ID);
374 
375 } temu_BinaryTranslationControlIface;
376 #define TEMU_BINARY_TRANSLATION_CONTROL_IFACE_TYPE
377  "temu::BinaryTranslationControlIface"
378 TEMU_IFACE_REFERENCE_TYPE(temu_BinaryTranslationControl);
379 
380 #ifdef __cplusplus
381 }
382 #endif
383 
384 #endif /* ! TEMU_CPU_H */
temu_CpuInfo::DataEndianess
temu_Endian DataEndianess
Data endianness.
Definition: Cpu.h:77
temu_CpuIface::setPowerState
void(* setPowerState)(void *Cpu, temu_PowerState Ps)
Definition: Cpu.h:206
temu_CpuIface::enterIdleMode
void(* enterIdleMode)(void *Obj)
Definition: Cpu.h:176
teBTS_CodeSize
@ teBTS_CodeSize
Translated code size in bytes.
Definition: Cpu.h:337
teCER_Early
@ teCER_Early
Other early exit reason.
Definition: Cpu.h:38
teBTS_TranslatedInstructions
@ teBTS_TranslatedInstructions
Number of translated instructions.
Definition: Cpu.h:333
teCER_Event
@ teCER_Event
Definition: Cpu.h:33
temu_CpuIface::raiseTrapNoJmp
void(* raiseTrapNoJmp)(void *Cpu, int Trap)
Definition: Cpu.h:215
temu_TrapEventInfo::PC
uint64_t PC
Program counter when trap occurred.
Definition: Cpu.h:261
teCER_WatchW
@ teCER_WatchW
Exited due to watchpoint write hit.
Definition: Cpu.h:37
temu_CpuIface::enableModeSwitchEvents
void(* enableModeSwitchEvents)(void *Obj)
Definition: Cpu.h:231
temu_BinaryTranslationControlIface::chainBlocks
int(* chainBlocks)(void *Obj, uint64_t SourceBlockPA, uint64_t TargetBlockPA, int TakenArm)
Manually chain blocks.
Definition: Cpu.h:357
temu_CpuIface::enableErrorModeEvents
void(* enableErrorModeEvents)(void *Cpu)
Definition: Cpu.h:211
temu_CpuIface::setFpr64
void(* setFpr64)(void *Cpu, unsigned Reg, uint64_t Value)
Definition: Cpu.h:190
temu_CpuIface::Trap
void int Trap
Definition: Cpu.h:175
temu_BinaryTranslationControlIface::enableBinaryTranslator
void(* enableBinaryTranslator)(void *Obj)
Enable translator for processor.
Definition: Cpu.h:342
teCER_Break
@ teCER_Break
Exited due to breakpoint hit.
Definition: Cpu.h:35
temu_CpuIface::forceEarlyExit
void(* forceEarlyExit)(void *Cpu)
Definition: Cpu.h:224
teBTS_ExecutedBlocks
@ teBTS_ExecutedBlocks
Number of executed blocks.
Definition: Cpu.h:336
temu_CpuIface::disableProfiling
void(* disableProfiling)(void *Obj)
Definition: Cpu.h:235
temu_CpuIface::disassemble
char *(* disassemble)(void *Cpu, uint32_t Instr)
Definition: Cpu.h:197
temu_CpuInfo::NumInstructionSets
unsigned NumInstructionSets
Number of instruction sets.
Definition: Cpu.h:79
temu_CpuIface::purgeDirtyPages
void(* purgeDirtyPages)(void *Obj)
Definition: Cpu.h:244
teBTS_TranslatedBlocks
@ teBTS_TranslatedBlocks
Number of translated blocks.
Definition: Cpu.h:335
temu_CpuIface::setSpr
void(* setSpr)(void *Cpu, unsigned Reg, uint64_t Value)
Definition: Cpu.h:192
teEN_Little
@ teEN_Little
Always little endian.
Definition: Cpu.h:55
temu_CpuInfo::ArchName
const char * ArchName
Architecture name.
Definition: Cpu.h:64
temu_CpuIface::setPc
void(* setPc)(void *Cpu, uint64_t Pc)
Definition: Cpu.h:184
temu_BinaryTranslationControlIface::translateBlock
int(* translateBlock)(void *Obj, uint64_t VA, uint64_t PA)
Definition: Cpu.h:352
teCER_Trap
@ teCER_Trap
Exited due to trap (sync trap)
Definition: Cpu.h:31
temu_CpuIface::forceSpecificExit
void(* forceSpecificExit)(void *Cpu, temu_CpuExitReason reason)
Definition: Cpu.h:242
temu_CpuInfo::InstructionEndianess
temu_Endian InstructionEndianess
Instruction endianness.
Definition: Cpu.h:76
temu_CpuState
temu_CpuState
Definition: Cpu.h:20
temu_CpuInfo::VASize
unsigned VASize
Virtual address size in bits.
Definition: Cpu.h:67
teCS_Nominal
@ teCS_Nominal
Normal all ok CPU state.
Definition: Cpu.h:21
temu_CpuIface::getRegName
const char *(* getRegName)(void *Cpu, int RegId)
Definition: Cpu.h:195
temu_BinaryTranslationControlIface::setThreshold
void(* setThreshold)(void *Obj, unsigned Threshold)
Set threshold (of call target execution) for triggering translation.
Definition: Cpu.h:346
temu_BinaryTranslationControlIface::clearBlocksOnPage
int(* clearBlocksOnPage)(void *Obj, uint64_t PA)
Remove all translated blocks on a specific physical page.
Definition: Cpu.h:365
temu_CpuIface::translateAddressWithRoot
int(* translateAddressWithRoot)(void *Cpu, uint64_t Va, uint32_t *Flags, uint64_t RootPointer, uint64_t *PA)
Definition: Cpu.h:247
temu_BinaryTranslationControlIface::disassembleBlock
const char *(* disassembleBlock)(void *Obj, uint64_t PA)
Disassemble block (using the host assembler)
Definition: Cpu.h:360
temu_CpuIface::enterHaltedMode
void(* enterHaltedMode)(void *Obj)
Definition: Cpu.h:240
temu_BinaryTranslationControlIface::translateFunc
int(* translateFunc)(void *Obj, uint64_t VA, uint64_t PA)
Definition: Cpu.h:355
temu_CpuIface::getTrapName
const char *(* getTrapName)(void *Cpu, int Trap)
Definition: Cpu.h:217
temu_BinaryTranslationControlIface::enableStatistics
void(* enableStatistics)(void *Obj, temu_BTStatID ID)
Enable collection of statistic in translated code.
Definition: Cpu.h:367
temu_CpuIface::disableModeSwitchEvents
void(* disableModeSwitchEvents)(void *Obj)
Definition: Cpu.h:232
temu_CpuIface::enableTrapEvents
void(* enableTrapEvents)(void *Cpu)
Definition: Cpu.h:208
temu_CpuIface::Reason
void temu_CpuExitReason Reason
Definition: Cpu.h:178
temu_CpuIface::getRegId
int(* getRegId)(void *Cpu, const char *RegName)
Definition: Cpu.h:194
teEN_Big
@ teEN_Big
Always big endian.
Definition: Cpu.h:56
temu_CpuInfo::FPRCount
unsigned FPRCount
FPR register count.
Definition: Cpu.h:74
temu_BinaryTranslationControlIface::clearBlock
int(* clearBlock)(void *Obj, uint64_t PA)
Remove a specific block and unlink incoming/outgoing chains.
Definition: Cpu.h:363
temu_BinaryTranslationControlIface::translateInstructions
int(* translateInstructions)(void *Obj, uint64_t VA, uint64_t PA, unsigned NumInstructions)
Translate specific instruction range.
Definition: Cpu.h:348
temu_CpuInfo::PASize
unsigned PASize
Physical address size in bits.
Definition: Cpu.h:68
temu_BinaryTranslationControlIface::clearStatistics
void(* clearStatistics)(void *Obj, temu_BTStatID ID)
Reset statistics.
Definition: Cpu.h:373
temu_CpuExitReason
temu_CpuExitReason
Definition: Cpu.h:29
teCER_Sync
@ teCER_Sync
Instruction cache sync operation.
Definition: Cpu.h:40
temu_CpuIface::disableErrorModeEvents
void(* disableErrorModeEvents)(void *Cpu)
Definition: Cpu.h:212
temu_TrapEventInfo::nPC
uint64_t nPC
Only valid for targets with delay slots.
Definition: Cpu.h:262
temu_CpuIface::enableTraps
void(* enableTraps)(void *Cpu)
Definition: Cpu.h:198
temu_ResetInfo::ResetType
int ResetType
0 == cold, 1 == warm reset
Definition: Cpu.h:271
temu_TargetExecutionIface::getRawRuntime
void *(* getRawRuntime)(void *Obj)
Internal usage.
Definition: Cpu.h:303
temu_TargetExecutionIface::profileCounterOverflow
void(* profileCounterOverflow)(void *Obj, uint64_t VA)
Profile counter overflow handler.
Definition: Cpu.h:299
temu_CpuIface::invalidateFetchAtc
void(* invalidateFetchAtc)(void *Obj)
Definition: Cpu.h:245
temu_CpuIface::reset
void(* reset)(void *Cpu, int ResetType)
Definition: Cpu.h:169
temu_CpuIface::getPowerState
temu_PowerState(* getPowerState)(void *Cpu)
Definition: Cpu.h:205
temu_CpuInfo::GPRCount
unsigned GPRCount
GPR register count.
Definition: Cpu.h:73
temu_CpuIface::enableProfiling
void(* enableProfiling)(void *Obj)
Definition: Cpu.h:234
temu_ModeSwitchInfo::OldMode
uint32_t OldMode
Old processor privilege level.
Definition: Cpu.h:266
teCER_WatchR
@ teCER_WatchR
Exited due to watchpoint read hit.
Definition: Cpu.h:36
temu_TrapEventInfo::TrapId
uint32_t TrapId
Trap number (architecture specific)
Definition: Cpu.h:260
temu_CpuIface::setGpr
void(* setGpr)(void *Cpu, int Reg, uint64_t Value)
Definition: Cpu.h:186
teEN_Dynamic
@ teEN_Dynamic
Can switch at runtime.
Definition: Cpu.h:57
temu_CpuInfo::PATypeSize
unsigned PATypeSize
Definition: Cpu.h:70
temu_CpuIface::disableTrapEvents
void(* disableTrapEvents)(void *Cpu)
Definition: Cpu.h:209
temu_BinaryTranslationControlIface::disableBinaryTranslator
void(* disableBinaryTranslator)(void *Obj)
Disable translator for processor.
Definition: Cpu.h:344
temu_CpuIface::__attribute__
void __attribute__((noreturn))(*exitEmuCore)(void *Cpu
temu_DynamicResetAddressIface::setResetAddress
void(* setResetAddress)(void *Obj, uint64_t Address)
Update reset address in processor.
Definition: Cpu.h:322
temu_CpuIface::getMachine
void *(* getMachine)(void *Cpu)
Definition: Cpu.h:214
temu_CpuIface::flushProfileCaches
void(* flushProfileCaches)(void *Obj)
Definition: Cpu.h:236
temu_CpuIface::wakeUp
int(* wakeUp)(void *Cpu)
Definition: Cpu.h:221
temu_CpuIface::translateIRAddress
void *(* translateIRAddress)(void *Obj, uint64_t Va)
Definition: Cpu.h:229
temu_Endian
temu_Endian
< Endianness of target architecture
Definition: Cpu.h:54
temu_ModeSwitchInfo::NewMode
uint32_t NewMode
New processor privilege level.
Definition: Cpu.h:267
teCER_Panic
@ teCER_Panic
Emulator panic (e.g. illegal mode transition)
Definition: Cpu.h:39
teBTS_ExecutedInstructions
@ teBTS_ExecutedInstructions
Number of executed instructions.
Definition: Cpu.h:334
temu_CpuInfo::ModelName
const char * ModelName
Processor model name.
Definition: Cpu.h:65
temu_CpuIface::setFpr32
void(* setFpr32)(void *Cpu, unsigned Reg, uint32_t Value)
Definition: Cpu.h:188
temu_CpuIface::invalidateAtc
void(* invalidateAtc)(void *Obj, uint64_t Addr, uint64_t Pages, uint32_t Flags)
Definition: Cpu.h:200
temu_CpuInfo::VATypeSize
unsigned VATypeSize
Virtual address type size in bytes.
Definition: Cpu.h:69
teCER_Normal
@ teCER_Normal
Normal exit (cannot be passed to early exit)
Definition: Cpu.h:30
teCS_Idling
@ teCS_Idling
Definition: Cpu.h:24
temu_BinaryTranslationControlIface::disableStatistics
void(* disableStatistics)(void *Obj, temu_BTStatID ID)
Disable collection of statistic in translated code.
Definition: Cpu.h:369
teCS_Halted
@ teCS_Halted
Definition: Cpu.h:22
temu_CpuIface::disableTraps
void(* disableTraps)(void *Cpu)
Definition: Cpu.h:199
temu_CpuIface::__attribute__
void __attribute__((noreturn))(*raiseTrap)(void *Obj
temu_TargetExecutionIface::wrotePage
void(* wrotePage)(void *Obj, uint64_t Va, uint64_t Pa)
Page written (for flushing caches)
Definition: Cpu.h:301
teCER_Halt
@ teCER_Halt
Exited due to halting (e.g. sparc error mode)
Definition: Cpu.h:32