Limitations

Current known limitations of the ARMv7 target include:

  • Performance is limited due to decoding logic needed for ARMv7 and Thumb2 ISAs. Current performance is around 30 % of the SPARCv8 model. This will be addressed in the future.

  • No static timing model is defined at this moment. That means that one instruction take one cycle to finish.

  • The built-in assemblers and disassemblers are not working at this moment.

  • Cache control interfaces are not implemented or supported, this can be addressed if needed.

  • NEON (vector) instructions are not implemented at this moment.

  • A co-processor interface exists, but it is currently not stable.