Limitations

The following deviations from real hardware are known to exist with this model:

  • The Disable Timer Freeze bit is always 1 and cannot be configured.

  • The Debug Halt bit for each timer is always 0 and cannot be altered.

  • Chained timers are not supported at the moment.

  • The last timer does not work as a watchdog.

  • As the timer utilise synchronised events, the minimum time for a timer expiration on a multi-core CPU would be equal to the time-quanta that the machine has been configured with.