Limitations

The following deviations from real hardware are known to exist with this model:

The controller clears the RX and TX buffers on reset. This is not the proper behaviour and may have an impact on FDIR. Let us know if this is an issue.
With all CAN models, there is no arbitration of messages in the simulated world and busses are not synchronised.
The model does at present not register filters with the CAN bus model.
The model currently ignores the error field in the CAN frame objects.
The model currently assumes the CAN bus is running at 1 Mb/s (in non-infinite speed mode). This is arguably incorrect and the timing should be picked from the bus timing register, this has however not yet been done. Contact Terma if this is this is critical for your needs.