Limitations

Current known limitations of the PowerPC target include:

  • No static timing model is defined at this moment. That means that one instruction take one cycle to finish.

  • The built-in assemblers and disassemblers are not working at this have problems with split field instructions (e.g. SPR IDs).

  • Cache control interfaces are not implemented or supported, this can be addressed if needed.

  • AltiVec instructions are not implemented at this moment. These can be added if such a PowerPC model is requested.

  • MMU model is not yet validated against hardware.