Configuration

Arguments

When creating the processor, the temu_create() fun function accepts a number of arguments (which can be given as args=key0:value0,key1:value1 in the command line interface).

These arguments are:

cpuid: CPUId, this is a numeric identifier of the core in multi-core/smp systems. Defaults to 0, ignore if you want a single core machine.
freq: Clock frequency in Hz.
cputype: For the Leon4 class only, the cputype argument can be set to the string 'ngmp' in order to indicate that the LEON4 core should use the NGMP reset values.

Properties

The following properties are important for configuration of a virtual system.

Interface References

memaccess: The interface reference to an object reacting to the emulator core’s memory accesses (whenever there is an ATC miss). This should normally refer to a memory space object or the MMU interface. Set this to memspace:MemAccessIface in case the CPU lacks an MMU or to cpu:MmuMemAccessIface in-case the CPU has an MMU. That is, in the case of an MMU, the iface reference refers to the object itself.
memAccessL2: The interface reference to an object reacting to the memory accesses invoked first in the memaccess interface reference. In case the system has an MMU, set this to memspace:MemAccessIface.
memory: The interface reference to an object handling memory block read and writes, this should normally refer to a memory space object.
irqctrl: The interface reference to an object implementing the IrqControl interface. This can be used to connect external interrupt controllers which need to have interrupts acknowledged.
devices: Array of interface references to device models. The objects in this array will have a CPU reset call propagated to themselves. If your device model handles reset messages, it must be put into the devices array (in either the CPU or the machine object).
dCache: Data cache model. For high performance, omit the cache model. This property is only available in processor cores that support cache.
iCache: Data cache model. For high performance, omit the cache model. This property is only available in processor cores that support cache.

Other Properties

freq: Clock frequency in Hz. Defaults to 50000000 = 50 MHz.
cpuid: CPU id for multiprocessor configurations, defaults to 0.

Interfaces

The SPARCv8 emulator cores implement the following interfaces:

CpuIface: The common CPU interface. This contain functions like run and register access functions.
SparcIface: Standard SPARCv8 interface. Contains among other things functions for accessing windowed registers. One capability of the SPARC interface is the registration of ASI handlers.
IrqIface: The interrupt controller interface for raising interrupts on the processor.
InvalidMemAccessIface: Interface invoked on invalid memory accesses. This contain functions that will longjmp to the CPU trap handling logic. The interface can only be invoked from code invoked by the CPU core in one way or the other. Do not call the functions in this interface directly!
EventIface: Interface for posting timed events on the CPU core’s event queue. Usually a reference to this event is installed in connected device models.
MemoryIface: Proxy interface which forwards to the memory space object.
MmuMemAccessIface: The memory interface provided by the CPU to do accesses through the MMU.
ICacheCtrlIface: Instruction cache control interface. Only available in LEON3 and LEON4.
DCacheCtrlIface: Data cache control interface. Only available in LEON3 and LEON4.