TEMU 4.4.0

TEMU 4.4.0 was released on 2025-04-29.

TEMU 4.4.0 is a feature release. It also addresses a few bugs with respect to 4.3.7.

Features

  • Adding ability to load ELF files to their physical address in the program headers. This is done by either adding use-pa=1 to the loader command, or using the temu_loadImagePhys() function.

  • Adding functionality to attach scripts to the processor add-call command method. The command method was previously only used for testing the callback mechanism.

  • Add SREC dump function: temu_storeSrecImage().

  • Introduce a new assembler interface for processor models. This interface makes variable length instructions easier to support.

  • Introduce a new experimental register information API. The API is intended to replace the old register info API, which was also experimental. The API is unstable and will stabilize for TEMU 5.

  • LEON5 model added.

Bugs

The following bugs have been fixed relative to TEMU 4.3.7:

  • Fix problems with TEMU cmake package definition files. The cmake package files allow the use of find_package(TEMU) and linking to temu::support if using the CMake build system.

  • Generic Processor Fixes

    • Incorrect ATC hashing could cause issues with code patching.

    • Internal tool fixes impacting register accessor emissions for some targets.

  • Generic Ethernet Models:

    • Make ethernet autonegotiation in phy conditional on being attached to link (prevents crash if no link/ethernet cable attached)

  • Peripheral Models

    • eTSEC (used in e.g. the P2020 model) was set as little endian instead of big endian in the memory space capabilities.

    • OpenPIC allow CCB and RTC frequencies to be set to any value.

  • E500 processor model

    • e500v2 TLB0 was of wrong size, used e500v1 sizes by mistake.

    • e500v2 BookE time base registers not correctly implemented, as a consequence the CPU must be configured with the CCB and TB clocks (for P2020, TB clock = RTC for the OpenPIC model). The issue could result in delay loops deadlocking.

    • Special Purpose Register (SPR) 976 (an undocumented register in the e500 processor) was added as a no-op register.

    • Special Purpose Registers (SPR) 1010 (L1CSR0) and 1011 (L1CSR1) did not force flush in progress bits to zero after writes, this could result in infinite loops on L1 cache flushes.

    • e500v2 efdcmplt instruction was producing incorrect comparison results in some cases.