Limitations

The following deviations from real hardware are known to exist with this model:

  • Broadcasted interrupts are broadcasted at the current time to all CPUs. If triggered by a non-synchronised event, the interrupt is raised at different times on the different cores. Depending on the IRQ frequency and the configured quanta length, this may result in problems for some software.

  • The model does not verify that register writes come from the correct CPU at the moment.