E500v2
The E500v2 models the NXP processor core of the same name. This includes the SPE instruction set.
@e500v2 Reference
e500v2 Reference
Properties
| Name | Type | Description |
|---|---|---|
CPUId |
uint32_t |
|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
TimeSource |
*void |
Time source object |
acc |
uint64_t |
Accumulator register |
atbl |
uint32_t |
|
atbu |
uint32_t |
|
bbear |
uint32_t |
|
bbtar |
uint32_t |
|
bucsr |
uint32_t |
|
cr |
uint32_t |
|
csrrs |
[uint32_t; 2] |
|
ctr |
uint32_t |
|
cycles |
int64_t |
|
dac1 |
uint32_t |
|
dac2 |
uint32_t |
|
dbcrs |
[uint32_t; 3] |
|
dbsr |
uint32_t |
|
dear |
uint32_t |
|
dec |
uint32_t |
|
decar |
uint32_t |
|
devices |
temu_IfaceRefArray |
|
dvc1 |
uint32_t |
|
dvc2 |
uint32_t |
|
esr |
uint32_t |
|
freq |
uint64_t |
|
gprs |
[uint64_t; 32] |
|
hids |
[uint32_t; 2] |
|
iac1 |
uint32_t |
|
iac2 |
uint32_t |
|
irq |
int8_t |
|
irqClient |
temu_IfaceRef/ <unknown> |
|
ivors |
[uint32_t; 64] |
|
ivpr |
uint32_t |
|
l1cfg0 |
uint32_t |
|
l1cfg1 |
uint32_t |
|
lr |
uint32_t |
|
machine |
temu_IfaceRef/ <unknown> |
|
mass |
[uint32_t; 7] |
|
mcar |
uint32_t |
|
mcsr |
uint32_t |
|
mcsrrs |
[uint32_t; 2] |
|
memAccess |
temu_IfaceRef/ <unknown> |
|
memAccessL2 |
temu_IfaceRef/ <unknown> |
|
memory |
temu_IfaceRef/ <unknown> |
|
mmucfg |
uint32_t |
|
mmucsr0 |
uint32_t |
|
msr |
uint32_t |
|
nextEvent |
int64_t |
|
pc |
uint32_t |
|
pid0 |
uint32_t |
|
pid1 |
uint32_t |
|
pid2 |
uint32_t |
|
pir |
uint32_t |
|
pmc0 |
uint32_t |
|
pmc1 |
uint32_t |
|
pmc2 |
uint32_t |
|
pmc3 |
uint32_t |
|
pmgc0 |
uint32_t |
|
pmlca0 |
uint32_t |
|
pmlca1 |
uint32_t |
|
pmlca2 |
uint32_t |
|
pmlca3 |
uint32_t |
|
pmlcb0 |
uint32_t |
|
pmlcb1 |
uint32_t |
|
pmlcb2 |
uint32_t |
|
pmlcb3 |
uint32_t |
|
powerState |
uint32_t |
|
pvr |
uint32_t |
|
spefscr |
uint32_t |
|
sprgs |
[uint32_t; 8] |
|
srrs |
[uint32_t; 2] |
|
state |
int32_t |
|
steps |
int64_t |
|
svr |
uint32_t |
|
tcr |
uint32_t |
|
tlb0cfg |
uint32_t |
|
tlb1cfg |
uint32_t |
|
tsr |
uint32_t |
|
upmc0 |
uint32_t |
|
upmc1 |
uint32_t |
|
upmc2 |
uint32_t |
|
upmc3 |
uint32_t |
|
upmgc0 |
uint32_t |
|
upmlca0 |
uint32_t |
|
upmlca1 |
uint32_t |
|
upmlca2 |
uint32_t |
|
upmlca3 |
uint32_t |
|
upmlcb0 |
uint32_t |
|
upmlcb1 |
uint32_t |
|
upmlcb2 |
uint32_t |
|
upmlcb3 |
uint32_t |
|
usrpg0 |
uint32_t |
|
xer |
uint32_t |
Interfaces
| Name | Type | Description |
|---|---|---|
ClockIface |
ClockIface |
|
CpuIface |
temu::CpuIface |
|
EventIface |
temu::EventIface |
|
InvalidMemAccessIface |
MemAccessIface |
|
IrqIface |
IrqCtrlIface |
|
MemoryIface |
MemoryIface |
|
MmuMemAccessIface |
MemAccessIface |
MMU access interface |
ObjectIface |
ObjectIface |
|
PowerIface |
PowerIface |
|
PowerPCIface |
temu::PowerPCIface |
|
ResetIface |
ResetIface |
Commands
| Name | Description |
|---|---|
delete |
Dispose instance of e500v2 |
printTLB0 |
Print TLB0 |
printTLB1 |
Print TLB1 |
raiseCritical |
Raise critical interrupt |
raiseExternal |
Raise external interrupt |
setPC |
Set PC |
setTLB0Entry |
Add entry to TLB0 |
setTLB1Entry |
Add entry to TLB1 |
Limitations
-
No static timing model is defined at this moment. That means that one instruction take one cycle to finish.
-
AltiVec instructions are not implemented at this moment. These can be added if such a PowerPC model is requested.
-
MMU model is not yet validated against hardware.
-
Cache control interfaces are not implemented or supported, this can be addressed if needed.
-
The errata described in the e500CORERMAD is not correctly simulated. the following instructions deviates from hardware errata and are implemented as documented instead:
-
evmwlssiaaw -
evmwlssianw -
evmwlusiaaw -
evmwlusianw
-