E500v2

The E500v2 models the NXP processor core of the same name. This includes the SPE instruction set.

@e500v2 Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @e500v2

new

Create new instance of e500v2

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

e500v2 Reference

Properties

Name Type Description

CPUId

uint32_t

CPUType

int32_t

Class

*void

Class object

ClockDivider

uint64_t

Current clock divider (relation CPU freq and CCB or TB freq).

Component

*void

Pointer to component object if part of component

HostFlags

uint64_t

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

acc

uint64_t

Accumulator register

atbl

uint32_t

Alternate Time Base Lower

atbu

uint32_t

Alternate Time Base Upper

bbear

uint32_t

Branch Buffer Entry Address Register

bbtar

uint32_t

Branch Buffer Target Address Register

bucsr

uint32_t

Branch Unit Control and Status Register

config.CCBFrequency

uint64_t

CCB Clock Frequency

config.TBFrequency

uint64_t

Time Base Clock Frequency (same as RTC on e500)

config.assemblerAliases

uint8_t

config.exitOnSync

uint8_t

config.handleEventWithinBlock

uint8_t

config.measureExecTime

uint8_t

cpi

double

Cycles per instruction

cr

uint32_t

csrrs

[uint32_t; 2]

ctr

uint32_t

Count Register

currentContextId

uint64_t

currentContextValid

uint8_t

currentThreadContextId

uint64_t

currentThreadContextValid

uint8_t

dac1

uint32_t

Data Address Compare Register 1

dac2

uint32_t

Data Address Compare Register 2

dbcrs

[uint32_t; 3]

dbsr

uint32_t

Debug Status Register

dear

uint32_t

Data Exception Address Register

dec

uint32_t

Decrementer

decar

uint32_t

Decrementer Auto-Reload Register

devices

temu_IfaceRefArray

dvc1

uint32_t

Data Value Compare Register 1

dvc2

uint32_t

Data Value Compare Register 2

esr

uint32_t

Exception Syndrome Register

exitReason

int32_t

freq

int64_t

Frequency in Hz

gprs

[uint64_t; 32]

hid0

uint32_t

Hardware Implementation-Dependent Register 0

hid1

uint32_t

Hardware Implementation-Dependent Register 1

iac1

uint32_t

Instruction Address Compare 1 Register

iac2

uint32_t

Instruction Address Compare 2 Register

idleSteps

int64_t

ipc

double

Instructions per cycle

irq

int8_t

irqClient

temu_IfaceRef/ <unknown>

ivors

[uint32_t; 64]

ivpr

uint32_t

Interrupt Vector Prefix Register

l1cfg0

uint32_t

L1 Cache Configuration Register 0

l1cfg1

uint32_t

L1 Cache Configuration Register 1

l1csr0

uint32_t

L1 Cache Control and Status Register 0

l1csr1

uint32_t

L1 Cache Control and Status Register 1

logTrampolines

uint8_t

lr

uint32_t

Link register

mass

[uint32_t; 7]

mcar

uint32_t

Machine Check Address Register

mcsr

uint32_t

Machine Check Syndrome Register

mcsrrs

[uint32_t; 2]

memAccess

temu_IfaceRef/ <unknown>

Level 1 memory access interface (MMU)

memAccessL2

temu_IfaceRef/ <unknown>

Level 2 memory access interface (physical)

memReset

temu_IfaceRef/ <unknown>

Memory space reset interface

memSpace

*void

Memory space.

mmucfg

uint32_t

mmucsr0

uint32_t

msr

uint32_t

nextEvent

int64_t

Next event

parentTimeSource

*void

Parent time source

pc

uint32_t

Program counter

pdcManager

temu_IfaceRef/ <unknown>

Pre-decode cache manager (normally memory space)

pid0

uint32_t

Process ID Register 0

pid1

uint32_t

Process ID Register 1

pid2

uint32_t

Process ID Register 2

pir

uint32_t

Processor ID Register

pmc0

uint32_t

Performance Monitor Counter 0

pmc1

uint32_t

Performance Monitor Counter 1

pmc2

uint32_t

Performance Monitor Counter 2

pmc3

uint32_t

Performance Monitor Counter 3

pmgc0

uint32_t

Performance Monitor Global Control Register 0

pmlca0

uint32_t

Performance Monitor Local Control a0

pmlca1

uint32_t

Performance Monitor Local Control a1

pmlca2

uint32_t

Performance Monitor Local Control a2

pmlca3

uint32_t

Performance Monitor Local Control a3

pmlcb0

uint32_t

Performance Monitor Local Control b0

pmlcb1

uint32_t

Performance Monitor Local Control b1

pmlcb2

uint32_t

Performance Monitor Local Control b2

pmlcb3

uint32_t

Performance Monitor Local Control b3

powerState

uint32_t

Power State property (deprecated)

pvr

uint32_t

Processor Version Register

skipIdleTags

uint64_t

spefscr

uint32_t

spr976

uint32_t

sprgs

[uint32_t; 8]

srrs

[uint32_t; 2]

startSteps

int64_t

Start steps of the time source

state

int32_t

steps

int64_t

Steps of the time source

stickyFlags

uint32_t

Set bit 0 to 1 to not exit CPU on halted mode.

svr

uint32_t

System Version Register

targetExec

temu_IfaceRef/ <unknown>

Target execution interface

targetSteps

int64_t

Target steps of the time source

tcr

uint32_t

Timer Control Register

tlb0Entries

[uint32_t; 8192]

TLB0 Entries

tlb0Nv

uint32_t

TLB0 NV

tlb0cfg

uint32_t

TLB0 Configuration Register

tlb1Entries

[uint32_t; 64]

TLB1 Entries

tlb1cfg

uint32_t

TLB1 Configuration Register

tsr

uint32_t

Timer Status Register

upmc0

uint32_t

User Performance Monitor Counter 0

upmc1

uint32_t

User Performance Monitor Counter 1

upmc2

uint32_t

User Performance Monitor Counter 2

upmc3

uint32_t

User Performance Monitor Counter 3

upmgc0

uint32_t

User Performance Monitor Global Control Register 0

upmlca0

uint32_t

User Performance Monitor Local Control a0

upmlca1

uint32_t

User Performance Monitor Local Control a1

upmlca2

uint32_t

User Performance Monitor Local Control a2

upmlca3

uint32_t

User Performance Monitor Local Control a3

upmlcb0

uint32_t

User Performance Monitor Local Control b0

upmlcb1

uint32_t

User Performance Monitor Local Control b1

upmlcb2

uint32_t

User Performance Monitor Local Control b2

upmlcb3

uint32_t

User Performance Monitor Local Control b3

usrpg0

uint32_t

User SPR General Register 0

xer

uint32_t

Integer exception register

Interfaces

Name Type Description

AssemblerIface

temu::AssemblerIface

Assembler interface

BinaryTranslationIface

temu::BinaryTranslationControlIface

ClockIface

ClockIface

CodePatternIface

temu::CodePatternIface

CpuIface

temu::CpuIface

E500MMUIface

temu::E500MMUIface

MMU interface for the E500

ExecIface

temu::TargetExecutionIface

InvalidMemAccessIface

MemAccessIface

IrqIface

IrqCtrlIface

MmuMemAccessIface

MemAccessIface

MMU access interface

ObjectIface

ObjectIface

PhysicalMemAccessIface

MemAccessIface

PowerIface

PowerIface

PowerPCIface

temu::PowerPCIface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

VirtualMemAccessIface

MemAccessIface

Ports

Prop Iface Description

irqClient

IrqIface

interrupt controller interface

Commands

Name Description

add-call

Adds a call at the specific address. The call operation calls a predefined method which logs that it is invoked.It is primarily useful for debugging.

add-idle

Adds an explicit idle operation at the specific address.

add-skip

Adds a skip operation at the specific address. After this, the given number of instructions will be skipped.

assemble

Assemble instruction

delete

Dispose instance of e500v2

disable-dbt-logging

Disable logging when translating code.

disable-dbt-validation

Disable validation of emitted machine code.

disable-hard-code-reset

Disable hard resets of DBT emitter cache.

disable-stats

Disable statistics

disable-translation-logging

Disable jit-logging.

disassemble-block

Disassemble binary translated code block.

disassemble-block-option

Set option for disassembler. Switch between AT&T (default) and Intel (alternate) syntax. Enable / disable insruction latency in output.

enable-dbt-logging

Enable logging when translating code.

enable-dbt-validation

Enable validation of emitted machine code.

enable-hard-code-reset

Enable hard resets of DBT emitter cache.

enable-stats

Enable statistics

enable-translation-logging

Enable jit-logging.

pfregs

Print floating point registers for CPU

pregs

Print registers for CPU

printTLB0

Print TLB0

printTLB1

Print TLB1

pstat

Print CPU stats

raiseCritical

Raise critical interrupt

raiseExternal

Raise external interrupt

set-reg

Set register

setPC

Set PC

setTLB0Entry

Add entry to TLB0

setTLB1Entry

Add entry to TLB1

stacktrace

ABI stack trace

translate-block

Translate block.

translate-func

Translate function.

wake-up

Wakes up the processor.

Command add-call Arguments

Name Type Required Description

context

string

no

Context

pa

int

no

Physical Address

pamask

int

no

Physical Address Mask

script

path

no

Script to run when reaching address

va

int

no

Virtual Address

vamask

int

no

Virtual Address Mask

Command add-idle Arguments

Name Type Required Description

context

string

no

Context

pa

int

no

Physical Address

pamask

int

no

Physical Address Mask

tag

int

no

Tag of idle operation

va

int

no

Virtual Address

vamask

int

no

Virtual Address Mask

Command add-skip Arguments

Name Type Required Description

context

string

no

Context

pa

int

no

Physical Address

pamask

int

no

Physical Address Mask

steps

int

yes

Steps to skip

va

int

no

Virtual Address

vamask

int

no

Virtual Address Mask

Command assemble Arguments

Name Type Required Description

inst

string

yes

Instruction to assemble.

pa

int

no

Physical address

va

int

no

Virtual address

Command disable-stats Arguments

Name Type Required Description

stat

string

yes

Name of statistics (executed-translated-instructions, executed-translated-blocks)

Command disassemble-block Arguments

Name Type Required Description

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Command disassemble-block-option Arguments

Name Type Required Description

option

string

yes

Option to set: 'default-syntax', 'alternate-syntax', 'latency', 'no-latency'.

Command enable-stats Arguments

Name Type Required Description

stat

string

yes

Name of statistics (executed-translated-instructions, executed-translated-blocks)

Command set-reg Arguments

Name Type Required Description

reg

string

yes

Register name

value

int

yes

Value

Command setPC Arguments

Name Type Required Description

pc

int

yes

New pc

Command setTLB0Entry Arguments

Name Type Required Description

mas1

int

yes

MAS1

mas2

int

yes

MAS2

mas3

int

yes

MAS3

mas7

int

yes

MAS7

set

int

yes

Set [0-127]

way

int

yes

Way [0-3]

Command setTLB1Entry Arguments

Name Type Required Description

entry

int

yes

Entry [0-15]

mas1

int

yes

MAS1

mas2

int

yes

MAS2

mas3

int

yes

MAS3

mas7

int

yes

MAS7

Command translate-block Arguments

Name Type Required Description

count

int

no

Number of instructions, omit for automatic.

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Command translate-func Arguments

Name Type Required Description

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Note on Trap Support

TEMU supports the raising of traps, via either the API or the command line. Some Book-E PowerPC traps are parametarized, and the standard interfaces sets the parameters to zero.

The parameters need to be applied manually after using the interfaces or command line.

Table 1. Traps Requiring Manual Setting of Registers Afterwards
Trap Name Note

data_storage

dear and esr registers need to be set.

instruction_storage

esr register needs to be set.

alignment_interrupt

dear and esr registers need to be set.

program_interrupt

esr needs to be set (upper 8 bits).

data_TLB_error

dear and esr registers need to be set.

In addition, the e500v2 core does not support all Book-E traps, please consult the hardware documentation for further information.

Limitations

  • No static timing model is defined at this moment. That means that one instruction take one cycle to finish.

  • MMU model is not yet validated against hardware.

  • Cache control interfaces are not implemented or supported, this can be addressed if needed.

  • The errata described in the e500CORERMAD is not correctly simulated. the following instructions deviates from hardware errata and are implemented as documented instead:

    • evmwlssiaaw

    • evmwlssianw

    • evmwlusiaaw

    • evmwlusianw