E500v2

The E500v2 models the NXP processor core of the same name. This includes the SPE instruction set.

@e500v2 Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @e500v2

new

Create new instance of e500v2

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

e500v2 Reference

Properties

Name Type Description

CPUId

uint32_t

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

acc

uint64_t

Accumulator register

atbl

uint32_t

atbu

uint32_t

bbear

uint32_t

bbtar

uint32_t

bucsr

uint32_t

config.exitOnSync

uint8_t

cpi

double

Cycles per instruction

cr

uint32_t

csrrs

[uint32_t; 2]

ctr

uint32_t

dac1

uint32_t

dac2

uint32_t

dbcrs

[uint32_t; 3]

dbsr

uint32_t

dear

uint32_t

dec

uint32_t

decar

uint32_t

devices

temu_IfaceRefArray

dvc1

uint32_t

dvc2

uint32_t

esr

uint32_t

freq

int64_t

Frequency in Hz

gprs

[uint64_t; 32]

hids

[uint32_t; 2]

iac1

uint32_t

iac2

uint32_t

ipc

double

Instructions per cycle

irq

int8_t

irqClient

temu_IfaceRef/ <unknown>

ivors

[uint32_t; 64]

ivpr

uint32_t

l1cfg0

uint32_t

l1cfg1

uint32_t

lr

uint32_t

mass

[uint32_t; 7]

mcar

uint32_t

mcsr

uint32_t

mcsrrs

[uint32_t; 2]

memAccess

temu_IfaceRef/ <unknown>

memAccessL2

temu_IfaceRef/ <unknown>

Level 2 memory access interface (physical)

memory

temu_IfaceRef/ <unknown>

mmucfg

uint32_t

mmucsr0

uint32_t

msr

uint32_t

nextEvent

int64_t

Next event

parentTimeSource

*void

Parent time source

pc

uint32_t

pid0

uint32_t

pid1

uint32_t

pid2

uint32_t

pir

uint32_t

pmc0

uint32_t

pmc1

uint32_t

pmc2

uint32_t

pmc3

uint32_t

pmgc0

uint32_t

pmlca0

uint32_t

pmlca1

uint32_t

pmlca2

uint32_t

pmlca3

uint32_t

pmlcb0

uint32_t

pmlcb1

uint32_t

pmlcb2

uint32_t

pmlcb3

uint32_t

powerState

uint32_t

pvr

uint32_t

spefscr

uint32_t

sprgs

[uint32_t; 8]

srrs

[uint32_t; 2]

startSteps

int64_t

Start steps of the time source

state

int32_t

steps

int64_t

Steps of the time source

svr

uint32_t

targetSteps

int64_t

Target steps of the time source

tcr

uint32_t

tlb0cfg

uint32_t

tlb1cfg

uint32_t

tsr

uint32_t

upmc0

uint32_t

upmc1

uint32_t

upmc2

uint32_t

upmc3

uint32_t

upmgc0

uint32_t

upmlca0

uint32_t

upmlca1

uint32_t

upmlca2

uint32_t

upmlca3

uint32_t

upmlcb0

uint32_t

upmlcb1

uint32_t

upmlcb2

uint32_t

upmlcb3

uint32_t

usrpg0

uint32_t

xer

uint32_t

Interfaces

Name Type Description

ClockIface

ClockIface

CpuIface

temu::CpuIface

InvalidMemAccessIface

MemAccessIface

IrqIface

IrqCtrlIface

MemoryIface

MemoryIface

MmuMemAccessIface

MemAccessIface

MMU access interface

ObjectIface

ObjectIface

PowerIface

PowerIface

PowerPCIface

temu::PowerPCIface

ResetIface

ResetIface

Ports

Prop Iface Description

irqClient

IrqIface

interrupt controller interface

Commands

Name Description

delete

Dispose instance of e500v2

printTLB0

Print TLB0

printTLB1

Print TLB1

raiseCritical

Raise critical interrupt

raiseExternal

Raise external interrupt

setPC

Set PC

setTLB0Entry

Add entry to TLB0

setTLB1Entry

Add entry to TLB1

Command setPC Arguments

Name Type Required Description

pc

int

yes

New pc

Command setTLB0Entry Arguments

Name Type Required Description

mas1

int

yes

MAS1

mas2

int

yes

MAS2

mas3

int

yes

MAS3

mas7

int

yes

MAS7

set

int

yes

Set [0-127]

way

int

yes

Way [0-3]

Command setTLB1Entry Arguments

Name Type Required Description

entry

int

yes

Entry [0-15]

mas1

int

yes

MAS1

mas2

int

yes

MAS2

mas3

int

yes

MAS3

mas7

int

yes

MAS7

Limitations

  • No static timing model is defined at this moment. That means that one instruction take one cycle to finish.

  • AltiVec instructions are not implemented at this moment. These can be added if such a PowerPC model is requested.

  • MMU model is not yet validated against hardware.

  • Cache control interfaces are not implemented or supported, this can be addressed if needed.

  • The errata described in the e500CORERMAD is not correctly simulated. the following instructions deviates from hardware errata and are implemented as documented instead:

    • evmwlssiaaw

    • evmwlssianw

    • evmwlusiaaw

    • evmwlusianw