GRLIB GRETH Model
The GRETH model is available in the GrEth plugin. The model needs to be combined with a MDIOBus, PHY and Ethernet model.
The GRETH model implements the behaviour of both GRETH and GRETH_GBIT.
Loading the Plugin
import BusModels
import GrEth
GRETH.new name=greth0
GenericPHY.new name=phy0
EthernetLink.new name=eth0
connect a=greth0.phy b=phy0:PHYIface
connect a=greth0.mdioBus b=phy0:MDIOIface
connect a=apbctrl0.slaves b=greth0:ApbIface
greth0.setMAC mac="00:00:00:00:00:01"
connect a=phy0.mac b=greth0:MACIface
eth0.connect device=phy0:PHYIface
Configuration
The config.gbitVariant property can be set to enable GRETH_GBIT extensions.
The extensions includes:
- 
Gigabit speed. 
- 
IP header checksum offloading. 
- 
TCP checksum offloading. 
- 
UDP checksum offloading. 
- 
Scatter / gather send lists. 
@GRETH Reference
GRETH Reference
Properties
| Name | Type | Description | 
|---|---|---|
| Class | *void | Class object | 
| Component | *void | Pointer to component object if part of component | 
| ETHCTR | uint32_t | Ethernet Control Register | 
| ETHMDC | uint32_t | Ethernet MDIO Control and Status Register | 
| ETHRDP | uint32_t | Ethernet Receiver Descriptor Pointer Register | 
| ETHSIS | uint32_t | Ethernet Status and Interrupt Source Register | 
| ETHTDP | uint32_t | Ethernet Transmitter Descriptor Pointer Register | 
| LoggingFlags | uint64_t | Flags for logging info | 
| MACLSB | uint32_t | Ethernet MAC Address LSB | 
| MACMSB | uint32_t | Ethernet MAC Address MSB | 
| Name | *char | Object name | 
| TimeSource | *void | Time source object | 
| config.checkCrc | uint8_t | Enable ethernet frame CRC checking. | 
| config.checkIpCrc | uint8_t | Enable IP header CRC checking. | 
| config.checkTcpCrc | uint8_t | Enable TCP header CRC checking. | 
| config.checkUdpCrc | uint8_t | Enable UDP header CRC checking. | 
| config.gbitVariant | uint8_t | Enable GRETH_GBIT behaviour. | 
| config.generateCrc | uint8_t | Enable ethernet frame CRC generation. | 
| config.irq | uint8_t | IRQ | 
| config.logTraffic | uint8_t | Enable traffic logging | 
| irqCtrl | temu_IfaceRef/ <unknown> | IRQ controller. | 
| mac | *char | Set MAC by string | 
| mdioBus | temu_IfaceRef/ <unknown> | MDIO bus. | 
| memAccess | temu_IfaceRef/ <unknown> | Memory access (for DMA). | 
| memory | temu_IfaceRef/ <unknown> | Memory (deprecated) | 
| phy | temu_IfaceRef/ <unknown> | PHY device. | 
Interfaces
| Name | Type | Description | 
|---|---|---|
| ApbIface | ApbIface | APB P&P interface | 
| DeviceIface | DeviceIface | |
| MACIface | temu::MACIface | MAC interface | 
| MemAccessIface | MemAccessIface | Mem access interface | 
| ResetIface | ResetIface | 
Registers
| Register support is currently experimental! | 
Register Bank registers
Register ETHCTR
- Description
- 
Ethernet Control Register 
- Reset value
- 
0x00000000 
- Warm reset mask
- 
0x00000000 
| Field | Mask | Reset | Description | 
|---|---|---|---|
| EA | 
 | 
 | EDCL available | 
| BS | 
 | 
 | EDCL buffer size | 
| GA | 
 | 
 | Gigabit MAC | 
| MA | 
 | 
 | MDIO interrupts supported | 
| MC | 
 | 
 | Multicast supported | 
| SP | 
 | 
 | Speed | 
| RS | 
 | 
 | Reset | 
| PM | 
 | 
 | Open Packet Mode | 
| FD | 
 | 
 | Full Duplex | 
| RI | 
 | 
 | Enable Receiver Interrupts | 
| TI | 
 | 
 | Enable Transmitter Interrupts | 
| RE | 
 | 
 | Receive Enable | 
| TE | 
 | 
 | Transmit Enable | 
Register ETHMDC
- Description
- 
Ethernet MDIO Control and Status Register 
- Reset value
- 
0x00000000 
- Warm reset mask
- 
0x00000000 
| Field | Mask | Reset | Description | 
|---|---|---|---|
| Data | 
 | 
 | Data for MMI read / write | 
| PHY_ADDR | 
 | 
 | PHY address | 
| REG_ADDR | 
 | 
 | MII reg addr | 
| NV | 
 | 
 | Not valid | 
| BU | 
 | 
 | Busy | 
| LF | 
 | 
 | Link fail | 
| RD | 
 | 
 | Read | 
| WR | 
 | 
 | Write | 
Register ETHRDP
- Description
- 
Ethernet Receiver Descriptor Pointer Register 
- Reset value
- 
0x00000000 
- Warm reset mask
- 
0x00000000 
| Field | Mask | Reset | Description | 
|---|---|---|---|
| RXDTRA | 
 | 
 | Rx desc base address | 
| RX_DESCRIPTOR_PTR | 
 | 
 | Rx desc offset | 
Register ETHSIS
- Description
- 
Ethernet Status and Interrupt Source Register 
- Reset value
- 
0x00000000 
- Warm reset mask
- 
0x00000000 
| Field | Mask | Reset | Description | 
|---|---|---|---|
| IA | 
 | 
 | Invalid Address | 
| TS | 
 | 
 | Too Small | 
| TA | 
 | 
 | Transmitter AHB Error | 
| RA | 
 | 
 | Receiver AHB Error | 
| TI | 
 | 
 | Transmitter Interrupt | 
| RI | 
 | 
 | Receiver Interrupt | 
| TE | 
 | 
 | Transmitter Error | 
| RE | 
 | 
 | Receiver Error | 
Register ETHTDP
- Description
- 
Ethernet Transmitter Descriptor Pointer Register 
- Reset value
- 
0x00000000 
- Warm reset mask
- 
0xfffffbf8 
| Field | Mask | Reset | Description | 
|---|---|---|---|
| TXDTRA | 
 | 
 | Tx desc base address | 
| TX_DESCRIPTOR_PTR | 
 | 
 | Tx desc offset |