GRLIB GRETH Model

The GRETH model is available in the GrEth plugin. The model needs to be combined with a MDIOBus, PHY and Ethernet model.

The GRETH model implements the behaviour of both GRETH and GRETH_GBIT.

Loading the Plugin

import BusModels
import GrEth
GRETH.new name=greth0
GenericPHY.new name=phy0
EthernetLink.new name=eth0
connect a=greth0.phy b=phy0:PHYIface
connect a=greth0.mdioBus b=phy0:MDIOIface
connect a=apbctrl0.slaves b=greth0:ApbIface
greth0.setMAC mac="00:00:00:00:00:01"
connect a=phy0.mac b=greth0:MACIface
eth0.connect device=phy0:PHYIface

Configuration

The config.gbitVariant property can be set to enable GRETH_GBIT extensions. The extensions includes:

  • Gigabit speed.

  • IP header checksum offloading.

  • TCP checksum offloading.

  • UDP checksum offloading.

  • Scatter / gather send lists.

@GRETH Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GRETH

new

Create new instance of GRETH

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GRETH Reference

Properties

Name Type Description

CTRLColdResetValue

uint32_t

Control register

CTRLForcedBits

uint32_t

Control register

CTRLForcedFlippedBits

uint32_t

Control register

CTRLReadMask

uint32_t

Control register

CTRLResetMask

uint32_t

Control register

CTRLResetValue

uint32_t

Control register

CTRLWriteMask

uint32_t

Control register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

EDCLIP

uint32_t

EDCL IP register

EDCLIPColdResetValue

uint32_t

EDCL IP register

EDCLIPForcedBits

uint32_t

EDCL IP register

EDCLIPForcedFlippedBits

uint32_t

EDCL IP register

EDCLIPReadMask

uint32_t

EDCL IP register

EDCLIPResetMask

uint32_t

EDCL IP register

EDCLIPResetValue

uint32_t

EDCL IP register

EDCLIPWriteMask

uint32_t

EDCL IP register

EMACLSB

uint32_t

EDCL MAC address LSB register

EMACLSBColdResetValue

uint32_t

EDCL MAC address LSB register

EMACLSBForcedBits

uint32_t

EDCL MAC address LSB register

EMACLSBForcedFlippedBits

uint32_t

EDCL MAC address LSB register

EMACLSBReadMask

uint32_t

EDCL MAC address LSB register

EMACLSBResetMask

uint32_t

EDCL MAC address LSB register

EMACLSBResetValue

uint32_t

EDCL MAC address LSB register

EMACLSBWriteMask

uint32_t

EDCL MAC address LSB register

EMACMSB

uint32_t

EDCL MAC address MSB register

EMACMSBColdResetValue

uint32_t

EDCL MAC address MSB register

EMACMSBForcedBits

uint32_t

EDCL MAC address MSB register

EMACMSBForcedFlippedBits

uint32_t

EDCL MAC address MSB register

EMACMSBReadMask

uint32_t

EDCL MAC address MSB register

EMACMSBResetMask

uint32_t

EDCL MAC address MSB register

EMACMSBResetValue

uint32_t

EDCL MAC address MSB register

EMACMSBWriteMask

uint32_t

EDCL MAC address MSB register

ETHCTR

uint32_t

Control register

ETHMDC

uint32_t

MDIO control and status register

ETHRDP

uint32_t

Receiver descriptor base address register

ETHSIS

uint32_t

Status register

ETHTDP

uint32_t

Transmitter descriptor base address register

HLSB

uint32_t

Hash table LSB register

HLSBColdResetValue

uint32_t

Hash table LSB register

HLSBForcedBits

uint32_t

Hash table LSB register

HLSBForcedFlippedBits

uint32_t

Hash table LSB register

HLSBReadMask

uint32_t

Hash table LSB register

HLSBResetMask

uint32_t

Hash table LSB register

HLSBResetValue

uint32_t

Hash table LSB register

HLSBWriteMask

uint32_t

Hash table LSB register

HMSB

uint32_t

Hash table MSB register

HMSBColdResetValue

uint32_t

Hash table MSB register

HMSBForcedBits

uint32_t

Hash table MSB register

HMSBForcedFlippedBits

uint32_t

Hash table MSB register

HMSBReadMask

uint32_t

Hash table MSB register

HMSBResetMask

uint32_t

Hash table MSB register

HMSBResetValue

uint32_t

Hash table MSB register

HMSBWriteMask

uint32_t

Hash table MSB register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

MACLSB

uint32_t

MAC address LSB register

MACLSBColdResetValue

uint32_t

MAC address LSB register

MACLSBForcedBits

uint32_t

MAC address LSB register

MACLSBForcedFlippedBits

uint32_t

MAC address LSB register

MACLSBReadMask

uint32_t

MAC address LSB register

MACLSBResetMask

uint32_t

MAC address LSB register

MACLSBResetValue

uint32_t

MAC address LSB register

MACLSBWriteMask

uint32_t

MAC address LSB register

MACMSB

uint32_t

MAC address MSB register

MACMSBColdResetValue

uint32_t

MAC address MSB register

MACMSBForcedBits

uint32_t

MAC address MSB register

MACMSBForcedFlippedBits

uint32_t

MAC address MSB register

MACMSBReadMask

uint32_t

MAC address MSB register

MACMSBResetMask

uint32_t

MAC address MSB register

MACMSBResetValue

uint32_t

MAC address MSB register

MACMSBWriteMask

uint32_t

MAC address MSB register

MDIOColdResetValue

uint32_t

MDIO control and status register

MDIOForcedBits

uint32_t

MDIO control and status register

MDIOForcedFlippedBits

uint32_t

MDIO control and status register

MDIOReadMask

uint32_t

MDIO control and status register

MDIOResetMask

uint32_t

MDIO control and status register

MDIOResetValue

uint32_t

MDIO control and status register

MDIOWriteMask

uint32_t

MDIO control and status register

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

RXBASEColdResetValue

uint32_t

Receiver descriptor base address register

RXBASEForcedBits

uint32_t

Receiver descriptor base address register

RXBASEForcedFlippedBits

uint32_t

Receiver descriptor base address register

RXBASEReadMask

uint32_t

Receiver descriptor base address register

RXBASEResetMask

uint32_t

Receiver descriptor base address register

RXBASEResetValue

uint32_t

Receiver descriptor base address register

RXBASEWriteMask

uint32_t

Receiver descriptor base address register

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

STATColdResetValue

uint32_t

Status register

STATForcedBits

uint32_t

Status register

STATForcedFlippedBits

uint32_t

Status register

STATReadMask

uint32_t

Status register

STATResetMask

uint32_t

Status register

STATResetValue

uint32_t

Status register

STATWriteMask

uint32_t

Status register

TXBASEColdResetValue

uint32_t

Transmitter descriptor base address register

TXBASEForcedBits

uint32_t

Transmitter descriptor base address register

TXBASEForcedFlippedBits

uint32_t

Transmitter descriptor base address register

TXBASEReadMask

uint32_t

Transmitter descriptor base address register

TXBASEResetMask

uint32_t

Transmitter descriptor base address register

TXBASEResetValue

uint32_t

Transmitter descriptor base address register

TXBASEWriteMask

uint32_t

Transmitter descriptor base address register

TimeSource

*void

Time source object

config.checkCrc

uint8_t

Enable ethernet frame CRC checking.

config.checkIpCrc

uint8_t

Enable IP header CRC checking.

config.checkTcpCrc

uint8_t

Enable TCP header CRC checking.

config.checkUdpCrc

uint8_t

Enable UDP header CRC checking.

config.gbitVariant

uint8_t

Enable GRETH_GBIT behaviour.

config.generateCrc

uint8_t

Enable ethernet frame CRC generation.

config.irq

uint8_t

IRQ

config.littleEndian

uint8_t

Endianess of memory interface.

config.logTraffic

uint8_t

Enable traffic logging

irqCtrl

temu_IfaceRef/ <unknown>

IRQ controller.

mac

*char

Set MAC by string

mdioBus

temu_IfaceRef/ <unknown>

MDIO bus.

memAccess

temu_IfaceRef/ <unknown>

Memory access (for DMA).

phy

temu_IfaceRef/ <unknown>

PHY device.

Interfaces

Name Type Description

ApbIface

ApbIface

APB P&P interface

DeviceIface

DeviceIface

MACIface

temu::MACIface

MAC interface

MemAccessIface

MemAccessIface

Mem access interface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Registers

Register support is currently experimental!

Register Bank Regs

Register CTRL
Description

Control register

Reset value

0x00000000

Warm reset mask

0xfe007fff

Diagram
Field Mask Reset Description

EA

0x80000000

0x0

EDCL available

BS

0x70000000

0x0

EDCL buffer size

GA

0x08000000

0x0

Gigabit MAC available

MA

0x04000000

0x0

MDIO interrupts supported

MC

0x02000000

0x0

Multicast available

ED

0x00004000

0x0

EDCL disable

RD

0x00002000

0x0

RAM debug enable

DD

0x00001000

0x0

Disable duplex detection

ME

0x00000800

0x0

Multicast enable

PI

0x00000400

0x0

PHY status change interrupt enable

BM

0x00000200

0x0

Burst mode

GB

0x00000100

0x0

Gigabit speed mode

SP

0x00000080

0x0

Speed

RS

0x00000040

0x0

Reset

PM

0x00000020

0x0

Promiscuous mode

FD

0x00000010

0x0

Full duplex

RI

0x00000008

0x0

Receiver interrupt enable

TI

0x00000004

0x0

Transmitter interrupt enable

RE

0x00000002

0x0

Receive enable

TE

0x00000001

0x0

Transmit enable
Register STAT
Description

Status register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

PS

0x00000100

-

PHY status changes

IA

0x00000080

-

Invalid address

TS

0x00000040

-

Too small

TA

0x00000020

-

Transmitter AHB error

RA

0x00000010

-

Receiver AHB error

TI

0x00000008

-

Transmit successful

RI

0x00000004

-

Receive successful

TE

0x00000002

-

Transmitter error

RE

0x00000001

-

Receiver error
Register MACMSB
Description

MAC address MSB register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

MSB

0x0000ffff

0x0

Two most significant bytes of the MAC address
Register MACLSB
Description

MAC address LSB register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LSB

0xffffffff

0x0

Four least significant bytes of the MAC address
Register MDIO
Description

MDIO control and status register

Reset value

0x00000000

Warm reset mask

0xffffffcf

Diagram
Field Mask Reset Description

DATA

0xffff0000

0x0

Data

PHYADDR

0x0000f800

0x0

PHY address

REGADDR

0x000007c0

0x0

Register address

BU

0x00000008

0x0

Busy

LF

0x00000004

0x0

Link fail

RD

0x00000002

0x0

Read

WR

0x00000001

0x0

Write
Register TXBASE
Description

Transmitter descriptor base address register

Reset value

0x00000000

Warm reset mask

0xfffffff8

Diagram
Field Mask Reset Description

BASEADDR

0xfffffc00

0x0

Transmitter descriptor table base address

DESCPNT

0x000003f8

0x0

Descriptor pointer
Register RXBASE
Description

Receiver descriptor base address register

Reset value

0x00000000

Warm reset mask

0xfffffff8

Diagram
Field Mask Reset Description

BASEADDR

0xfffffc00

0x0

Receiver descriptor table base address

DESCPNT

0x000003f8

0x0

Descriptor pointer
Register EDCLIP
Description

EDCL IP register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

IP

0xffffffff

0x0

EDCL IP address
Register HMSB
Description

Hash table MSB register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

HASH

0xffffffff

0x0

Hash table MSB
Register HLSB
Description

Hash table LSB register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

HASH

0xffffffff

0x0

Hash table LSB
Register EMACMSB
Description

EDCL MAC address MSB register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

MSB

0x0000ffff

0x0

Two most significant bytes of the EDCL MAC address
Register EMACLSB
Description

EDCL MAC address LSB register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LSB

0xffffffff

0x0

Four least significant bytes of the EDCL MAC address

Commands

Name Description

delete

Dispose instance of GRETH

sendFrame

Send frame

setMAC

Set MAC address

Command sendFrame Arguments

Name Type Required Description

mac

string

yes

MAC address of target

Command setMAC Arguments

Name Type Required Description

mac

string

yes

MAC address to set

Limitations

  • Multicast groups are not yet supported.

  • ECDL mode is not supported.