GRLIB IRQAMP Model

The IRQAMP is part of the GRLIB device library from Gaisler. It is a multiprocessor capable interrupt controller.

The controller supports among things the routing of interrupts to different processor cores, and also broadcasted interrupts.

The device supports the boot address registers.

Loading the Plugin

import IrqAMp

Configuration

@IRQAMP Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @IRQAMP

new

Create new instance of IRQAMP

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

IRQAMP Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

bootAddress

[uint32_t; 16]

Boot addresses

broadcast

uint32_t

config.bootReg

uint8_t

Enable boot address registers

config.enExtIrq

uint8_t

config.experimentalDisableExtIrqBit

uint8_t

Disable setting the shared ext-irq bit when raising interrupts

config.irqMapping

uint8_t

Enable interrupt mapping

config.logInterrupts

uint8_t

config.nCpu

uint8_t

config.traceReads

uint8_t

config.traceWrites

uint8_t

cpu

[temu_IfaceRef; 16]/ <unknown>

Processors

dynamicReset

[temu_IfaceRef; 16]/ <unknown>

Dynamic reset address interface (typically implemented by CPU)

extIntAck

[uint32_t; 16]

force

[uint32_t; 16]

interruptMap

[uint32_t; 8]

irqClear

uint32_t

irqCtrl

[temu_IfaceRef; 16]/ <unknown>

Upstream interrupt controllers

irqForce0

uint32_t

irqLevel

uint32_t

irqPending

uint32_t

mask

[uint32_t; 16]

mpStatus

uint32_t

pnp.bar

uint32_t

pnp.config

uint32_t

Interfaces

Name Type Description

ApbIface

ApbIface

DeviceIface

DeviceIface

IrqClientIface

IrqClientIface

uptree interrupt handlers (e.g. CPUs)

IrqIface

IrqCtrlIface

MemAccessIface

MemAccessIface

ResetIface

ResetIface

Ports

Prop Iface Description

irqCtrl

IrqClientIface

irq port

Commands

Name Description

delete

Dispose instance of IRQAMP

raiseExternalIrq

Raise interrupt

Command raiseExternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number

Limitations

The following deviations from real hardware are known to exist with this model:

  • Broadcasted interrupts are broadcasted at the current time to all CPUs. If triggered by a non-synchronised event, the interrupt is raised at different times on the different cores. Depending on the IRQ frequency and the configured quanta length, this may result in problems for some software.

  • The model does not verify that register writes come from the correct CPU at the moment.