GRLIB IRQAMP Model
The IRQAMP is part of the GRLIB device library from Gaisler. It is a multiprocessor capable interrupt controller.
The controller supports among things the routing of interrupts to different processor cores, and also broadcasted interrupts.
The device supports the boot address registers.
@IRQAMP Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
TimeSource |
*void |
Time source object |
IRQAMP Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
ERRSTAT |
uint32_t |
Error mode status register |
ICSELR |
[uint32_t; 2] |
Interrupt controller select register |
ITCNT |
[uint32_t; 16] |
Interrupt timestamp counter registers |
ITSTAMPAC |
[uint32_t; 16] |
Interrupt acknowledge timestamp registers |
ITSTAMPAS |
[uint32_t; 16] |
Interrupt assertion timestamp registers |
ITSTMPC |
[uint32_t; 16] |
Interrupt timestamp control registers |
LocalName |
*char |
Local name (in component, if applicable) |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
PBOOT |
uint32_t |
Processor boot register |
TimeSource |
*void |
Time source object |
acknowledgedInterrupts |
[uint64_t; 16] |
|
bootAddress |
[uint32_t; 16] |
Boot addresses |
broadcast |
uint32_t |
|
config.bootReg |
uint8_t |
Enable boot address registers |
config.enExtIrq |
uint8_t |
|
config.experimentalDisableExtIrqBit |
uint8_t |
Disable setting the shared ext-irq bit when raising interrupts (deprecated) |
config.hasErrorModeStatusRegister |
uint8_t |
Enable error mode status register |
config.hasProcessorBootRegister |
uint8_t |
Enable processor boot register |
config.interruptLogMask |
uint64_t |
|
config.irqMapping |
uint8_t |
Enable interrupt mapping |
config.legacyCpuControlDisabled |
uint8_t |
|
config.littleEndian |
uint8_t |
Endianess of memory interface. |
config.logInterrupts |
uint8_t |
|
config.nCpu |
uint8_t |
|
config.numberOfTimeStamps |
uint8_t |
Number of timestamp registers |
config.traceReads |
uint8_t |
|
config.traceWrites |
uint8_t |
|
cpu |
[temu_IfaceRef; 16]/ <unknown> |
Processors |
dynamicReset |
[temu_IfaceRef; 16]/ <unknown> |
Dynamic reset address interface (typically implemented by CPU) |
extIntAck |
[uint32_t; 16] |
|
force |
[uint32_t; 16] |
|
interruptMap |
[uint32_t; 8] |
|
irqClear |
uint32_t |
|
irqCtrl |
[temu_IfaceRef; 16]/ <unknown> |
Upstream interrupt controllers |
irqLevel |
uint32_t |
|
irqPending |
uint32_t |
|
irqSignalStatus |
[uint16_t; 16] |
|
irqTimestampMap |
[uint32_t; 32] |
Auxiliary helper properties to map IRQ numbers to timestamp counters |
mask |
[uint32_t; 16] |
|
mpStatus |
uint32_t |
|
pnp.bar |
uint32_t |
|
pnp.config |
uint32_t |
|
raisedInterrupts |
[uint64_t; 16] |
Interfaces
| Name | Type | Description |
|---|---|---|
ApbIface |
ApbIface |
|
DeviceIface |
DeviceIface |
|
IrqClientIface |
IrqClientIface |
uptree interrupt handlers (e.g. CPUs) |
IrqIface |
IrqCtrlIface |
|
LegacyDisableIface |
SignalIface |
Signal interface to toggle legacy mode. |
MemAccessIface |
MemAccessIface |
|
RegisterIface |
temu::RegisterIface |
|
ResetIface |
ResetIface |
Registers
| Register support is currently experimental! |
Register Bank default
Register ICSELR
- Description
-
Interrupt controller select register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register ITCNT
- Description
-
Interrupt timestamp counter registers
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register ITSTAMPAC
- Description
-
Interrupt acknowledge timestamp registers
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register ITSTAMPAS
- Description
-
Interrupt assertion timestamp registers
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register ITSTMPC
- Description
-
Interrupt timestamp control registers
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register PBOOT
- Description
-
Processor boot register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register bootAddress
- Description
-
Boot addresses
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register broadcast
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register extIntAck
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register force
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register interruptMap
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register irqClear
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register irqLevel
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register irqPending
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Limitations
The following deviations from real hardware are known to exist with this model:
-
Broadcasted interrupts are broadcasted at the current time to all CPUs. If triggered by a non-synchronised event, the interrupt is raised at different times on the different cores. Depending on the IRQ frequency and the configured quanta length, this may result in problems for some software.
-
The model does not verify that register writes come from the correct CPU at the moment.