GRLIB IRQAMP Model

The IRQAMP is part of the GRLIB device library from Gaisler. It is a multiprocessor capable interrupt controller.

The controller supports among things the routing of interrupts to different processor cores, and also broadcasted interrupts.

The device supports the boot address registers.

Loading the Plugin

import IrqAMp

Configuration

@IRQAMP Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @IRQAMP

new

Create new instance of IRQAMP

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

IRQAMP Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

ERRSTAT

uint32_t

Error mode status register

ICSELR

[uint32_t; 2]

Interrupt controller select register

ITCNT

[uint32_t; 16]

Interrupt timestamp counter registers

ITSTAMPAC

[uint32_t; 16]

Interrupt acknowledge timestamp registers

ITSTAMPAS

[uint32_t; 16]

Interrupt assertion timestamp registers

ITSTMPC

[uint32_t; 16]

Interrupt timestamp control registers

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

PBOOT

uint32_t

Processor boot register

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

acknowledgedInterrupts

[uint64_t; 16]

bootAddress

[uint32_t; 16]

Boot addresses

broadcast

uint32_t

config.bootReg

uint8_t

Enable boot address registers

config.enExtIrq

uint8_t

config.experimentalDisableExtIrqBit

uint8_t

Disable setting the shared ext-irq bit when raising interrupts (deprecated)

config.hasErrorModeStatusRegister

uint8_t

Enable error mode status register

config.hasProcessorBootRegister

uint8_t

Enable processor boot register

config.interruptLogMask

uint64_t

config.irqMapping

uint8_t

Enable interrupt mapping

config.legacyCpuControlDisabled

uint8_t

config.littleEndian

uint8_t

Endianess of memory interface.

config.logInterrupts

uint8_t

config.nCpu

uint8_t

config.numberOfTimeStamps

uint8_t

Number of timestamp registers

config.traceReads

uint8_t

config.traceWrites

uint8_t

cpu

[temu_IfaceRef; 16]/ <unknown>

Processors

dynamicReset

[temu_IfaceRef; 16]/ <unknown>

Dynamic reset address interface (typically implemented by CPU)

extIntAck

[uint32_t; 16]

force

[uint32_t; 16]

interruptMap

[uint32_t; 8]

irqClear

uint32_t

irqCtrl

[temu_IfaceRef; 16]/ <unknown>

Upstream interrupt controllers

irqLevel

uint32_t

irqPending

uint32_t

irqSignalStatus

[uint16_t; 16]

irqTimestampMap

[uint32_t; 32]

Auxiliary helper properties to map IRQ numbers to timestamp counters

mask

[uint32_t; 16]

mpStatus

uint32_t

pnp.bar

uint32_t

pnp.config

uint32_t

raisedInterrupts

[uint64_t; 16]

Interfaces

Name Type Description

ApbIface

ApbIface

DeviceIface

DeviceIface

IrqClientIface

IrqClientIface

uptree interrupt handlers (e.g. CPUs)

IrqIface

IrqCtrlIface

LegacyDisableIface

SignalIface

Signal interface to toggle legacy mode.

MemAccessIface

MemAccessIface

RegisterIface

temu::RegisterIface

ResetIface

ResetIface

Ports

Prop Iface Description

irqCtrl

IrqClientIface

irq port

Registers

Register support is currently experimental!

Register Bank default

Register ILEVEL
Description

Interrupt level register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IPEND
Description

Interrupt pending register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IFORCE
Description

Interrupt force register (ncpu = 1)

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ICLEAR
Description

Interrupt clear register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register MPSTAT
Description

Multiprocessor status register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register BRDCST
Description

Broadcast register (ncpu > 1)

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ERRSTAT
Description

Error mode status register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ASMPCTRL
Description

Asymmetric multiprocessing control register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ICLSELR0
Description

Interrupt controller select register (CPU 0-7)

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ICLSELR1
Description

Interrupt controller select register (CPU 8-15)

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PIMASK0
Description

Processor 0 interrupt mask register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PIMASK1
Description

Processor 1 interrupt mask register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PIMASK2
Description

Processor 2 interrupt mask register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PIMASK3
Description

Processor 3 interrupt mask register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCFORCE0
Description

Processor 0 interrupt force register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCFORCE1
Description

Processor 1 interrupt force register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCFORCE2
Description

Processor 2 interrupt force register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCFORCE3
Description

Processor 3 interrupt force register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PEXTACK0
Description

Processor 0 extended interrupt acknowledge register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PEXTACK1
Description

Processor 1 extended interrupt acknowledge register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PEXTACK2
Description

Processor 2 extended interrupt acknowledge register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PEXTACK3
Description

Processor 3 extended interrupt acknowledge register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ITCNT0
Description

Timestamp counter register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ITSTMPC0
Description

Interrupt timestamp control register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ITSTMPAS0
Description

Interrupt assertion timestamp register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ITSTMPAC0
Description

Interrupt acknowledge timestamp register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ITCNT1
Description

Timestamp counter register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ITSTMPC1
Description

Interrupt timestamp control register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ITSTMPAS1
Description

Interrupt assertion timestamp register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register ITSTMPAC1
Description

Interrupt acknowledge timestamp register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register BADDR0
Description

Processor 0 boot address register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register BADDR1
Description

Processor 1 boot address register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register BADDR2
Description

Processor 2 boot address register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register BADDR3
Description

Processor 3 boot address register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IRQMAP0
Description

Interrupt map register 0

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IRQMAP1
Description

Interrupt map register 1

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IRQMAP2
Description

Interrupt map register 2

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IRQMAP3
Description

Interrupt map register 3

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IRQMAP4
Description

Interrupt map register 4

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IRQMAP5
Description

Interrupt map register 5

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IRQMAP6
Description

Interrupt map register 6

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register IRQMAP0
Description

Interrupt map register 7

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-

Commands

Name Description

delete

Dispose instance of IRQAMP

raiseExternalIrq

Raise interrupt

Command raiseExternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number

Limitations

The following deviations from real hardware are known to exist with this model:

  • Broadcasted interrupts are broadcasted at the current time to all CPUs. If triggered by a non-synchronised event, the interrupt is raised at different times on the different cores. Depending on the IRQ frequency and the configured quanta length, this may result in problems for some software.

  • The model does not verify that register writes come from the correct CPU at the moment.