Limitations

The following deviations from real hardware are known to exist. If you need the correct behavior (contact us for more info).

  • The UARTs do not support external (watchdog) clocks.

  • The UARTs do not support parity, framing errors, break signals or stop bit configuration. Note that transmission times do take into account stop and parity bits.

  • Write protection registers have no effect

  • Timer values are lazily computed on reads, the content in the case a timer is disabled is estimated on disabling time. This is in principle correct. However, the prescaler counter write has no effect, only the reload value has an effect when written. This may cause an offset of 1024 cycles when re-enabling a timer.