GRLIB GRPCI2 Model

The GRPCI2 model is available in the GrPci2 plugin.

Loading the Plugin

import GrPci2

Configuration

@GRPCI2 Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GRPCI2

new

Create new instance of GRPCI2

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GRPCI2 Reference

Properties

Name Type Description

AHB2PCI

uint32_t

AHB to PCI mapping for PCI I/O

AHBM2PCI

[uint32_t; 16]

DMA channel active

BCIM

uint32_t

PCI master prefetch burst limit

CTRL

uint32_t

Control register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DMABASE

uint32_t

DMA descriptor base address

DMACHAN

uint32_t

DMA channel active

DMACTRL

uint32_t

GRPCI2 DMA control and status register

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

PCI2AHB

[uint32_t; 6]

DMA channel active

STATCAP

uint32_t

Status and Capability register

TimeSource

*void

Time source object

config.Irq

uint8_t

PCI irq number

ioMem

temu_IfaceRef/ <unknown>

PCI i/o space object

irqCtrl

temu_IfaceRef/ <unknown>

Upward interrupt controller (i.e. on AMBA bus)

pciBus

*void

PCI bus object

pciDevices

temu_IfaceRefArray

PCI devices

pciMem

temu_IfaceRef/ <unknown>

PCI memory space object

processorMem

temu_IfaceRef/ <unknown>

Access to the processor’s memory space

Interfaces

Name Type Description

ApbIface

ApbIface

APB P&P interface

ConfigAccessIface

MemAccessIface

PCI config access interface.

IrqIface

IrqCtrlIface

PCI IRQ interface

MemAccessIface

MemAccessIface

Memory access interface (registers)

PCIBridgeIface

temu::PCIBridgeIface

PCI bridge interface.

PCIMemAccessIface

MemAccessIface

PCI memory access interfaces

Registers

Register support is currently experimental!

Register Bank default

Register AHB2PCI
Description

AHB to PCI mapping for PCI I/O

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register AHBM2PCI
Description

DMA channel active

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register BCIM
Description

PCI master prefetch burst limit

Reset value

0x000000ff

Warm reset mask

0xffff00ff

Diagram
Field Mask Reset Description

AHB_master_unmask

0xffff0000

0x0

Limit prefetch burst

burst_length

0x000000ff

0xff

Max number of beats / burst
Register CTRL
Description

Control register

Reset value

0x00000000

Warm reset mask

0xefff0fff

Diagram
Field Mask Reset Description

RE

0x80000000

0x0

Reset

MR

0x40000000

0x0

Master Reset

TR

0x20000000

0x0

Target Reset

SI

0x08000000

0x0

System Error Interrupt Enable

PE

0x04000000

0x0

Parity Error

ER

0x02000000

0x0

Master / Target Error

EI

0x01000000

0x0

Master / Target Interrupt

BusNumber

0x00ff0000

0x0

Bus number for config cycles

DFA

0x00000800

0x0

DMA fair arbitration

IB

0x00000400

0x0

Burst I/O cycles

CB

0x00000200

0x0

Burst config cycles

DIF

0x00000100

0x0

Device Interrupt Force

DeviceINTMask

0x000000f0

0x0

Device interrupt mask

HostINTMask

0x0000000f

0x0

Host interrupt mask
Register DMABASE
Description

DMA descriptor base address

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register DMACHAN
Description

DMA channel active

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register DMACTRL
Description

GRPCI2 DMA control and status register

Reset value

0x80000000

Warm reset mask

0x800fffff

Diagram
Field Mask Reset Description

SAFE

0x80000000

0x1

Arming of control field updates

CHIRQ

0x000ff000

0x0

Channel IRQ status

MA

0x00000800

0x0

Master abort

TA

0x00000400

0x0

Target abort

PE

0x00000200

0x0

Parity error

AE

0x00000100

0x0

AHB data error

DE

0x00000080

0x0

Descriptor error

NumDMAChans

0x00000070

0x0

Number of DMA channels

ACTIVE

0x00000008

0x0

DMA is active

DIS

0x00000004

0x0

DMA disable

IE

0x00000002

0x0

Interrupt enable

EN

0x00000001

0x0

DMA enable
Register PCI2AHB
Description

DMA channel active

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register STATCAP
Description

Status and Capability register

Reset value

0x00000000

Warm reset mask

0x003ff000

Diagram
Field Mask Reset Description

Host

0x80000000

0x0

Core allowed ot act as system host

MST

0x40000000

0x0

Master implemented

TAR

0x20000000

0x0

Target implemented

DMA

0x10000000

0x0

DMA implemented

DI

0x08000000

0x0

Device drives PCI INTA

HI

0x04000000

0x0

Device samples PCI INTA..D

IRQmode

0x03000000

0x0

APB IRQ mode

Trace

0x00800000

0x0

PCI trace buffer implemented

FH

0x00200000

0x0

Fake device in system slot

CFGDO

0x00100000

0x0

PCI config access done

CFGER

0x00080000

0x0

Error during PCI config access

CoreInterruptStatus

0x0007f000

0x0

Interrupt status

HostInterruptStatus

0x00000f00

0x0

Host interrupt status

FDEPTH

0x0000001c

0x0

Words in each FIFO

FNUM

0x00000003

0x0

Number of FIFOs

Commands

Name Description

delete

Dispose instance of GRPCI2

Limitations

  • The device currently only supports one AHB master. Since most systems only have one (e.g. an AHB2AHB bridge), this limitation should not be a major issue.