ARMv7-R
Attributes
Properties
| Name | Type | Description |
|---|---|---|
CPUId |
uint32_t |
|
abtregs |
[2 x uint32_t] |
|
coproc |
[16 x iref / ARMCoProcessor] |
|
cpsr |
uint32_t |
CPSR register |
cycles |
int64_t |
|
fiqregs |
[7 x uint32_t] |
|
freq |
uint64_t |
|
gprs |
[16 x uint32_t] |
|
irqClient |
iref / <unknown> |
|
irqregs |
[2 x uint32_t] |
|
machine |
iref / <unknown> |
|
memAccess |
iref / MemAccessIface |
|
memory |
iref / MemoryIface |
|
monregs |
[2 x uint32_t] |
|
nextEvent |
int64_t |
|
object.timeSource |
object |
Time source object (a cpu or machine object) |
powerState |
uint32_t |
|
sctlr |
uint32_t |
|
sctlr_rst |
uint32_t |
|
spsr |
[7 x uint32_t] |
|
state |
int32_t |
|
steps |
int64_t |
|
svcregs |
[2 x uint32_t] |
|
undregs |
[2 x uint32_t] |
Registers
| Register support is currently experimental! |
Register Bank registers
Register cpsr
CPSR register
Cold reset value: 0x13
Warm reset value: 0x13
| Field | Mask | Cold | Warm | Description |
|---|---|---|---|---|
0x80000000 |
0x0 |
0x0 |
Negative condition flag |
|
0x40000000 |
0x0 |
0x0 |
Zero condition flag |
|
0x20000000 |
0x0 |
0x0 |
Carry condition flag |
|
0x10000000 |
0x0 |
0x0 |
Overflow condition flag |
|
0x8000000 |
0x0 |
0x0 |
Cumulative saturation bit |
|
it_1_0 |
0x6000000 |
0x0 |
0x0 |
If-Then execution state |
0x3000000 |
0x0 |
0x0 |
Jazelle bit |
|
ge |
0xf0000 |
0x0 |
0x0 |
Greater than or equal flags |
it_7_2 |
0xfc00 |
0x0 |
0x0 |
If-Then execution state |
0x200 |
0x1 |
0x1 |
Endianess |
|
0x100 |
0x1 |
0x1 |
Asynchronous abort mask |
|
0x80 |
0x1 |
0x1 |
IRQ mask |
|
0x40 |
0x1 |
0x1 |
FIQ mask |
|
0x20 |
0x0 |
0x0 |
Thumb bit |
|
|
0x13 |
0x13 |
Mode |