ARMv7-R

The ARMv7-R model simulates the ARM sub architecture of the same name.

@ARMv7-R Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @ARMv7-R

new

Create new instance of ARMv7-R

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

ARMv7-R Reference

Properties

Name Type Description

CPUId

uint32_t

CPUType

int32_t

Class

*void

Class object

Component

*void

Pointer to component object if part of component

HostFlags

uint64_t

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

abtregs

[uint32_t; 2]

config.assemblerAliases

uint8_t

config.exitOnSync

uint8_t

config.handleEventWithinBlock

uint8_t

config.measureExecTime

uint8_t

coproc

[temu_IfaceRef; 16]/ <unknown>

ARM coprocessor

cpi

double

Cycles per instruction

cpsr

uint32_t

CPSR register

currentContextId

uint64_t

currentContextValid

uint8_t

currentThreadContextId

uint64_t

currentThreadContextValid

uint8_t

exitReason

int32_t

fiqregs

[uint32_t; 7]

freq

int64_t

Frequency in Hz

gprs

[uint32_t; 16]

idleSteps

int64_t

ipc

double

Instructions per cycle

irqClient

temu_IfaceRef/ <unknown>

Down stream interrupt controller (for ACKs)

irqregs

[uint32_t; 2]

mProfileClient

temu_IfaceRef/ <unknown>

Cortex-M profile exception controller

memAccess

temu_IfaceRef/ <unknown>

Level 1 memory access interface (MMU)

memReset

temu_IfaceRef/ <unknown>

Memory space reset interface

memSpace

*void

Memory space.

monregs

[uint32_t; 2]

nextEvent

int64_t

Next event

parentTimeSource

*void

Parent time source

pdcManager

temu_IfaceRef/ <unknown>

Pre-decode cache manager (normally memory space)

powerState

uint32_t

Power State property (deprecated)

sctlr

uint32_t

sctlr_rst

uint32_t

skipIdleTags

uint64_t

spsr

[uint32_t; 7]

startSteps

int64_t

Start steps of the time source

state

int32_t

steps

int64_t

Steps of the time source

stickyFlags

uint32_t

Set bit 0 to 1 to not exit CPU on halted mode.

svcregs

[uint32_t; 2]

targetExec

temu_IfaceRef/ <unknown>

Target execution interface

targetSteps

int64_t

Target steps of the time source

undregs

[uint32_t; 2]

Interfaces

Name Type Description

ARMMProfileIface

ARMMProfile

ArmIface

ARMCpu

AssemblerIface

temu::AssemblerIface

Assembler interface

ClockIface

ClockIface

CodePatternIface

temu::CodePatternIface

CpuIface

temu::CpuIface

InvalidMemAccessIface

MemAccessIface

IrqIface

IrqCtrlIface

ObjectIface

ObjectIface

PowerIface

PowerIface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Ports

Prop Iface Description

irqClient

IrqIface

interrupt controller interface

Commands

Name Description

delete

Dispose instance of ARMv7-R

disassemble

Disassemble code

Command disassemble Arguments

Name Type Required Description

count

int

no

Number of instructions

isa

string

no

Instruction set (a32 or t2), by default the current ISA is used.

pa

int

no

Physical address

va

int

no

Virtual address