PowerPC 750

The TEMU PowerPC 750 model, models a PPC750CX processor core.

@ppc750 Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @ppc750

new

Create new instance of ppc750

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

ppc750 Reference

Properties

Name Type Description

CPUId

uint32_t

CPUType

int32_t

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

TimeSource

*void

Time source object

config.exitOnSync

uint8_t

config.measureExecTime

uint8_t

cpi

double

Cycles per instruction

cr

uint32_t

ctr

uint32_t

dabr

uint32_t

dar

uint32_t

dbats

[uint32_t; 16]

dec

uint32_t

devices

temu_IfaceRefArray

dmal

uint32_t

dmau

uint32_t

dsisr

uint32_t

ear

uint32_t

exitReason

int32_t

fprs

[uint64_t; 32]

freq

int64_t

Frequency in Hz

gprs

[uint32_t; 32]

gqrs

[uint32_t; 8]

hids

[uint32_t; 4]

iabr

uint32_t

ibats

[uint32_t; 16]

ictc

uint32_t

idleSteps

int64_t

ipc

double

Instructions per cycle

irq

int8_t

irqClient

temu_IfaceRef/ <unknown>

l2cr

uint32_t

logTrampolines

uint8_t

lr

uint32_t

memAccess

temu_IfaceRef/ <unknown>

Level 1 memory access interface (MMU)

memAccessL2

temu_IfaceRef/ <unknown>

Level 2 memory access interface (physical)

memSpace

*void

Memory space.

mmcrs

[uint32_t; 2]

msr

uint32_t

nextEvent

int64_t

Next event

parentTimeSource

*void

Parent time source

pc

uint32_t

Program counter

pdcManager

temu_IfaceRef/ <unknown>

Pre-decode cache manager (normally memory space)

pmcs

[uint32_t; 4]

powerState

uint32_t

pvr

uint32_t

sdr1

uint32_t

sia

uint32_t

skipIdleTags

uint64_t

sprgs

[uint32_t; 4]

srrs

[uint32_t; 2]

startSteps

int64_t

Start steps of the time source

state

int32_t

steps

int64_t

Steps of the time source

stickyFlags

uint32_t

Set bit 0 to 1 to not exit CPU on halted mode.

targetExec

temu_IfaceRef/ <unknown>

Target execution interface

targetSteps

int64_t

Target steps of the time source

tdch

uint32_t

tdcl

uint32_t

thrms

[uint32_t; 3]

uisa

uint32_t

ummcrs

[uint32_t; 2]

upmcs

[uint32_t; 4]

wpar

uint32_t

xer

uint32_t

Interfaces

Name Type Description

AssemblerIface

temu::AssemblerIface

Assembler interface

BinaryTranslationIface

temu::BinaryTranslationControlIface

ClockIface

ClockIface

CodePatternIface

temu::CodePatternIface

CpuIface

temu::CpuIface

ExecIface

temu::TargetExecutionIface

InvalidMemAccessIface

MemAccessIface

IrqIface

IrqCtrlIface

MmuMemAccessIface

MemAccessIface

ObjectIface

ObjectIface

PhysicalMemAccessIface

MemAccessIface

PowerIface

PowerIface

PowerPCIface

temu::PowerPCIface

RegisterIface

temu::RegisterIface

ResetIface

ResetIface

VirtualMemAccessIface

MemAccessIface

Ports

Prop Iface Description

irqClient

IrqIface

interrupt controller interface

Commands

Name Description

add-call

Adds a call at the specific address. The call operation calls a predefined method which logs that it is invoked.It is primarily useful for debugging.

add-idle

Adds an explicit idle operation at the specific address.

add-skip

Adds a skip operation at the specific address. After this, the given number of instructions will be skipped.

assemble

Assemble instruction

delete

Dispose instance of ppc750

disable-dbt-logging

Disable logging when translating code.

disable-dbt-validation

Disable validation of emitted machine code.

disable-hard-code-reset

Disable hard resets of DBT emitter cache.

disable-stats

Disable statistics

disable-translation-logging

Disable jit-logging.

disassemble-block

Disassemble binary translated code block.

disassemble-block-option

Set option for disassembler. Switch between AT&T (default) and Intel (alternate) syntax. Enable / disable insruction latency in output.

enable-dbt-logging

Enable logging when translating code.

enable-dbt-validation

Enable validation of emitted machine code.

enable-hard-code-reset

Enable hard resets of DBT emitter cache.

enable-stats

Enable statistics

enable-translation-logging

Enable jit-logging.

pfregs

Print floating point registers for CPU

pregs

Print registers for CPU

pstat

Print CPU stats

set-reg

Set register

setPC

Set PC

stacktrace

ABI stack trace

translate-block

Translate block.

translate-func

Translate function.

wake-up

Wakes up the processor.

Command add-call Arguments

Name Type Required Description

pa

int

yes

Physical Address

script

path

no

Script to run when reaching address

Command add-idle Arguments

Name Type Required Description

pa

int

yes

Physical Address

tag

int

no

Tag of idle operation

Command add-skip Arguments

Name Type Required Description

pa

int

yes

Physical Address

steps

int

yes

Steps to skip

Command assemble Arguments

Name Type Required Description

inst

string

yes

Instruction to assemble.

pa

int

no

Physical address

va

int

no

Virtual address

Command disable-stats Arguments

Name Type Required Description

stat

string

yes

Name of statistics (executed-translated-instructions, executed-translated-blocks)

Command disassemble-block Arguments

Name Type Required Description

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Command disassemble-block-option Arguments

Name Type Required Description

option

string

yes

Option to set: 'default-syntax', 'alternate-syntax', 'latency', 'no-latency'.

Command enable-stats Arguments

Name Type Required Description

stat

string

yes

Name of statistics (executed-translated-instructions, executed-translated-blocks)

Command set-reg Arguments

Name Type Required Description

reg

string

yes

Register name

value

int

yes

Value

Command setPC Arguments

Name Type Required Description

pc

int

yes

New pc

Command translate-block Arguments

Name Type Required Description

count

int

no

Number of instructions, omit for automatic.

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Command translate-func Arguments

Name Type Required Description

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Note on Trap Support

TEMU supports the raising of traps, via either the API or the command line. Some Power traps are parametarized, and the standard interfaces sets the parameters to zero.

The parameters need to be applied manually after using the interfaces or command line.

Table 1. Traps Requiring Manual Setting of Registers Afterwards
Trap Name Note

data_storage

dear and esr registers need to be set.

data_segment

dear and esr registers need to be set.

instruction_storage

esr register needs to be set.

alignment

dear and esr registers need to be set.

program

esr needs to be set (upper 8 bits).

data_TLB_error

dear and esr registers need to be set.

Limitations

  • No static timing model is defined at this moment. That means that one instruction take one cycle to finish.

  • AltiVec instructions are not implemented at this moment. These can be added if such a PowerPC model is requested.

  • MMU model is not yet validated against hardware.