NOEL-V

The NOEL-V models the NOEL-V RISC-V processor core of the same name. This includes the following instruction set extensions:

  • RV64I: 64-bit base instruction set

  • RV32I: 32-bit base instruction set

  • M: Multiply and Divide

  • A: Atomics

  • FD: Single/Double precision floating point

  • B: Bit-manipulation

  • C: Compressed Instructions

  • H: Hypervisor

  • Zicntr: Counters

  • Zicsr: Control and status register

  • Zifencei: Instruction-fetch fence

The model is validated against the RISC-V conformance test suite.

@NOELV Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @NOELV

new

Create new instance of NOELV

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

NOELV Reference

Properties

Name Type Description

CPUId

uint32_t

CPUType

int32_t

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

TimeSource

*void

Time source object

aclintCsrClient

temu_IfaceRef/ <unknown>

Aclint Csr interface

aiaCsrClient

temu_IfaceRef/ <unknown>

Interrupt controller Csr interface

config.exitOnSync

uint8_t

config.logTrampolines

uint8_t

config.measureExecTime

uint8_t

cpi

double

Cycles per instruction

devices

temu_IfaceRefArray

exitReason

int32_t

fcsr

uint32_t

freq

int64_t

Frequency in Hz

gprs

[uint64_t; 32]

idleSteps

int64_t

ipc

double

Instructions per cycle

irqClient

temu_IfaceRef/ <unknown>

Interrupt controller (for ACKs)

memAccess

temu_IfaceRef/ <unknown>

Level 1 memory access interface (MMU)

memAccessL2

temu_IfaceRef/ <unknown>

Level 2 memory access interface (physical)

memReset

temu_IfaceRef/ <unknown>

Memory space reset interface

memSpace

*void

Memory space.

mhpmcounter

[uint64_t; 29]

nextEvent

int64_t

Next event

parentTimeSource

*void

Parent time source

pc

uint64_t

Program counter register (pc)

pdcManager

temu_IfaceRef/ <unknown>

Pre-decode cache manager (normally memory space)

powerState

uint32_t

privilege

uint64_t

reservationSet

[uint64_t; 3]

skipIdleTags

uint64_t

startSteps

int64_t

Start steps of the time source

state

int32_t

steps

int64_t

Steps of the time source

stickyFlags

uint32_t

Set bit 0 to 1 to not exit CPU on halted mode.

targetExec

temu_IfaceRef/ <unknown>

Target execution interface

targetSteps

int64_t

Target steps of the time source

topPendingExternalInterrupt

uint64_t

Interfaces

Name Type Description

AhbIface

AhbIface

AssemblerIface

temu::AssemblerIface

Assembler interface

BinaryTranslationIface

temu::BinaryTranslationControlIface

ClockIface

ClockIface

CodePatternIface

temu::CodePatternIface

CpuIface

temu::CpuIface

ExecIface

temu::TargetExecutionIface

InvalidMemAccessIface

MemAccessIface

IrqIface

IrqCtrlIface

PhysicalMemAccessIface

MemAccessIface

RegisterIface

temu::RegisterIface

VirtualMemAccessIface

MemAccessIface

Ports

Prop Iface Description

irqClient

IrqIface

interrupt controller interface

Commands

Name Description

assemble

Assemble instruction

delete

Dispose instance of NOELV

disable-dbt

Disable binary translation.

disable-dbt-logging

Disable logging when translating code.

disable-dbt-validation

Disable validation of emitted machine code.

disable-hard-code-reset

Disable hard resets of DBT emitter cache.

disable-stats

Disable statistics

disable-translation-logging

Disable jit-logging.

disassemble

Disassemble code

disassemble-block

Disassemble binary translated code block.

enable-dbt

Enable binary translation.

enable-dbt-logging

Enable logging when translating code.

enable-dbt-validation

Enable validation of emitted machine code.

enable-hard-code-reset

Enable hard resets of DBT emitter cache.

enable-stats

Enable statistics

enable-translation-logging

Enable jit-logging.

enableHpm

Enable performance monitor

enableTraps

Enable traps.

pregs

Print registers for CPU

pstat

Print CPU stats

setPC

Set PC

setReg

Set register

translate-block

Translate block.

translate-func

Translate function.

Command assemble Arguments

Name Type Required Description

inst

string

yes

Instruction to assemble.

pa

int

no

Physical address

va

int

no

Virtual address

Command disable-stats Arguments

Name Type Required Description

stat

string

yes

Name of statistics (executed-translated-instructions, executed-translated-blocks)

Command disassemble Arguments

Name Type Required Description

count

int

no

Number of instructions

pa

int

no

Physical address

va

int

no

Virtual address

Command disassemble-block Arguments

Name Type Required Description

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Command enable-stats Arguments

Name Type Required Description

stat

string

yes

Name of statistics (executed-translated-instructions, executed-translated-blocks)

Command enableHpm Arguments

Name Type Required Description

hpm-id

int

no

HPM index

Command setPC Arguments

Name Type Required Description

pc

int

yes

New %pc

Command setReg Arguments

Name Type Required Description

reg

string

yes

Register name

value

int

yes

Value

Command translate-block Arguments

Name Type Required Description

count

int

no

Number of instructions, omit for automatic.

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Command translate-func Arguments

Name Type Required Description

pa

int

no

Physical address of block

va

int

no

Virtual address of block

Limitations

  • The NOEL-V model is not yet validated against hardware.