GRLIB GRPCI2 Model

The GRPCI2 model is available in the GrPci2 plugin.

Loading the Plugin

import GrPci2

Configuration

@GRPCI2 Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GRPCI2

new

Create new instance of GRPCI2

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GRPCI2 Reference

Properties

Name Type Description

AHB2PCI

uint32_t

AHB to PCI mapping for PCI I/O

AHBM2PCI

[uint32_t; 16]

DMA channel active

BCIM

uint32_t

PCI master prefetch burst limit

CTRL

uint32_t

Control register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DMABASE

uint32_t

DMA descriptor base address

DMACHAN

uint32_t

DMA channel active

DMACTRL

uint32_t

GRPCI2 DMA control and status register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

PCI2AHB

[uint32_t; 6]

DMA channel active

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

STATCAP

uint32_t

Status and Capability register

TimeSource

*void

Time source object

config.Irq

uint8_t

PCI irq number

config.littleEndian

uint8_t

Endianess of memory interface.

ioMem

temu_IfaceRef/ <unknown>

PCI i/o space object

irqCtrl

temu_IfaceRef/ <unknown>

Upward interrupt controller (i.e. on AMBA bus)

pciBus

*void

PCI bus object

pciDevices

temu_IfaceRefArray

PCI devices

pciMem

temu_IfaceRef/ <unknown>

PCI memory space object

processorMem

temu_IfaceRef/ <unknown>

Access to the processor’s memory space

Interfaces

Name Type Description

ApbIface

ApbIface

APB P&P interface

ConfigAccessIface

MemAccessIface

PCI config access interface.

IrqIface

IrqCtrlIface

PCI IRQ interface

MemAccessIface

MemAccessIface

Memory access interface (registers)

PCIBridgeIface

temu::PCIBridgeIface

PCI bridge interface.

PCIMemAccessIface

MemAccessIface

PCI memory access interfaces

RegisterIface

temu::RegisterIface

Registers

Register support is currently experimental!

Register Bank default

Register CTRL
Description

Control register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register STATCAP
Description

Status and capability register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register BCIM
Description

PCI master prefetch burst limit

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register AHB2PCI
Description

AHB to PCI mapping for PCI I/O

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register DMACTRL
Description

DMA control and status register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register DMABASE
Description

DMA descriptor base address

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register DMACHAN
Description

DMA descriptor base address

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCI2AHB0
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCI2AHB1
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCI2AHB2
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCI2AHB3
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCI2AHB4
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register PCI2AHB5
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register AHBM2PCI0
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register AHBM2PCI1
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register AHBM2PCI2
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register AHBM2PCI3
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-

Commands

Name Description

delete

Dispose instance of GRPCI2

Limitations

  • The device currently only supports one AHB master. Since most systems only have one (e.g. an AHB2AHB bridge), this limitation should not be a major issue.