GRLIB GRPCI2 Model

The GRPCI2 model is available in the GrPci2 plugin.

Loading the Plugin

import GrPci2

Configuration

@GRPCI2 Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GRPCI2

new

Create new instance of GRPCI2

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GRPCI2 Reference

Properties

Name Type Description

AHB2PCI

uint32_t

AHB to PCI mapping for PCI I/O

AHB2PCIColdResetValue

uint32_t

AHB to PCI mapping for PCI I/O

AHB2PCIForcedBits

uint32_t

AHB to PCI mapping for PCI I/O

AHB2PCIForcedFlippedBits

uint32_t

AHB to PCI mapping for PCI I/O

AHB2PCIReadMask

uint32_t

AHB to PCI mapping for PCI I/O

AHB2PCIResetMask

uint32_t

AHB to PCI mapping for PCI I/O

AHB2PCIResetValue

uint32_t

AHB to PCI mapping for PCI I/O

AHB2PCIWriteMask

uint32_t

AHB to PCI mapping for PCI I/O

AHBM2PCI

[uint32_t; 16]

AHB master to PCI memory address mapping register

BCIM

uint32_t

PCI master prefetch burst limit

BCIMColdResetValue

uint32_t

PCI master prefetch burst limit

BCIMForcedBits

uint32_t

PCI master prefetch burst limit

BCIMForcedFlippedBits

uint32_t

PCI master prefetch burst limit

BCIMReadMask

uint32_t

PCI master prefetch burst limit

BCIMResetMask

uint32_t

PCI master prefetch burst limit

BCIMResetValue

uint32_t

PCI master prefetch burst limit

BCIMWriteMask

uint32_t

PCI master prefetch burst limit

CTRL

uint32_t

Control register

CTRLColdResetValue

uint32_t

Control register

CTRLForcedBits

uint32_t

Control register

CTRLForcedFlippedBits

uint32_t

Control register

CTRLReadMask

uint32_t

Control register

CTRLResetMask

uint32_t

Control register

CTRLResetValue

uint32_t

Control register

CTRLWriteMask

uint32_t

Control register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DMABASE

uint32_t

DMA descriptor base address

DMABASEColdResetValue

uint32_t

DMA descriptor base address

DMABASEForcedBits

uint32_t

DMA descriptor base address

DMABASEForcedFlippedBits

uint32_t

DMA descriptor base address

DMABASEReadMask

uint32_t

DMA descriptor base address

DMABASEResetMask

uint32_t

DMA descriptor base address

DMABASEResetValue

uint32_t

DMA descriptor base address

DMABASEWriteMask

uint32_t

DMA descriptor base address

DMACHAN

uint32_t

DMA channel active

DMACHANColdResetValue

uint32_t

DMA channel active

DMACHANForcedBits

uint32_t

DMA channel active

DMACHANForcedFlippedBits

uint32_t

DMA channel active

DMACHANReadMask

uint32_t

DMA channel active

DMACHANResetMask

uint32_t

DMA channel active

DMACHANResetValue

uint32_t

DMA channel active

DMACHANWriteMask

uint32_t

DMA channel active

DMACTRL

uint32_t

GRPCI2 DMA control and status register

DMACTRLColdResetValue

uint32_t

GRPCI2 DMA control and status register

DMACTRLForcedBits

uint32_t

GRPCI2 DMA control and status register

DMACTRLForcedFlippedBits

uint32_t

GRPCI2 DMA control and status register

DMACTRLReadMask

uint32_t

GRPCI2 DMA control and status register

DMACTRLResetMask

uint32_t

GRPCI2 DMA control and status register

DMACTRLResetValue

uint32_t

GRPCI2 DMA control and status register

DMACTRLWriteMask

uint32_t

GRPCI2 DMA control and status register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

PCI2AHB

[uint32_t; 6]

PCI BAR to AHB address mapping registers

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

STATCAP

uint32_t

Status and Capability register

STATCAPColdResetValue

uint32_t

Status and Capability register

STATCAPForcedBits

uint32_t

Status and Capability register

STATCAPForcedFlippedBits

uint32_t

Status and Capability register

STATCAPReadMask

uint32_t

Status and Capability register

STATCAPResetMask

uint32_t

Status and Capability register

STATCAPResetValue

uint32_t

Status and Capability register

STATCAPWriteMask

uint32_t

Status and Capability register

TimeSource

*void

Time source object

config.Irq

uint8_t

PCI irq number

config.littleEndian

uint8_t

Endianess of memory interface.

ioMem

temu_IfaceRef/ <unknown>

PCI i/o space object

irqCtrl

temu_IfaceRef/ <unknown>

Upward interrupt controller (i.e. on AMBA bus)

pciBus

*void

PCI bus object

pciDevices

temu_IfaceRefArray

PCI devices

pciMem

temu_IfaceRef/ <unknown>

PCI memory space object

processorMem

temu_IfaceRef/ <unknown>

Access to the processor’s memory space

Interfaces

Name Type Description

ApbIface

ApbIface

APB P&P interface

ConfigAccessIface

MemAccessIface

PCI config access interface.

IrqIface

IrqCtrlIface

PCI IRQ interface

MemAccessIface

MemAccessIface

Memory access interface (registers)

PCIBridgeIface

temu::PCIBridgeIface

PCI bridge interface.

PCIMemAccessIface

MemAccessIface

PCI memory access interfaces

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

Registers

Register support is currently experimental!

Register Bank Regs

Register CTRL
Description

Control register

Reset value

0x00000000

Warm reset mask

0xefff0fff

Diagram
Field Mask Reset Description

RE

0x80000000

0x0

PCI reset

MR

0x40000000

0x0

PCI master reset

TR

0x20000000

0x0

PCI target reset

SI

0x08000000

0x0

System error interrupt enable

PE

0x04000000

0x0

Parity error response enable

ER

0x02000000

0x0

Abort error response enable

EI

0x01000000

0x0

Error interrupt enable

BusNumber

0x00ff0000

0x0

Bus number for configuration cycles

DFA

0x00000800

0x0

Disable internal AHB-slave/DMA fair arbitration

IB

0x00000400

0x0

IO burst enable

CB

0x00000200

0x0

Configuration burst enable

DIF

0x00000100

0x0

Device interrupt force

DeviceINTMask

0x000000f0

0x0

Device interrupt mask

HostINTMask

0x0000000f

0x0

Host interrupt mask
Register STATCAP
Description

Status and Capability register

Reset value

0x00000000

Warm reset mask

0xffa00f1f

Diagram
Field Mask Reset Description

Host

0x80000000

0x0

System host indicator

MST

0x40000000

0x0

Master implemented

TAR

0x20000000

0x0

Target implemented

DMA

0x10000000

0x0

DMA implemented

DI

0x08000000

0x0

Device drives PCI INTA

HI

0x04000000

0x0

Device samples PCI INTA..D

IRQmode

0x03000000

0x0

APB IRQ mode

Trace

0x00800000

0x0

PCI trace buffer implemented

FH

0x00200000

0x0

Fake device in system slot

CFGDO

0x00100000

-

PCI configuration access done

CFGER

0x00080000

-

Error during PCI configuration access

CoreInterruptStatus

0x0007f000

-

Core interrupt status

HostInterruptStatus

0x00000f00

0x0

Host interrupt status

FDEPTH

0x0000001c

0x0

FIFO depth

FNUM

0x00000003

0x0

Number of FIFOs
Register BCIM
Description

PCI master prefetch burst limit

Reset value

0x000000ff

Warm reset mask

0xffff00ff

Diagram
Field Mask Reset Description

AHB_master_unmask

0xffff0000

0x0

Limit prefetch burst

burst_length

0x000000ff

0xff

Maximum number of beats per burst
Register AHB2PCI
Description

AHB to PCI mapping for PCI I/O

Reset value

0x00000000

Warm reset mask

0xffff0000

Diagram
Field Mask Reset Description

AHB_to_PCI_IO

0xffff0000

0x0

AHB to PCI IO base address
Register DMACTRL
Description

GRPCI2 DMA control and status register

Reset value

0x80000000

Warm reset mask

0x8000007f

Diagram
Field Mask Reset Description

SAFE

0x80000000

0x1

Arming of control field updates

CHIRQ

0x000ff000

-

Channel IRQ status

MA

0x00000800

-

Master abort

TA

0x00000400

-

Target abort

PE

0x00000200

-

Parity error

AE

0x00000100

-

AHB data error

DE

0x00000080

-

Descriptor error

NumDMAChans

0x00000070

0x0

Number of DMA channels

ACTIVE

0x00000008

0x0

DMA is active

DIS

0x00000004

0x0

DMA disable

IE

0x00000002

0x0

Interrupt enable

EN

0x00000001

0x0

DMA enable
Register DMABASE
Description

DMA descriptor base address

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

DMA descriptor base address
Register DMACHAN
Description

DMA channel active

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

DMA channel active descriptor base address
Register PCI2AHB
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

PCI BAR to AHB address mapping
Register PCI2AHB
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

PCI BAR to AHB address mapping
Register PCI2AHB
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

PCI BAR to AHB address mapping
Register PCI2AHB
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

PCI BAR to AHB address mapping
Register PCI2AHB
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

PCI BAR to AHB address mapping
Register PCI2AHB
Description

PCI BAR to AHB address mapping registers

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

PCI BAR to AHB address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping
Register AHBM2PCI
Description

AHB master to PCI memory address mapping register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ADDR

0xffffffff

0x0

AHB master to PCI memory address mapping

Commands

Name Description

delete

Dispose instance of GRPCI2

Limitations

  • The device currently only supports one AHB master. Since most systems only have one (e.g. an AHB2AHB bridge), this limitation should not be a major issue.