GRLIB GRIOMMU Model

The GRIOMMU model is available in the GrIoMmu plugin.

Loading the Plugin

import GrIoMmu

Configuration

The model should be attached in two directions:

Firstly, IO-devices need to have their memory access interface references routed through the IOMMU. To do this, connect the memory access iface ref in the device to IOMMUAccessIface in the IOMMU.

Secondly, the IOMMU needs to get access to the device’s AMBA PNP info. The info is used to populate the MasterConfig registers. To set the PNP info, attach it to the devicePnp array.

The IOMMUAccessIface and devicePnp array assumes that the same device indexes are used. Not connecting devices the correct way is undefined behaviour.

Connecting the GRIOMMU
// Connect command
connect a=iommu.devicePnp[0] b=device:ApbIface (1)
connect a=device.mem b=iommu:IOMMUAccessIface[0] (2)

// Or with assigmment syntax
iommu.devicePnp[0] = device:ApbIface (1)
device.mem = iommu:IOMMUAccessIface[0] (2)
1 Index should match index on next line.
2 Index should match index on previous line.

@GRIOMMU Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GRIOMMU

new

Create new instance of GRIOMMU

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GRIOMMU Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

abhFailingAccess

uint32_t

AHB failing access register

asmpAccessControl

[uint32_t; 4]

ASMP access control register

capbility

[uint32_t; 3]

Capability register

config.interrupt

uint8_t

Interrupt number

control

uint32_t

Control register

dataRamErrorInjection

uint32_t

Data RAM error injection register

devicePnp

[temu_IfaceRef; 16]/ <unknown>

Devices under IOMMU control

diagnosticCacheAccess

uint32_t

Diagnostic cache access register

diagnosticCacheAccessData

[uint32_t; 8]

Diagnostic cache access data register

diagnosticCacheAccessTag

uint32_t

Diagnostic cache access tag register

groupConfig

[uint32_t; 16]

Group config register

irq

temu_IfaceRef/ <unknown>

ASMP access control register

irqMask

uint32_t

Interrupt mask register

masterConfig

[uint32_t; 16]

Master config register

masterPnp.bar

[uint32_t; 4]

AMBA plug and play base address register

masterPnp.ident

uint32_t

AMBA plug and play config word

masterPnp.user

[uint32_t; 3]

AMBA plug and play user words

mem

temu_IfaceRef/ <unknown>

Main memory bus

secondaryMasterPnp.bar

[uint32_t; 4]

AMBA plug and play base address register

secondaryMasterPnp.ident

uint32_t

AMBA plug and play config word

secondaryMasterPnp.user

[uint32_t; 3]

AMBA plug and play user words

slavePnp.bar

[uint32_t; 4]

AMBA plug and play base address register

slavePnp.ident

uint32_t

AMBA plug and play config word

slavePnp.user

[uint32_t; 3]

AMBA plug and play user words

status

uint32_t

Status register

tagRamErrorInjection

uint32_t

Tag RAM error injection register

tlbCacheFlush

uint32_t

TLB/cache flush register

Interfaces

Name Type Description

DeviceIface

DeviceIface

IOMMUAccessIface

MemAccessIface

IOMMU memory access interfaces

MasterAhbIface

AhbIface

Master AHB interfaces

MemAccessIface

MemAccessIface

ResetIface

ResetIface

SlaveAhbIface

AhbIface

Registers

Register support is currently experimental!

Register Bank default

Register abhFailingAccess
Description

AHB failing access register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register asmpAccessControl
Description

ASMP access control register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register capbility
Description

Capability register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register control
Description

Control register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register dataRamErrorInjection
Description

Data RAM error injection register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register diagnosticCacheAccess
Description

Diagnostic cache access register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register diagnosticCacheAccessData
Description

Diagnostic cache access data register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register diagnosticCacheAccessTag
Description

Diagnostic cache access tag register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register groupConfig
Description

Group config register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register irqMask
Description

Interrupt mask register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register masterConfig
Description

Master config register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register status
Description

Status register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register tagRamErrorInjection
Description

Tag RAM error injection register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register tlbCacheFlush
Description

TLB/cache flush register

Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-

Commands

Name Description

delete

Dispose instance of GRIOMMU

Limitations

  • Read and write combining is not simulated

  • Bus select is ignored, only one memory space is used for memory and processor.

  • APV and TLB caches are not implemented at the moment.

  • Flushes are instantaneous. This means that the FLI and FCI will only result in one actual interrupt being raised.