GRLIB GRIOMMU Model
The GRIOMMU model is available in the GrIoMmu plugin.
Configuration
The model should be attached in two directions:
Firstly, IO-devices need to have their memory access interface references routed through the IOMMU.
To do this, connect the memory access iface ref in the device to IOMMUAccessIface in the IOMMU.
Secondly, the IOMMU needs to get access to the device’s AMBA PNP info.
The info is used to populate the MasterConfig registers.
To set the PNP info, attach it to the devicePnp array.
The IOMMUAccessIface and devicePnp array assumes that the same device indexes are used.
Not connecting devices the correct way is undefined behaviour.
// Connect command
connect a=iommu.devicePnp[0] b=device:ApbIface (1)
connect a=device.mem b=iommu:IOMMUAccessIface[0] (2)
// Or with assigmment syntax
iommu.devicePnp[0] = device:ApbIface (1)
device.mem = iommu:IOMMUAccessIface[0] (2)
| 1 | Index should match index on next line. |
| 2 | Index should match index on previous line. |
@GRIOMMU Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
GRIOMMU Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
abhFailingAccess |
uint32_t |
AHB failing access register |
asmpAccessControl |
[uint32_t; 4] |
ASMP access control register |
capbility |
[uint32_t; 3] |
Capability register |
config.interrupt |
uint8_t |
Interrupt number |
config.littleEndian |
uint8_t |
Endianess of memory interface. |
control |
uint32_t |
Control register |
dataRamErrorInjection |
uint32_t |
Data RAM error injection register |
devicePnp |
[temu_IfaceRef; 16]/ <unknown> |
Devices under IOMMU control |
diagnosticCacheAccess |
uint32_t |
Diagnostic cache access register |
diagnosticCacheAccessData |
[uint32_t; 8] |
Diagnostic cache access data register |
diagnosticCacheAccessTag |
uint32_t |
Diagnostic cache access tag register |
groupConfig |
[uint32_t; 16] |
Group config register |
irq |
temu_IfaceRef/ <unknown> |
ASMP access control register |
irqMask |
uint32_t |
Interrupt mask register |
masterConfig |
[uint32_t; 16] |
Master config register |
masterPnp.bar |
[uint32_t; 4] |
AMBA plug and play base address register |
masterPnp.ident |
uint32_t |
AMBA plug and play config word |
masterPnp.user |
[uint32_t; 3] |
AMBA plug and play user words |
mem |
temu_IfaceRef/ <unknown> |
Main memory bus |
secondaryMasterPnp.bar |
[uint32_t; 4] |
AMBA plug and play base address register |
secondaryMasterPnp.ident |
uint32_t |
AMBA plug and play config word |
secondaryMasterPnp.user |
[uint32_t; 3] |
AMBA plug and play user words |
slavePnp.bar |
[uint32_t; 4] |
AMBA plug and play base address register |
slavePnp.ident |
uint32_t |
AMBA plug and play config word |
slavePnp.user |
[uint32_t; 3] |
AMBA plug and play user words |
status |
uint32_t |
Status register |
tagRamErrorInjection |
uint32_t |
Tag RAM error injection register |
tlbCacheFlush |
uint32_t |
TLB/cache flush register |
Interfaces
| Name | Type | Description |
|---|---|---|
DeviceIface |
DeviceIface |
|
IOMMUAccessIface |
MemAccessIface |
IOMMU memory access interfaces |
MasterAhbIface |
AhbIface |
Master AHB interfaces |
MemAccessIface |
MemAccessIface |
|
RegisterIface |
temu::RegisterIface |
|
ResetIface |
ResetIface |
|
SlaveAhbIface |
AhbIface |
Registers
| Register support is currently experimental! |
Register Bank default
Register LAP0
- Description
-
Capability register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register LAP1
- Description
-
Capability register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register LAP2
- Description
-
Capability register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register CTRL
- Description
-
Control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register FLUSH
- Description
-
TLB/cache flush register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register STAT
- Description
-
Status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register IMASH
- Description
-
Interrupt mask register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register AHBFAS
- Description
-
Failing access registers
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register MSTLFG0
- Description
-
Master configuration register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register GRPCTRC0
- Description
-
Group control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register DIAGCTRL
- Description
-
Diagnostic cache access register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register DIAG0
- Description
-
Diagnostic cache access data register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register DIAGT
- Description
-
Diagnostic cache access tag register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register DERRI
- Description
-
Data RAM error injection register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register TERRI
- Description
-
Tag RAM error injection register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register ASMPCTRL0
- Description
-
ASMP access control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register ASMPCTRL1
- Description
-
ASMP access control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Limitations
-
Read and write combining is not simulated
-
Bus select is ignored, only one memory space is used for memory and processor.
-
APV and TLB caches are not implemented at the moment.
-
Flushes are instantaneous. This means that the FLI and FCI will only result in one actual interrupt being raised.