GRLIB GRSPW1 Model

The GRSPW1 is part of the GRLIB IP library. It is available in libTEMUGrspw1.so.

Loading the Plugin

import Grspw1

Configuration

To work correctly, the device must be connected to an interrupt controller, a memory and another SpaceWire device.

There are several configuration parameters in the GrSpw1 device. They are summarized in the following table:

Name Description

config.infiniteSpeed

With this set, messages are sent immediately instead of being scheduled for the future based on the message length. This is the default option.

config.transmitter.frequency

Specify the SpaceWire transmitter frequency in Hz. Affects transfer speed when infinite speed is disabled.

config.transmitter.dataRate

SpaceWire port datarate: 1=single, 2=double, etc. Affects transfer speed when infinite speed is disabled.

config.interrupt

Influences the interrupt that is raised with the IRQ controller (setting this property also updates the APB PnP info).

config.realCrcCheck

Set to use real crc check instead of packet crc flags. Real crc costs in terms of performance.

@Grspw1 Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @Grspw1

new

Create new instance of Grspw1

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

Grspw1 Reference

Properties

Name Type Description

CLKDIVColdResetValue

uint32_t

Clock divisor register

CLKDIVForcedBits

uint32_t

Clock divisor register

CLKDIVForcedFlippedBits

uint32_t

Clock divisor register

CLKDIVReadMask

uint32_t

Clock divisor register

CLKDIVResetMask

uint32_t

Clock divisor register

CLKDIVResetValue

uint32_t

Clock divisor register

CLKDIVWriteMask

uint32_t

Clock divisor register

CTRLColdResetValue

uint32_t

Control register

CTRLForcedBits

uint32_t

Control register

CTRLForcedFlippedBits

uint32_t

Control register

CTRLReadMask

uint32_t

Control register

CTRLResetMask

uint32_t

Control register

CTRLResetValue

uint32_t

Control register

CTRLWriteMask

uint32_t

Control register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DKEYColdResetValue

uint32_t

Destination key register

DKEYForcedBits

uint32_t

Destination key register

DKEYForcedFlippedBits

uint32_t

Destination key register

DKEYReadMask

uint32_t

Destination key register

DKEYResetMask

uint32_t

Destination key register

DKEYResetValue

uint32_t

Destination key register

DKEYWriteMask

uint32_t

Destination key register

DMACTRLColdResetValue

uint32_t

DMA channel 1 control/status register

DMACTRLForcedBits

uint32_t

DMA channel 1 control/status register

DMACTRLForcedFlippedBits

uint32_t

DMA channel 1 control/status register

DMACTRLReadMask

uint32_t

DMA channel 1 control/status register

DMACTRLResetMask

uint32_t

DMA channel 1 control/status register

DMACTRLResetValue

uint32_t

DMA channel 1 control/status register

DMACTRLWriteMask

uint32_t

DMA channel 1 control/status register

DMAMAXLENColdResetValue

uint32_t

DMA channel 1 RX maximum length register

DMAMAXLENForcedBits

uint32_t

DMA channel 1 RX maximum length register

DMAMAXLENForcedFlippedBits

uint32_t

DMA channel 1 RX maximum length register

DMAMAXLENReadMask

uint32_t

DMA channel 1 RX maximum length register

DMAMAXLENResetMask

uint32_t

DMA channel 1 RX maximum length register

DMAMAXLENResetValue

uint32_t

DMA channel 1 RX maximum length register

DMAMAXLENWriteMask

uint32_t

DMA channel 1 RX maximum length register

DMARXDESCColdResetValue

uint32_t

DMA channel 1 receive descriptor table address register

DMARXDESCForcedBits

uint32_t

DMA channel 1 receive descriptor table address register

DMARXDESCForcedFlippedBits

uint32_t

DMA channel 1 receive descriptor table address register

DMARXDESCReadMask

uint32_t

DMA channel 1 receive descriptor table address register

DMARXDESCResetMask

uint32_t

DMA channel 1 receive descriptor table address register

DMARXDESCResetValue

uint32_t

DMA channel 1 receive descriptor table address register

DMARXDESCWriteMask

uint32_t

DMA channel 1 receive descriptor table address register

DMATXDESCColdResetValue

uint32_t

DMA channel 1 transmit descriptor table address register

DMATXDESCForcedBits

uint32_t

DMA channel 1 transmit descriptor table address register

DMATXDESCForcedFlippedBits

uint32_t

DMA channel 1 transmit descriptor table address register

DMATXDESCReadMask

uint32_t

DMA channel 1 transmit descriptor table address register

DMATXDESCResetMask

uint32_t

DMA channel 1 transmit descriptor table address register

DMATXDESCResetValue

uint32_t

DMA channel 1 transmit descriptor table address register

DMATXDESCWriteMask

uint32_t

DMA channel 1 transmit descriptor table address register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

NODEADDRColdResetValue

uint32_t

Node address register

NODEADDRForcedBits

uint32_t

Node address register

NODEADDRForcedFlippedBits

uint32_t

Node address register

NODEADDRReadMask

uint32_t

Node address register

NODEADDRResetMask

uint32_t

Node address register

NODEADDRResetValue

uint32_t

Node address register

NODEADDRWriteMask

uint32_t

Node address register

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

STSColdResetValue

uint32_t

Status / Interrupt-source register

STSForcedBits

uint32_t

Status / Interrupt-source register

STSForcedFlippedBits

uint32_t

Status / Interrupt-source register

STSReadMask

uint32_t

Status / Interrupt-source register

STSResetMask

uint32_t

Status / Interrupt-source register

STSResetValue

uint32_t

Status / Interrupt-source register

STSWriteMask

uint32_t

Status / Interrupt-source register

TDRColdResetValue

uint32_t

Timer and disconnect register

TDRForcedBits

uint32_t

Timer and disconnect register

TDRForcedFlippedBits

uint32_t

Timer and disconnect register

TDRReadMask

uint32_t

Timer and disconnect register

TDRResetMask

uint32_t

Timer and disconnect register

TDRResetValue

uint32_t

Timer and disconnect register

TDRWriteMask

uint32_t

Timer and disconnect register

TIMEColdResetValue

uint32_t

Time register

TIMEForcedBits

uint32_t

Time register

TIMEForcedFlippedBits

uint32_t

Time register

TIMEReadMask

uint32_t

Time register

TIMEResetMask

uint32_t

Time register

TIMEResetValue

uint32_t

Time register

TIMEWriteMask

uint32_t

Time register

TimeSource

*void

Time source object

config.infiniteSpeed

uint8_t

Set to use infinite speed for transfers.

config.interrupt

uint8_t

The interrupt index

config.realCrcCheck

uint8_t

Set to use real crc check instead of packet crc flags

config.transmitter.dataRate

uint8_t

SpaceWire port datarate: 1=single, 2=double,…​

config.transmitter.frequency

uint32_t

SpaceWire transmitter frequency in Hz

internal.linkState

int32_t

Link state

internal.txDAddr

uint32_t

Data address for the scheduled dma engine transfer

internal.txDLength

uint32_t

Data length for the scheduled dma engine transfer

internal.txFlags

uint32_t

Flags for the scheduled dma engine transfer

internal.txHAddr

uint32_t

Header address for the scheduled dma engine transfer

internal.txType

uint8_t

Scheduled transmission type (dma engine/rmap)

internal.uplinkNsPerByte

uint32_t

Transmitter speed

irqCtrl

temu_IfaceRef/ <unknown>

Irq controller

memAccess

temu_IfaceRef/ <unknown>

Memory used for DMA accesses

pnp.bar

uint32_t

Pnp BAR

pnp.config

uint32_t

Pnp configuration

regs.clockDiv

uint32_t

Clock divisor register

regs.control

uint32_t

Control register

regs.destKey

uint32_t

Destination key register

regs.dmaControl

uint32_t

DMA channel 1 control/status register

regs.dmaRxDescTableAddr

uint32_t

DMA channel 1 receive descriptor table address register

regs.dmaRxMaxLen

uint32_t

DMA channel 1 RX maximum length register

regs.dmaTxDescTableAddr

uint32_t

DMA channel 1 transmit descriptor table address register

regs.nodeAddress

uint32_t

Node address register

regs.statusIrqSrc

uint32_t

Status / Interrupt-source register

regs.time

uint32_t

Time register

regs.timeDisconnect

uint32_t

Timer and disconnect register

spwUplink

[temu_IfaceRef; 2]/ <unknown>

SpaceWire devices connected to the port

Interfaces

Name Type Description

ApbIface

ApbIface

Apb interface

DeviceIface

DeviceIface

Device interface

MemAccessIface

MemAccessIface

Memory Access Interface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

SpwPortIface

SpwPortIface

SpaceWire ports interfaces

Registers

Register support is currently experimental!

Register Bank Regs

Register CTRL
Description

Control register

Reset value

0xe0000000

Warm reset mask

0xe4330f7f

Diagram
Field Mask Reset Description

RA

0x80000000

0x1

RMAP available

RX

0x40000000

0x1

RX unaligned access

RC

0x20000000

0x1

RMAP CRC available

PO

0x04000000

0x0

Number of ports minus one

PS

0x00200000

0x0

Port select

NP

0x00100000

0x0

No port force

RD

0x00020000

0x0

RMAP buffer disable

RE

0x00010000

0x0

RMAP enable

TR

0x00000800

0x0

Time RX enable

TT

0x00000400

0x0

Time TX enable

LI

0x00000200

0x0

Link error IRQ

TQ

0x00000100

0x0

Tick-out IRQ

RS

0x00000040

0x0

Reset

PM

0x00000020

0x0

Promiscuous mode

TI

0x00000010

0x0

Tick in

IE

0x00000008

0x0

Interrupt enable

AS

0x00000004

0x0

Autostart

LS

0x00000002

0x0

Link start

LD

0x00000001

0x0

Link disable
Register STS
Description

Status / Interrupt-source register

Reset value

0x00000000

Warm reset mask

0x00e00200

Diagram
Field Mask Reset Description

LS

0x00e00000

0x0

Link state

AP

0x00000200

0x0

Active port

EE

0x00000100

-

Early EOP/EEP

IA

0x00000080

-

Invalid address

WE

0x00000040

-

Write synchronization error

PE

0x00000010

-

Parity error

DE

0x00000008

-

Disconnect error

ER

0x00000004

-

Escape error

CE

0x00000002

-

Credit error

TO

0x00000001

-

Tick out
Register NODEADDR
Description

Node address register

Reset value

0x000000fe

Warm reset mask

0x000000ff

Diagram
Field Mask Reset Description

NODEADDR

0x000000ff

0xfe

Node address
Register CLKDIV
Description

Clock divisor register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

CLKDIVSTART

0x0000ff00

0x0

Clock divisor startup

CLKDIVRUN

0x000000ff

0x0

Clock divisor run
Register DKEY
Description

Destination key register

Reset value

0x00000000

Warm reset mask

0x000000ff

Diagram
Field Mask Reset Description

DESTKEY

0x000000ff

0x0

Destination key
Register TIME
Description

Time register

Reset value

0x00000000

Warm reset mask

0x000000ff

Diagram
Field Mask Reset Description

TCTRL

0x000000c0

0x0

Time control flags

TIMECNT

0x0000003f

0x0

Time counter
Register TDR
Description

Timer and disconnect register

Reset value

0x00000000

Warm reset mask

0x003fffff

Diagram
Field Mask Reset Description

DISCONNECT

0x003ff000

0x0

Disconnect period

TIMER64

0x00000fff

0x0

6.4 us timer
Register DMACTRL
Description

DMA channel 1 control/status register

Reset value

0x00000000

Warm reset mask

0x00011e1f

Diagram
Field Mask Reset Description

LE

0x00010000

0x0

Link error disable

NS

0x00001000

0x0

No spill

RD

0x00000800

0x0

RX descriptors available

RX

0x00000400

0x0

RX active

AT

0x00000200

0x0

Abort TX

RA

0x00000100

-

RX AHB error

TA

0x00000080

-

TX AHB error

PR

0x00000040

-

Packet received

PS

0x00000020

-

Packet sent

AI

0x00000010

0x0

AHB error interrupt

RI

0x00000008

0x0

Receive interrupt

TI

0x00000004

0x0

Transmit interrupt

RE

0x00000002

0x0

Receiver enable

TE

0x00000001

0x0

Transmitter enable
Register DMAMAXLEN
Description

DMA channel 1 RX maximum length register

Reset value

0x00000000

Warm reset mask

0x01fffffc

Diagram
Field Mask Reset Description

RXMAXLEN

0x01fffffc

0x0

Receiver packet maximum length in bytes
Register DMATXDESC
Description

DMA channel 1 transmit descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff0

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f0

0x0

Descriptor selector
Register DMARXDESC
Description

DMA channel 1 receive descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff8

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f8

0x0

Descriptor selector

Commands

Name Description

delete

Dispose instance of Grspw1

Limitations

The following deviations from real hardware are known to exist with this model:

  • No spill is currently not implemented.

  • Althougth the device already provides two spacewire ports, dual port is not yet implemented. This correspond to a device where the port VHDL parameter is set to 1. Therefore, in the control register, PO = 0 and PS / NP are not available. Let us know if you need this feature implemented.

  • The link interface currently effectively uses only ErrorReset, Ready, Connecting and Run states. These are the only values that will be visible on the status register.

  • RMAPEN signals not available.

Examples

This example show how to create two Grspw1 devices and connect them:

Creating and Connecting GRSPW1 Devices
import BusModels
import TEMUGrspw1
Grspw1.new name=grspw0
Grspw1.new name=grspw1
spw-connect port1=grspw0:SpwPortIface[0] port2=grspw1:SpwPortIface[0]