GRLIB GRGPIO Model

The GRGPIO device is part of the GRLIB device library from Gaisler. The GrGPIO model simulates a 16 pin GPIO device by providing input and output via the SignalIface.

Loading the Plugin

import GrGPIO

Usage

The device can be connected to and from via the signal interface it implements. It implements 16 usable signals (signal 0 through 15). Signal 0 cannot raise interrupts.

You can connect the signal interface as follows:

Connecting via Command Line
# Connect GPIO device signal 0 to device model
connect a=gpio.outSignals[0] b=mydevice:SignalIface

# Connect a device signal interface ref to GPIO device
connect a=mydevice.signal b=gpio:SignalIface[1]
Connecting via API
// Connect GPIO device signal 0 to device model
temu_connect(gpio, "outSignals[0]", mydevice, "SignalIface");

// Connect a device signal interface ref to GPIO device
temu_connect(mydevice, "signal", gpio, "SignalIface[1]");

@GrGPIO Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GrGPIO

new

Create new instance of GrGPIO

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GrGPIO Reference

Properties

Name Type Description

BYPASSColdResetValue

uint32_t

Bypass register

BYPASSForcedBits

uint32_t

Bypass register

BYPASSForcedFlippedBits

uint32_t

Bypass register

BYPASSReadMask

uint32_t

Bypass register

BYPASSResetMask

uint32_t

Bypass register

BYPASSResetValue

uint32_t

Bypass register

BYPASSWriteMask

uint32_t

Bypass register

CAPColdResetValue

uint32_t

Capability register

CAPForcedBits

uint32_t

Capability register

CAPForcedFlippedBits

uint32_t

Capability register

CAPReadMask

uint32_t

Capability register

CAPResetMask

uint32_t

Capability register

CAPResetValue

uint32_t

Capability register

CAPWriteMask

uint32_t

Capability register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DATAColdResetValue

uint32_t

I/O port data register

DATAForcedBits

uint32_t

I/O port data register

DATAForcedFlippedBits

uint32_t

I/O port data register

DATAReadMask

uint32_t

I/O port data register

DATAResetMask

uint32_t

I/O port data register

DATAResetValue

uint32_t

I/O port data register

DATAWriteMask

uint32_t

I/O port data register

DIRECTIONColdResetValue

uint32_t

I/O port direction register

DIRECTIONForcedBits

uint32_t

I/O port direction register

DIRECTIONForcedFlippedBits

uint32_t

I/O port direction register

DIRECTIONReadMask

uint32_t

I/O port direction register

DIRECTIONResetMask

uint32_t

I/O port direction register

DIRECTIONResetValue

uint32_t

I/O port direction register

DIRECTIONWriteMask

uint32_t

I/O port direction register

IAVAILColdResetValue

uint32_t

Interrupt available register

IAVAILForcedBits

uint32_t

Interrupt available register

IAVAILForcedFlippedBits

uint32_t

Interrupt available register

IAVAILReadMask

uint32_t

Interrupt available register

IAVAILResetMask

uint32_t

Interrupt available register

IAVAILResetValue

uint32_t

Interrupt available register

IAVAILWriteMask

uint32_t

Interrupt available register

IEDGEColdResetValue

uint32_t

Interrupt edge register

IEDGEForcedBits

uint32_t

Interrupt edge register

IEDGEForcedFlippedBits

uint32_t

Interrupt edge register

IEDGEReadMask

uint32_t

Interrupt edge register

IEDGEResetMask

uint32_t

Interrupt edge register

IEDGEResetValue

uint32_t

Interrupt edge register

IEDGEWriteMask

uint32_t

Interrupt edge register

IFLAGColdResetValue

uint32_t

Interrupt flag register

IFLAGForcedBits

uint32_t

Interrupt flag register

IFLAGForcedFlippedBits

uint32_t

Interrupt flag register

IFLAGReadMask

uint32_t

Interrupt flag register

IFLAGResetMask

uint32_t

Interrupt flag register

IFLAGResetValue

uint32_t

Interrupt flag register

IFLAGWriteMask

uint32_t

Interrupt flag register

IMASKColdResetValue

uint32_t

Interrupt mask register

IMASKForcedBits

uint32_t

Interrupt mask register

IMASKForcedFlippedBits

uint32_t

Interrupt mask register

IMASKReadMask

uint32_t

Interrupt mask register

IMASKResetMask

uint32_t

Interrupt mask register

IMASKResetValue

uint32_t

Interrupt mask register

IMASKWriteMask

uint32_t

Interrupt mask register

IPENColdResetValue

uint32_t

Input enable register

IPENForcedBits

uint32_t

Input enable register

IPENForcedFlippedBits

uint32_t

Input enable register

IPENReadMask

uint32_t

Input enable register

IPENResetMask

uint32_t

Input enable register

IPENResetValue

uint32_t

Input enable register

IPENWriteMask

uint32_t

Input enable register

IPOLColdResetValue

uint32_t

Interrupt polarity register

IPOLForcedBits

uint32_t

Interrupt polarity register

IPOLForcedFlippedBits

uint32_t

Interrupt polarity register

IPOLReadMask

uint32_t

Interrupt polarity register

IPOLResetMask

uint32_t

Interrupt polarity register

IPOLResetValue

uint32_t

Interrupt polarity register

IPOLWriteMask

uint32_t

Interrupt polarity register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

OUTPUTColdResetValue

uint32_t

I/O port output register

OUTPUTForcedBits

uint32_t

I/O port output register

OUTPUTForcedFlippedBits

uint32_t

I/O port output register

OUTPUTReadMask

uint32_t

I/O port output register

OUTPUTResetMask

uint32_t

I/O port output register

OUTPUTResetValue

uint32_t

I/O port output register

OUTPUTWriteMask

uint32_t

I/O port output register

ObjectID

uint64_t

Unique ObjectID.

PULSEColdResetValue

uint32_t

Pulse register

PULSEForcedBits

uint32_t

Pulse register

PULSEForcedFlippedBits

uint32_t

Pulse register

PULSEReadMask

uint32_t

Pulse register

PULSEResetMask

uint32_t

Pulse register

PULSEResetValue

uint32_t

Pulse register

PULSEWriteMask

uint32_t

Pulse register

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

bypass

uint32_t

Bypass register

capability

uint32_t

Capability register

config.inputEnable

uint8_t

config.irqFlag

uint8_t

config.irqGen

uint8_t

config.irqMask

uint32_t

config.littleEndian

uint8_t

Endianess of memory interface.

config.pinMask

uint32_t

config.pirq

uint8_t

config.pulse

uint8_t

data

uint32_t

I/O port data register

direction

uint32_t

I/O port direction register

edge

uint32_t

Interrupt edge register

inputEnable

uint32_t

Input enable register

irqAvailable

uint32_t

Interrupt available register

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller

irqFlag

uint32_t

Interrupt flag register

irqMap

[uint32_t; 8]

Interrupt map register

mask

uint32_t

Interrupt mask register

outSignals

[temu_IfaceRef; 32]/ <unknown>

GPIO signals

output

uint32_t

I/O port output register

pnp.bar

uint32_t

pnp.config

uint32_t

polarity

uint32_t

Interrupt polarity register

pulse

uint32_t

Pulse register

Interfaces

Name Type Description

ApbIface

ApbIface

DeviceIface

DeviceIface

MemAccessIface

MemAccessIface

PulseIface

SignalIface

Pulse signals

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

SignalIface

SignalIface

Incoming signals

Registers

Register support is currently experimental!

Register Bank Regs

Register DATA
Description

I/O port data register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

DATA

0xffffffff

0x0

I/O port input value
Register OUTPUT
Description

I/O port output register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

DATA

0xffffffff

0x0

I/O port output value
Register DIRECTION
Description

I/O port direction register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

DIR

0xffffffff

0x0

I/O port direction value
Register IMASK
Description

Interrupt mask register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

MASK

0x0000ffff

0x0

Interrupt mask
Register IPOL
Description

Interrupt polarity register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

POL

0x0000ffff

-

Interrupt polarity
Register IEDGE
Description

Interrupt edge register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

EDGE

0x0000ffff

-

Interrupt edge
Register BYPASS
Description

Bypass register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

DATA

0xffffffff

0x0

Bypass alternate function selection
Register CAP
Description

Capability register

Reset value

0x00010400

Warm reset mask

0x00071f1f

Diagram
Field Mask Reset Description

PU

0x00040000

0x0

Pulse register implemented

IER

0x00020000

0x0

Input enable register implemented

IFL

0x00010000

0x1

Interrupt flag register implemented

IRQGEN

0x00001f00

0x4

Interrupt generation setting

NLINES

0x0000001f

0x0

Number of pins in GPIO port minus one
Register IAVAIL
Description

Interrupt available register

Reset value

0x0000ffff

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

IMASK

0xffffffff

0xffff

Interrupt available bit field
Register IFLAG
Description

Interrupt flag register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

IFLAG

0x0000ffff

-

Interrupt flag
Register IPEN
Description

Input enable register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

DATA

0xffffffff

0x0

Input enable value
Register PULSE
Description

Pulse register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

PULSE

0x0000ffff

0x0

Pulse enable
Register IPEN_OR
Description

Input enable register, logical-OR

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DATA

0xffffffff

-

Input enable logical-OR
Register OUTPUT_OR
Description

I/O port output register, logical-OR

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DATA

0xffffffff

-

I/O port output logical-OR
Register DIRECTION_OR
Description

I/O port direction register, logical-OR

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DIR

0xffffffff

-

I/O port direction logical-OR
Register IMASK_OR
Description

Interrupt mask register, logical-OR

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

MASK

0x0000ffff

-

Interrupt mask logical-OR
Register IPEN_AND
Description

Input enable register, logical-AND

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DATA

0xffffffff

-

Input enable logical-AND
Register OUTPUT_AND
Description

I/O port output register, logical-AND

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DATA

0xffffffff

-

I/O port output logical-AND
Register DIRECTION_AND
Description

I/O port direction register, logical-AND

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DIR

0xffffffff

-

I/O port direction logical-AND
Register IMASK_AND
Description

Interrupt mask register, logical-AND

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

MASK

0x0000ffff

-

Interrupt mask logical-AND
Register IPEN_XOR
Description

Input enable register, logical-XOR

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DATA

0xffffffff

-

Input enable logical-XOR
Register OUTPUT_XOR
Description

I/O port output register, logical-XOR

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DATA

0xffffffff

-

I/O port output logical-XOR
Register DIRECTION_XOR
Description

I/O port direction register, logical-XOR

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DIR

0xffffffff

-

I/O port direction logical-XOR
Register IMASK_XOR
Description

Interrupt mask register, logical-XOR

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

MASK

0x0000ffff

-

Interrupt mask logical-XOR
Register IRQMAPR
Description

Interrupt map register

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

IRQMAP3

0x1f000000

0x0

Interrupt map field for GPIO line n+3

IRQMAP2

0x001f0000

0x0

Interrupt map field for GPIO line n+2

IRQMAP1

0x00001f00

0x0

Interrupt map field for GPIO line n+1

IRQMAP0

0x0000001f

0x0

Interrupt map field for GPIO line n
Register IRQMAPR
Description

Interrupt map register

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

IRQMAP3

0x1f000000

0x0

Interrupt map field for GPIO line n+3

IRQMAP2

0x001f0000

0x0

Interrupt map field for GPIO line n+2

IRQMAP1

0x00001f00

0x0

Interrupt map field for GPIO line n+1

IRQMAP0

0x0000001f

0x0

Interrupt map field for GPIO line n
Register IRQMAPR
Description

Interrupt map register

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

IRQMAP3

0x1f000000

0x0

Interrupt map field for GPIO line n+3

IRQMAP2

0x001f0000

0x0

Interrupt map field for GPIO line n+2

IRQMAP1

0x00001f00

0x0

Interrupt map field for GPIO line n+1

IRQMAP0

0x0000001f

0x0

Interrupt map field for GPIO line n
Register IRQMAPR
Description

Interrupt map register

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

IRQMAP3

0x1f000000

0x0

Interrupt map field for GPIO line n+3

IRQMAP2

0x001f0000

0x0

Interrupt map field for GPIO line n+2

IRQMAP1

0x00001f00

0x0

Interrupt map field for GPIO line n+1

IRQMAP0

0x0000001f

0x0

Interrupt map field for GPIO line n
Register IRQMAPR
Description

Interrupt map register

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

IRQMAP3

0x1f000000

0x0

Interrupt map field for GPIO line n+3

IRQMAP2

0x001f0000

0x0

Interrupt map field for GPIO line n+2

IRQMAP1

0x00001f00

0x0

Interrupt map field for GPIO line n+1

IRQMAP0

0x0000001f

0x0

Interrupt map field for GPIO line n
Register IRQMAPR
Description

Interrupt map register

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

IRQMAP3

0x1f000000

0x0

Interrupt map field for GPIO line n+3

IRQMAP2

0x001f0000

0x0

Interrupt map field for GPIO line n+2

IRQMAP1

0x00001f00

0x0

Interrupt map field for GPIO line n+1

IRQMAP0

0x0000001f

0x0

Interrupt map field for GPIO line n
Register IRQMAPR
Description

Interrupt map register

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

IRQMAP3

0x1f000000

0x0

Interrupt map field for GPIO line n+3

IRQMAP2

0x001f0000

0x0

Interrupt map field for GPIO line n+2

IRQMAP1

0x00001f00

0x0

Interrupt map field for GPIO line n+1

IRQMAP0

0x0000001f

0x0

Interrupt map field for GPIO line n
Register IRQMAPR
Description

Interrupt map register

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

IRQMAP3

0x1f000000

0x0

Interrupt map field for GPIO line n+3

IRQMAP2

0x001f0000

0x0

Interrupt map field for GPIO line n+2

IRQMAP1

0x00001f00

0x0

Interrupt map field for GPIO line n+1

IRQMAP0

0x0000001f

0x0

Interrupt map field for GPIO line n

Commands

Name Description

delete

Dispose instance of GrGPIO

Limitations

  • Only the UT700 based configuration is supported at the moment. That means that the bypass and capabilities registers are missing. Further the IRQ map registers are not available.