GRLIB GRGPIO Model

The GRGPIO device is part of the GRLIB device library from Gaisler. The GrGPIO model simulates a 16 pin GPIO device by providing input and output via the SignalIface.

Loading the Plugin

import GrGPIO

Usage

The device can be connected to and from via the signal interface it implements. It implements 16 usable signals (signal 0 through 15). Signal 0 cannot raise interrupts.

You can connect the signal interface as follows:

Connecting via Command Line
# Connect GPIO device signal 0 to device model
connect a=gpio.outSignals[0] b=mydevice:SignalIface

# Connect a device signal interface ref to GPIO device
connect a=mydevice.signal b=gpio:SignalIface[1]
Connecting via API
// Connect GPIO device signal 0 to device model
temu_connect(gpio, "outSignals[0]", mydevice, "SignalIface");

// Connect a device signal interface ref to GPIO device
temu_connect(mydevice, "signal", gpio, "SignalIface[1]");

@GrGPIO Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GrGPIO

new

Create new instance of GrGPIO

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GrGPIO Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

bypass

uint32_t

capability

uint32_t

Capability register

config.inputEnable

uint8_t

config.irqFlag

uint8_t

config.irqGen

uint8_t

config.irqMask

uint32_t

config.pinMask

uint32_t

config.pirq

uint8_t

config.pulse

uint8_t

data

uint32_t

direction

uint32_t

edge

uint32_t

inputEnable

uint32_t

irqAvailable

uint32_t

Interrupt available register

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller

irqFlag

uint32_t

irqMap

[uint32_t; 8]

mask

uint32_t

outSignals

[temu_IfaceRef; 32]/ <unknown>

GPIO signals

output

uint32_t

pnp.bar

uint32_t

pnp.config

uint32_t

polarity

uint32_t

pulse

uint32_t

Interfaces

Name Type Description

ApbIface

ApbIface

DeviceIface

DeviceIface

MemAccessIface

MemAccessIface

PulseIface

SignalIface

Pulse signals

ResetIface

ResetIface

SignalIface

SignalIface

Incoming signals

Registers

Register support is currently experimental!

Register Bank default

Register bypass
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register data
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register direction
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register edge
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register inputEnable
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register irqFlag
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register irqMap
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register mask
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register output
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register polarity
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register pulse
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-

Commands

Name Description

delete

Dispose instance of GrGPIO

Limitations

  • Only the UT700 based configuration is supported at the moment. That means that the bypass and capabilities registers are missing. Further the IRQ map registers are not available.