P2020 DMA Model

This section describes the P2020 DMA model.

The DMA controller transfers blocks of data between the interface and functional modules of this chip, independent of the cores or external hosts. It has four high-speed DMA channels. Both the cores and external devices can initiate DMA transfers.

The DMA module has two modes of operation: basic and extended. Basic mode is the DMA legacy mode, which does not support advanced features. Extended mode supports advanced features such as striding and flexible descriptor structures. These two basic modes allow users to initiate and end DMA transfers in various ways:

  • Direct mode: no descriptors are involved, software/user must initialize such required fields as source address and attributes and destination address and attributes.

  • Chaining mode: software must initialize descriptors in memory and such fields as link/list descriptor address before starting a transfer.

  • Single-write start mode: DMA process can be started using a single-write command to either the descriptor address register in one of the chaining modes or the source/destination address registers in one of the direct modes.

Loading the Plugin

import P2020

Configuration

The DMA programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. All 4 DMA channels have the same set of registers, so the register index is the channels id (from 0 to 3).

Setting registers via Command Line
# set source address for channel 3
dma.SAR[3] = 0x40000000
Setting registers via API
// set source address for channel 3
temu_writeValueU32(dma, "SAR", 0x40000000, 3);

@DMA Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @DMA

new

Create new instance of DMA

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

DMA Reference

Properties

Name Type Description

BCR

[uint32_t; 4]

DMA byte count register

CLNDAR

[uint32_t; 4]

DMA current link descriptor address register

CLSDAR

[uint32_t; 4]

DMA current list descriptor address register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DAR

[uint32_t; 4]

DMA destination address register

DATR

[uint32_t; 4]

DMA destination attributes register

DGSR

uint32_t

DMA general status register

DGSRColdResetValue

uint32_t

DMA general status register

DGSRForcedBits

uint32_t

DMA general status register

DGSRForcedFlippedBits

uint32_t

DMA general status register

DGSRReadMask

uint32_t

DMA general status register

DGSRResetMask

uint32_t

DMA general status register

DGSRResetValue

uint32_t

DMA general status register

DGSRWriteMask

uint32_t

DMA general status register

DSR

[uint32_t; 4]

DMA destination stride register

ECLNDAR

[uint32_t; 4]

DMA current link descriptor extended address register

ECLSDAR

[uint32_t; 4]

DMA extended current list descriptor address register

ENLNDAR

[uint32_t; 4]

DMA extended next link descriptor address register

ENLSDAR

[uint32_t; 4]

DMA extended next list descriptor address register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

MR

[uint32_t; 4]

DMA channel mode register

NLNDAR

[uint32_t; 4]

DMA next link descriptor address register

NLSDAR

[uint32_t; 4]

DMA next list descriptor address register

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

SAR

[uint32_t; 4]

DMA source address register

SATR

[uint32_t; 4]

DMA source attributes register

SR

[uint32_t; 4]

DMA channel status register

SSR

[uint32_t; 4]

DMA source stride register

TimeSource

*void

Time source object

config.interrupt

[uint8_t; 4]

DMA IRQ number for each channel

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller

memAccess

temu_IfaceRef/ <unknown>

Memory access for DMA.

Interfaces

Name Type Description

DeviceIface

DeviceIface

Device Interface

MemAccessIface

MemAccessIface

Memory access interface.

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Reset Interface

Commands

Name Description

delete

Dispose instance of DMA

Limitations

None