GRLIB L2CACHE Model
The GrlibL2Cache device is part of the GRLIB IP library.
It is available in libTEMUGrlibL2Cache.so.
@GrlibL2Cache Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
GrlibL2Cache Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
accessControl |
uint32_t |
L2C access control register |
config.littleEndian |
uint8_t |
Endianess of memory interface. |
control |
uint32_t |
L2C Control Register |
dataCheckBits |
uint32_t |
L2C data check bits register |
errorAddress |
uint32_t |
L2C error address register |
errorHandlingAndInjectionConfig |
uint32_t |
L2C injection configuration register |
errorInjection |
uint32_t |
L2C error injection register |
errorStatusCtrl |
uint32_t |
L2C error status/control register |
flushMem |
uint32_t |
L2C Flush memory address register |
flushSet |
uint32_t |
L2C Flush set address register |
mtrr |
[uint32_t; 32] |
L2C memory type range registers |
pnp.bar |
uint32_t |
|
scrubControlStatus |
uint32_t |
L2C scrub control/status register |
scrubDelay |
uint32_t |
L2C scrub delay register |
status |
uint32_t |
L2C Status Register |
tagCheckBits |
uint32_t |
L2C tag check bits register |
Interfaces
| Name | Type | Description |
|---|---|---|
AhbIface |
AhbIface |
|
DeviceIface |
DeviceIface |
|
MemAccessIface |
MemAccessIface |
|
RegisterIface |
temu::RegisterIface |
|
ResetIface |
ResetIface |
Registers
| Register support is currently experimental! |
Register Bank default
Register L2CC
- Description
-
L2C Control Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CS
- Description
-
L2C Status Register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CFMA
- Description
-
L2C flush (memory address) register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CFSI
- Description
-
L2C Flush (Set, Index) register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CACC
- Description
-
Access counter register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CHIT
- Description
-
Hit counter register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CFSCCNT
- Description
-
Front-side bus cycle counter register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CFSUCNT
- Description
-
Front-side bus usage counter register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CERR
- Description
-
Error status / control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CERRA
- Description
-
Error address register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CTCB
- Description
-
TAG-check bits (or TAG-bit) register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CCB
- Description
-
Data-check bits (or data-bits) register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CSCRUB
- Description
-
Scrub control/status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CSDEL
- Description
-
Scrub delay register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CSDEL
- Description
-
Scrub delay register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register L2CEINJ
- Description
-
Error injection register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |