P2020 eSPI Model

This section describes the P2020 Enhanced Serial Peripheral Interface (eSPI) model.

The eSPI is a full-duplex, synchronous, character-oriented channel that supports a simple interface (receive, transmit and chip selects).

eSPI model contains names which include master/slave terminology. The TEMU project does not use such terms normally, however given that the hardware specification, this header deals with, use these terms they are reused here for consistency.

Loading the Plugin

import P2020

Configuration

Master device does not have a direct access to slave devices(and vice versa). Transmission and reception process is done through bus, the bus route on chip select signals.

The eSPI bus model can be configured by connecting SPI slave device interface to the spiSlaveDevices array, and master device to the spiMasterDevice.

Connecting via Command Line
# Connect eSPI device to eSPI bus via SpiSlaveDeviceIface
connect a=spiBus.spiSlaveDevices b=spidev:SpiSlaveDeviceIface
# Connect master interface from eSPI model to the bus
connect a=spiBus.spiMasterDevice b=espi:MasterDeviceIface
# Connect bus to the eSPI model
connect a=espi.spiBus b=spiBus:SpiBusIface
# Connect bus and the eSPI device
connect a=spidev.spiBus, spiBus:SpiBusIface
Connecting via API
// Connect eSPI device to eSPI bus via SpiSlaveDeviceIface
temu_connect(spiBus, "spiSlaveDevices", spidev, "SpiSlaveDeviceIface");
// Connect master interface from eSPI model to the bus
temu_connect(spiBus, "spiMasterDevice", espi, "MasterDeviceIface");
// Connect bus to the eSPI model
temu_connect(espi, "spiBus", spiBus, "SpiBusIface");
// Connect bus and the eSPI device
temu_connect(spidev, "spiBus", spiBus, "SpiBusIface");

The eSPI programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. All the registers are 4-byte wide:

Setting registers via Command Line
# Configure SPMODE register to enable normal operation
espi.SPMODE = 0x8000100F;
Setting registers via API
// Configure SPMODE register to enable normal operation
temu_writeValueU32(espi, "SPMODE", 0x8000100F, 0);

@eSPI Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @eSPI

new

Create new instance of eSPI

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

eSPI Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

SPCOM

uint32_t

eSPI command register

SPCOMColdResetValue

uint32_t

eSPI command register

SPCOMForcedBits

uint32_t

eSPI command register

SPCOMForcedFlippedBits

uint32_t

eSPI command register

SPCOMReadMask

uint32_t

eSPI command register

SPCOMResetMask

uint32_t

eSPI command register

SPCOMResetValue

uint32_t

eSPI command register

SPCOMWriteMask

uint32_t

eSPI command register

SPIE

uint32_t

eSPI event register

SPIEColdResetValue

uint32_t

eSPI event register

SPIEForcedBits

uint32_t

eSPI event register

SPIEForcedFlippedBits

uint32_t

eSPI event register

SPIEReadMask

uint32_t

eSPI event register

SPIEResetMask

uint32_t

eSPI event register

SPIEResetValue

uint32_t

eSPI event register

SPIEWriteMask

uint32_t

eSPI event register

SPIM

uint32_t

eSPI mask register

SPIMColdResetValue

uint32_t

eSPI mask register

SPIMForcedBits

uint32_t

eSPI mask register

SPIMForcedFlippedBits

uint32_t

eSPI mask register

SPIMReadMask

uint32_t

eSPI mask register

SPIMResetMask

uint32_t

eSPI mask register

SPIMResetValue

uint32_t

eSPI mask register

SPIMWriteMask

uint32_t

eSPI mask register

SPIRF

uint32_t

eSPI receive FIFO access register

SPIRFColdResetValue

uint32_t

eSPI receive FIFO access register

SPIRFForcedBits

uint32_t

eSPI receive FIFO access register

SPIRFForcedFlippedBits

uint32_t

eSPI receive FIFO access register

SPIRFReadMask

uint32_t

eSPI receive FIFO access register

SPIRFResetMask

uint32_t

eSPI receive FIFO access register

SPIRFResetValue

uint32_t

eSPI receive FIFO access register

SPIRFWriteMask

uint32_t

eSPI receive FIFO access register

SPITF

uint32_t

eSPI transmit FIFO access register

SPITFColdResetValue

uint32_t

eSPI transmit FIFO access register

SPITFForcedBits

uint32_t

eSPI transmit FIFO access register

SPITFForcedFlippedBits

uint32_t

eSPI transmit FIFO access register

SPITFReadMask

uint32_t

eSPI transmit FIFO access register

SPITFResetMask

uint32_t

eSPI transmit FIFO access register

SPITFResetValue

uint32_t

eSPI transmit FIFO access register

SPITFWriteMask

uint32_t

eSPI transmit FIFO access register

SPMODE

uint32_t

eSPI mode register

SPMODE0

uint32_t

eSPI CS0 mode register

SPMODE0ColdResetValue

uint32_t

eSPI CS0 mode register

SPMODE0ForcedBits

uint32_t

eSPI CS0 mode register

SPMODE0ForcedFlippedBits

uint32_t

eSPI CS0 mode register

SPMODE0ReadMask

uint32_t

eSPI CS0 mode register

SPMODE0ResetMask

uint32_t

eSPI CS0 mode register

SPMODE0ResetValue

uint32_t

eSPI CS0 mode register

SPMODE0WriteMask

uint32_t

eSPI CS0 mode register

SPMODE1

uint32_t

eSPI CS1 mode register

SPMODE1ColdResetValue

uint32_t

eSPI CS1 mode register

SPMODE1ForcedBits

uint32_t

eSPI CS1 mode register

SPMODE1ForcedFlippedBits

uint32_t

eSPI CS1 mode register

SPMODE1ReadMask

uint32_t

eSPI CS1 mode register

SPMODE1ResetMask

uint32_t

eSPI CS1 mode register

SPMODE1ResetValue

uint32_t

eSPI CS1 mode register

SPMODE1WriteMask

uint32_t

eSPI CS1 mode register

SPMODE2

uint32_t

eSPI CS2 mode register

SPMODE2ColdResetValue

uint32_t

eSPI CS2 mode register

SPMODE2ForcedBits

uint32_t

eSPI CS2 mode register

SPMODE2ForcedFlippedBits

uint32_t

eSPI CS2 mode register

SPMODE2ReadMask

uint32_t

eSPI CS2 mode register

SPMODE2ResetMask

uint32_t

eSPI CS2 mode register

SPMODE2ResetValue

uint32_t

eSPI CS2 mode register

SPMODE2WriteMask

uint32_t

eSPI CS2 mode register

SPMODE3

uint32_t

eSPI CS3 mode register

SPMODE3ColdResetValue

uint32_t

eSPI CS3 mode register

SPMODE3ForcedBits

uint32_t

eSPI CS3 mode register

SPMODE3ForcedFlippedBits

uint32_t

eSPI CS3 mode register

SPMODE3ReadMask

uint32_t

eSPI CS3 mode register

SPMODE3ResetMask

uint32_t

eSPI CS3 mode register

SPMODE3ResetValue

uint32_t

eSPI CS3 mode register

SPMODE3WriteMask

uint32_t

eSPI CS3 mode register

SPMODEColdResetValue

uint32_t

eSPI mode register

SPMODEForcedBits

uint32_t

eSPI mode register

SPMODEForcedFlippedBits

uint32_t

eSPI mode register

SPMODEReadMask

uint32_t

eSPI mode register

SPMODEResetMask

uint32_t

eSPI mode register

SPMODEResetValue

uint32_t

eSPI mode register

SPMODEWriteMask

uint32_t

eSPI mode register

TimeSource

*void

Time source object

chipType

uint8_t

Chip type

config.interrupt

uint8_t

eSPI IRQ number

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller

rxFifo.data

[uint8_t; 32]

RX FIFO data

rxFifo.size

uint8_t

RX size

rxFifo.start

uint8_t

RX start index

rxFifo.usage

uint8_t

RX usage

spiBus

temu_IfaceRef/ <unknown>

Spi bus

txFifo.data

[uint8_t; 32]

TX FIFO data

txFifo.size

uint8_t

TX size

txFifo.start

uint8_t

TX start index

txFifo.usage

uint8_t

TX usage

Interfaces

Name Type Description

DeviceIface

DeviceIface

Device Interface

MasterDeviceIface

temu::SpiMasterDeviceIface

Communication interface.

MemAccessIface

MemAccessIface

Memory access interface.

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Reset Interface

Registers

Register support is currently experimental!

Register Bank Regs

Register SPMODE
Description

eSPI mode register

Reset value

0x0000100f

Warm reset mask

0xc0003f1f

Diagram
Field Mask Reset Description

EN

0x80000000

0x0

Enable eSPI

LOOP

0x40000000

0x0

Loop mode

TXTHR

0x00003f00

0x10

Tx FIFO threshold

RXTHR

0x0000001f

0xf

Rx FIFO threshold
Register SPIE
Description

eSPI event register

Reset value

0x00200000

Warm reset mask

0x3f3f0300

Diagram
Field Mask Reset Description

RXCNT

0x3f000000

0x0

Current number of full Rx FIFO bytes

TXCNT

0x003f0000

0x20

Current number of free Tx FIFO bytes

TXE

0x00008000

-

Tx FIFO is empty

DON

0x00004000

-

Last character was transmitted

RXT

0x00002000

-

Rx FIFO has more than RXTHR bytes

RXF

0x00001000

-

Rx FIFO is full

TXT

0x00000800

-

Tx FIFO has less than TXTHR bytes

RNE

0x00000200

0x0

Rx FIFO is not empty

TNF

0x00000100

0x0

Tx FIFO is not full
Register SPIM
Description

eSPI mask register

Reset value

0x00000000

Warm reset mask

0x0000fb00

Diagram
Field Mask Reset Description

TXE

0x00008000

0x0

Tx FIFO empty interrupt mask

DON

0x00004000

0x0

Last character transmitted mask

RXT

0x00002000

0x0

Rx threshold interrupt mask

RXF

0x00001000

0x0

Rx FIFO full interrupt mask

TXT

0x00000800

0x0

Tx threshold interrupt mask

RNE

0x00000200

0x0

Rx not empty interrupt mask

TNF

0x00000100

0x0

Tx not full interrupt mask
Register SPCOM
Description

eSPI command register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

CS

0xc0000000

-

Chip select for which transaction is destined

RxDelay

0x20000000

-

Rx data sampling delay

DO

0x10000000

-

Winbond dual output read

TO

0x08000000

-

Transmit only

HLD

0x04000000

-

Mask first generated SPI_CLK

RxSKIP

0x00ff0000

-

Number of characters skipped for reception from frame start

TRANLEN

0x0000ffff

-

Transaction length, number of characters in the frame minus one
Register SPITF
Description

eSPI transmit FIFO access register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

DATA

0xffffffff

-

Transmit FIFO data
Register SPIRF
Description

eSPI receive FIFO access register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

DATA

0xffffffff

0x0

Receive FIFO data
Register SPMODE0
Description

eSPI CS0 mode register

Reset value

0x00100000

Warm reset mask

0xff9ffff8

Diagram
Field Mask Reset Description

CI0

0x80000000

0x0

Clock invert

CP0

0x40000000

0x0

Clock phase

REV0

0x20000000

0x0

Reverse data mode

DIV160

0x10000000

0x0

Divide by 16

PM0

0x0f000000

0x0

Prescale modulus select

ODD0

0x00800000

0x0

Odd division

POL0

0x00100000

0x1

Chip select polarity

LEN0

0x000f0000

0x0

Character length in bits per character

CS0BEF

0x0000f000

0x0

CS assertion time in bits before frame start

CS0AFT

0x00000f00

0x0

CS assertion time in bits after frame end

CS0CG

0x000000f8

0x0

Clock gap
Register SPMODE1
Description

eSPI CS1 mode register

Reset value

0x00100000

Warm reset mask

0xff9ffff8

Diagram
Field Mask Reset Description

CI1

0x80000000

0x0

Clock invert

CP1

0x40000000

0x0

Clock phase

REV1

0x20000000

0x0

Reverse data mode

DIV161

0x10000000

0x0

Divide by 16

PM1

0x0f000000

0x0

Prescale modulus select

ODD1

0x00800000

0x0

Odd division

POL1

0x00100000

0x1

Chip select polarity

LEN1

0x000f0000

0x0

Character length in bits per character

CS1BEF

0x0000f000

0x0

CS assertion time in bits before frame start

CS1AFT

0x00000f00

0x0

CS assertion time in bits after frame end

CS1CG

0x000000f8

0x0

Clock gap
Register SPMODE2
Description

eSPI CS2 mode register

Reset value

0x00100000

Warm reset mask

0xff9ffff8

Diagram
Field Mask Reset Description

CI2

0x80000000

0x0

Clock invert

CP2

0x40000000

0x0

Clock phase

REV2

0x20000000

0x0

Reverse data mode

DIV162

0x10000000

0x0

Divide by 16

PM2

0x0f000000

0x0

Prescale modulus select

ODD2

0x00800000

0x0

Odd division

POL2

0x00100000

0x1

Chip select polarity

LEN2

0x000f0000

0x0

Character length in bits per character

CS2BEF

0x0000f000

0x0

CS assertion time in bits before frame start

CS2AFT

0x00000f00

0x0

CS assertion time in bits after frame end

CS2CG

0x000000f8

0x0

Clock gap
Register SPMODE3
Description

eSPI CS3 mode register

Reset value

0x00100000

Warm reset mask

0xff9ffff8

Diagram
Field Mask Reset Description

CI3

0x80000000

0x0

Clock invert

CP3

0x40000000

0x0

Clock phase

REV3

0x20000000

0x0

Reverse data mode

DIV163

0x10000000

0x0

Divide by 16

PM3

0x0f000000

0x0

Prescale modulus select

ODD3

0x00800000

0x0

Odd division

POL3

0x00100000

0x1

Chip select polarity

LEN3

0x000f0000

0x0

Character length in bits per character

CS3BEF

0x0000f000

0x0

CS assertion time in bits before frame start

CS3AFT

0x00000f00

0x0

CS assertion time in bits after frame end

CS3CG

0x000000f8

0x0

Clock gap

Commands

Name Description

delete

Dispose instance of eSPI

Limitations

  • eSPI doesn’t generate the transfer clock SPI_CLK signal and doesn’t implement the eSPI baud rate generator (BRG).