P2020 eSPI Model

This section describes the P2020 Enhanced Serial Peripheral Interface (eSPI) model.

The eSPI is a full-duplex, synchronous, character-oriented channel that supports a simple interface (receive, transmit and chip selects).

eSPI model contains names which include master/slave terminology. The TEMU project does not use such terms normally, however given that the hardware specification, this header deals with, use these terms they are reused here for consistency.

Loading the Plugin

import P2020

Configuration

Master device does not have a direct access to slave devices(and vice versa). Transmission and reception process is done through bus, the bus route on chip select signals.

The eSPI bus model can be configured by connecting it to a temu_SpiBus2 bus model.

Connecting via Command Line
# Connect bus to the eSPI model
connect a=espi.spiBus b=spiBus:SpiBus2Iface
Connecting via API
// Connect SPI bus SpiBus2Iface to eSPI
temu_connect(espi, "spiBus", spiBus, "SpiBus2Iface")

The eSPI programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. All the registers are 4-byte wide:

Setting registers via Command Line
# Configure SPMODE register to enable normal operation
espi.SPMODE = 0x8000100F;
Setting registers via API
// Configure SPMODE register to enable normal operation
temu_writeValueU32(espi, "SPMODE", 0x8000100F, 0);

@eSPI Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @eSPI

new

Create new instance of eSPI

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

eSPI Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

SPCOM

uint32_t

eSPI command register

SPCOMColdResetValue

uint32_t

eSPI command register

SPCOMForcedBits

uint32_t

eSPI command register

SPCOMForcedFlippedBits

uint32_t

eSPI command register

SPCOMReadMask

uint32_t

eSPI command register

SPCOMResetMask

uint32_t

eSPI command register

SPCOMResetValue

uint32_t

eSPI command register

SPCOMWriteMask

uint32_t

eSPI command register

SPIE

uint32_t

eSPI event register

SPIEColdResetValue

uint32_t

eSPI event register

SPIEForcedBits

uint32_t

eSPI event register

SPIEForcedFlippedBits

uint32_t

eSPI event register

SPIEReadMask

uint32_t

eSPI event register

SPIEResetMask

uint32_t

eSPI event register

SPIEResetValue

uint32_t

eSPI event register

SPIEWriteMask

uint32_t

eSPI event register

SPIM

uint32_t

eSPI mask register

SPIMColdResetValue

uint32_t

eSPI mask register

SPIMForcedBits

uint32_t

eSPI mask register

SPIMForcedFlippedBits

uint32_t

eSPI mask register

SPIMReadMask

uint32_t

eSPI mask register

SPIMResetMask

uint32_t

eSPI mask register

SPIMResetValue

uint32_t

eSPI mask register

SPIMWriteMask

uint32_t

eSPI mask register

SPIRF

uint32_t

eSPI receive FIFO access register

SPIRFColdResetValue

uint32_t

eSPI receive FIFO access register

SPIRFForcedBits

uint32_t

eSPI receive FIFO access register

SPIRFForcedFlippedBits

uint32_t

eSPI receive FIFO access register

SPIRFReadMask

uint32_t

eSPI receive FIFO access register

SPIRFResetMask

uint32_t

eSPI receive FIFO access register

SPIRFResetValue

uint32_t

eSPI receive FIFO access register

SPIRFWriteMask

uint32_t

eSPI receive FIFO access register

SPITF

uint32_t

eSPI transmit FIFO access register

SPITFColdResetValue

uint32_t

eSPI transmit FIFO access register

SPITFForcedBits

uint32_t

eSPI transmit FIFO access register

SPITFForcedFlippedBits

uint32_t

eSPI transmit FIFO access register

SPITFReadMask

uint32_t

eSPI transmit FIFO access register

SPITFResetMask

uint32_t

eSPI transmit FIFO access register

SPITFResetValue

uint32_t

eSPI transmit FIFO access register

SPITFWriteMask

uint32_t

eSPI transmit FIFO access register

SPMODE

uint32_t

eSPI mode register

SPMODE0

uint32_t

eSPI CS0 mode register

SPMODE0ColdResetValue

uint32_t

eSPI CS0 mode register

SPMODE0ForcedBits

uint32_t

eSPI CS0 mode register

SPMODE0ForcedFlippedBits

uint32_t

eSPI CS0 mode register

SPMODE0ReadMask

uint32_t

eSPI CS0 mode register

SPMODE0ResetMask

uint32_t

eSPI CS0 mode register

SPMODE0ResetValue

uint32_t

eSPI CS0 mode register

SPMODE0WriteMask

uint32_t

eSPI CS0 mode register

SPMODE1

uint32_t

eSPI CS1 mode register

SPMODE1ColdResetValue

uint32_t

eSPI CS1 mode register

SPMODE1ForcedBits

uint32_t

eSPI CS1 mode register

SPMODE1ForcedFlippedBits

uint32_t

eSPI CS1 mode register

SPMODE1ReadMask

uint32_t

eSPI CS1 mode register

SPMODE1ResetMask

uint32_t

eSPI CS1 mode register

SPMODE1ResetValue

uint32_t

eSPI CS1 mode register

SPMODE1WriteMask

uint32_t

eSPI CS1 mode register

SPMODE2

uint32_t

eSPI CS2 mode register

SPMODE2ColdResetValue

uint32_t

eSPI CS2 mode register

SPMODE2ForcedBits

uint32_t

eSPI CS2 mode register

SPMODE2ForcedFlippedBits

uint32_t

eSPI CS2 mode register

SPMODE2ReadMask

uint32_t

eSPI CS2 mode register

SPMODE2ResetMask

uint32_t

eSPI CS2 mode register

SPMODE2ResetValue

uint32_t

eSPI CS2 mode register

SPMODE2WriteMask

uint32_t

eSPI CS2 mode register

SPMODE3

uint32_t

eSPI CS3 mode register

SPMODE3ColdResetValue

uint32_t

eSPI CS3 mode register

SPMODE3ForcedBits

uint32_t

eSPI CS3 mode register

SPMODE3ForcedFlippedBits

uint32_t

eSPI CS3 mode register

SPMODE3ReadMask

uint32_t

eSPI CS3 mode register

SPMODE3ResetMask

uint32_t

eSPI CS3 mode register

SPMODE3ResetValue

uint32_t

eSPI CS3 mode register

SPMODE3WriteMask

uint32_t

eSPI CS3 mode register

SPMODEColdResetValue

uint32_t

eSPI mode register

SPMODEForcedBits

uint32_t

eSPI mode register

SPMODEForcedFlippedBits

uint32_t

eSPI mode register

SPMODEReadMask

uint32_t

eSPI mode register

SPMODEResetMask

uint32_t

eSPI mode register

SPMODEResetValue

uint32_t

eSPI mode register

SPMODEWriteMask

uint32_t

eSPI mode register

TimeSource

*void

Time source object

charsSent

uint32_t

chipType

uint8_t

Chip type

config.interrupt

uint8_t

eSPI IRQ number

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller

isActive

uint8_t

isDone

uint8_t

rxFifo.data

[uint8_t; 32]

RX FIFO data

rxFifo.size

uint8_t

RX size

rxFifo.start

uint8_t

RX start index

rxFifo.usage

uint8_t

RX usage

spiBus

temu_IfaceRef/ <unknown>

Spi bus

state.isActive

uint8_t

SPI transaction in progress

txFifo.data

[uint8_t; 32]

TX FIFO data

txFifo.size

uint8_t

TX size

txFifo.start

uint8_t

TX start index

txFifo.usage

uint8_t

TX usage

Interfaces

Name Type Description

DeviceIface

DeviceIface

Device Interface

MemAccessIface

MemAccessIface

Memory access interface.

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Reset Interface

Commands

Name Description

delete

Dispose instance of eSPI

Limitations

  • eSPI doesn’t generate the transfer clock SPI_CLK signal and doesn’t implement the eSPI baud rate generator (BRG).