P2020 DDR Model

This section describes the DDR controller model.

The model supports the handling of SEU and MEU events (i.e. correctable and uncorrectable ECC errors). Such events will update the counters and raise interrupts accordingly.

Loading the Plugin

import P2020

Configuration

To use SEU and MEU events connect the memoryspace upset/faulty handlers to the DDR model and allow interrupts as follows:

Connecting SEU and MEU events via Command Line
# Connect the memoryspace upset/faulty handlers to the ddr
connect a=mem.upsetHandlers b=ddr:CorrectableErrorIface
connect a=mem.faultyHandlers b=ddr:UncorrectableErrorIface

# Enable ECC error interrupts
ddr.ERR_INT_EN = 0x0000000c

# Set/clear faulty attribute on the given memory range
memory-set-faulty addr=0x08 obj=mem
memory-clear-faulty addr=0x08 obj=mem

# Set/clear upset attribute on the given memory range
memory-set-upset addr=0x08 obj=mem
memory-clear-upset addr=0x08 obj=mem
Connecting SEU and MEU events via API
// Connect the memoryspace upset/faulty handlers to the ddr
temu_connect(mem, "upsetHandlers", ddr, "CorrectableErrorIface");
temu_connect(mem, "faultyHandlers", ddr, "UncorrectableErrorIface");

// Enable ECC error interrupts
temu_writeValueU32(ddr, "ERR_INT_EN", 0x0000000c, 0);

// Set/clear faulty attribute on the given memory range
temu_memorySetAttr(mem, 0x08, 4, teMA_Faulty);
temu_memoryClearAttr(mem, 0x08, 4, teMA_Faulty);

// Set/clear upset attribute on the given memory range
temu_memorySetAttr(mem, 0x08, 4, teMA_Upset);
temu_memoryClearAttr(mem, 0x08, 4, teMA_Upset);

@DDR Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @DDR

new

Create new instance of DDR

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

DDR Reference

Properties

Name Type Description

CAPTURE_ADDRESS

uint32_t

Memory error address capture

CAPTURE_ADDRESSColdResetValue

uint32_t

Memory error address capture

CAPTURE_ADDRESSForcedBits

uint32_t

Memory error address capture

CAPTURE_ADDRESSForcedFlippedBits

uint32_t

Memory error address capture

CAPTURE_ADDRESSReadMask

uint32_t

Memory error address capture

CAPTURE_ADDRESSResetMask

uint32_t

Memory error address capture

CAPTURE_ADDRESSResetValue

uint32_t

Memory error address capture

CAPTURE_ADDRESSWriteMask

uint32_t

Memory error address capture

CAPTURE_ATTRIBUTES

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESColdResetValue

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESForcedBits

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESForcedFlippedBits

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESReadMask

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESResetMask

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESResetValue

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESWriteMask

uint32_t

Memory error attributes capture

CAPTURE_DATA_HI

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIColdResetValue

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIForcedBits

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIForcedFlippedBits

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIReadMask

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIResetMask

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIResetValue

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIWriteMask

uint32_t

Memory data path read capture high

CAPTURE_DATA_LO

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOColdResetValue

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOForcedBits

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOForcedFlippedBits

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOReadMask

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOResetMask

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOResetValue

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOWriteMask

uint32_t

Memory data path read capture low

CAPTURE_ECC

uint32_t

Memory data path read capture ECC

CAPTURE_ECCColdResetValue

uint32_t

Memory data path read capture ECC

CAPTURE_ECCForcedBits

uint32_t

Memory data path read capture ECC

CAPTURE_ECCForcedFlippedBits

uint32_t

Memory data path read capture ECC

CAPTURE_ECCReadMask

uint32_t

Memory data path read capture ECC

CAPTURE_ECCResetMask

uint32_t

Memory data path read capture ECC

CAPTURE_ECCResetValue

uint32_t

Memory data path read capture ECC

CAPTURE_ECCWriteMask

uint32_t

Memory data path read capture ECC

CAPTURE_EXT_ADDRESS

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSColdResetValue

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSForcedBits

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSForcedFlippedBits

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSReadMask

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSResetMask

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSResetValue

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSWriteMask

uint32_t

Memory error extended address capture

CS_BNDS

[uint32_t; 4]

Chip select memory bounds register

CS_CONFIG

[uint32_t; 4]

Chip select configuration register

CS_CONFIG_2

[uint32_t; 4]

Chip select configuration 2 register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DATA_ERR_INJECT_HI

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIColdResetValue

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIForcedBits

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIForcedFlippedBits

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIReadMask

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIResetMask

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIResetValue

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIWriteMask

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_LO

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOColdResetValue

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOForcedBits

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOForcedFlippedBits

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOReadMask

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOResetMask

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOResetValue

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOWriteMask

uint32_t

Memory data path error injection mask low

DATA_INIT

uint32_t

DDR SDRAM data initialization

DATA_INITColdResetValue

uint32_t

DDR SDRAM data initialization

DATA_INITForcedBits

uint32_t

DDR SDRAM data initialization

DATA_INITForcedFlippedBits

uint32_t

DDR SDRAM data initialization

DATA_INITReadMask

uint32_t

DDR SDRAM data initialization

DATA_INITResetMask

uint32_t

DDR SDRAM data initialization

DATA_INITResetValue

uint32_t

DDR SDRAM data initialization

DATA_INITWriteMask

uint32_t

DDR SDRAM data initialization

DDRCDR_1

uint32_t

DDR control driver register 1

DDRCDR_1ColdResetValue

uint32_t

DDR control driver register 1

DDRCDR_1ForcedBits

uint32_t

DDR control driver register 1

DDRCDR_1ForcedFlippedBits

uint32_t

DDR control driver register 1

DDRCDR_1ReadMask

uint32_t

DDR control driver register 1

DDRCDR_1ResetMask

uint32_t

DDR control driver register 1

DDRCDR_1ResetValue

uint32_t

DDR control driver register 1

DDRCDR_1WriteMask

uint32_t

DDR control driver register 1

DDRCDR_2

uint32_t

DDR control driver register 2

DDRCDR_2ColdResetValue

uint32_t

DDR control driver register 2

DDRCDR_2ForcedBits

uint32_t

DDR control driver register 2

DDRCDR_2ForcedFlippedBits

uint32_t

DDR control driver register 2

DDRCDR_2ReadMask

uint32_t

DDR control driver register 2

DDRCDR_2ResetMask

uint32_t

DDR control driver register 2

DDRCDR_2ResetValue

uint32_t

DDR control driver register 2

DDRCDR_2WriteMask

uint32_t

DDR control driver register 2

DDRDSR_1

uint32_t

DDR debug status register 1

DDRDSR_1ColdResetValue

uint32_t

DDR debug status register 1

DDRDSR_1ForcedBits

uint32_t

DDR debug status register 1

DDRDSR_1ForcedFlippedBits

uint32_t

DDR debug status register 1

DDRDSR_1ReadMask

uint32_t

DDR debug status register 1

DDRDSR_1ResetMask

uint32_t

DDR debug status register 1

DDRDSR_1ResetValue

uint32_t

DDR debug status register 1

DDRDSR_1WriteMask

uint32_t

DDR debug status register 1

DDRDSR_2

uint32_t

DDR debug status register 2

DDRDSR_2ColdResetValue

uint32_t

DDR debug status register 2

DDRDSR_2ForcedBits

uint32_t

DDR debug status register 2

DDRDSR_2ForcedFlippedBits

uint32_t

DDR debug status register 2

DDRDSR_2ReadMask

uint32_t

DDR debug status register 2

DDRDSR_2ResetMask

uint32_t

DDR debug status register 2

DDRDSR_2ResetValue

uint32_t

DDR debug status register 2

DDRDSR_2WriteMask

uint32_t

DDR debug status register 2

ERR_DETECT

uint32_t

Memory error detect

ERR_DETECTColdResetValue

uint32_t

Memory error detect

ERR_DETECTForcedBits

uint32_t

Memory error detect

ERR_DETECTForcedFlippedBits

uint32_t

Memory error detect

ERR_DETECTReadMask

uint32_t

Memory error detect

ERR_DETECTResetMask

uint32_t

Memory error detect

ERR_DETECTResetValue

uint32_t

Memory error detect

ERR_DETECTWriteMask

uint32_t

Memory error detect

ERR_DISABLE

uint32_t

Memory error disable

ERR_DISABLEColdResetValue

uint32_t

Memory error disable

ERR_DISABLEForcedBits

uint32_t

Memory error disable

ERR_DISABLEForcedFlippedBits

uint32_t

Memory error disable

ERR_DISABLEReadMask

uint32_t

Memory error disable

ERR_DISABLEResetMask

uint32_t

Memory error disable

ERR_DISABLEResetValue

uint32_t

Memory error disable

ERR_DISABLEWriteMask

uint32_t

Memory error disable

ERR_INJECT

uint32_t

Memory data path error injection mask ECC

ERR_INJECTColdResetValue

uint32_t

Memory data path error injection mask ECC

ERR_INJECTForcedBits

uint32_t

Memory data path error injection mask ECC

ERR_INJECTForcedFlippedBits

uint32_t

Memory data path error injection mask ECC

ERR_INJECTReadMask

uint32_t

Memory data path error injection mask ECC

ERR_INJECTResetMask

uint32_t

Memory data path error injection mask ECC

ERR_INJECTResetValue

uint32_t

Memory data path error injection mask ECC

ERR_INJECTWriteMask

uint32_t

Memory data path error injection mask ECC

ERR_INT_EN

uint32_t

Memory error interrupt enable

ERR_INT_ENColdResetValue

uint32_t

Memory error interrupt enable

ERR_INT_ENForcedBits

uint32_t

Memory error interrupt enable

ERR_INT_ENForcedFlippedBits

uint32_t

Memory error interrupt enable

ERR_INT_ENReadMask

uint32_t

Memory error interrupt enable

ERR_INT_ENResetMask

uint32_t

Memory error interrupt enable

ERR_INT_ENResetValue

uint32_t

Memory error interrupt enable

ERR_INT_ENWriteMask

uint32_t

Memory error interrupt enable

ERR_SBE

uint32_t

Single-bit ECC memory error management

ERR_SBEColdResetValue

uint32_t

Single-bit ECC memory error management

ERR_SBEForcedBits

uint32_t

Single-bit ECC memory error management

ERR_SBEForcedFlippedBits

uint32_t

Single-bit ECC memory error management

ERR_SBEReadMask

uint32_t

Single-bit ECC memory error management

ERR_SBEResetMask

uint32_t

Single-bit ECC memory error management

ERR_SBEResetValue

uint32_t

Single-bit ECC memory error management

ERR_SBEWriteMask

uint32_t

Single-bit ECC memory error management

INIT_ADDR

uint32_t

DDR training initialization address

INIT_ADDRColdResetValue

uint32_t

DDR training initialization address

INIT_ADDRForcedBits

uint32_t

DDR training initialization address

INIT_ADDRForcedFlippedBits

uint32_t

DDR training initialization address

INIT_ADDRReadMask

uint32_t

DDR training initialization address

INIT_ADDRResetMask

uint32_t

DDR training initialization address

INIT_ADDRResetValue

uint32_t

DDR training initialization address

INIT_ADDRWriteMask

uint32_t

DDR training initialization address

INIT_EXT_ADDR

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRColdResetValue

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRForcedBits

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRForcedFlippedBits

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRReadMask

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRResetMask

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRResetValue

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRWriteMask

uint32_t

DDR training initialization extended address

IP_REV1

uint32_t

DDR IP block revision 1

IP_REV1ColdResetValue

uint32_t

DDR IP block revision 1

IP_REV1ForcedBits

uint32_t

DDR IP block revision 1

IP_REV1ForcedFlippedBits

uint32_t

DDR IP block revision 1

IP_REV1ReadMask

uint32_t

DDR IP block revision 1

IP_REV1ResetMask

uint32_t

DDR IP block revision 1

IP_REV1ResetValue

uint32_t

DDR IP block revision 1

IP_REV1WriteMask

uint32_t

DDR IP block revision 1

IP_REV2

uint32_t

DDR IP block revision 2

IP_REV2ColdResetValue

uint32_t

DDR IP block revision 2

IP_REV2ForcedBits

uint32_t

DDR IP block revision 2

IP_REV2ForcedFlippedBits

uint32_t

DDR IP block revision 2

IP_REV2ReadMask

uint32_t

DDR IP block revision 2

IP_REV2ResetMask

uint32_t

DDR IP block revision 2

IP_REV2ResetValue

uint32_t

DDR IP block revision 2

IP_REV2WriteMask

uint32_t

DDR IP block revision 2

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

SDRAM_CFG

uint32_t

DDR SDRAM control configuration

SDRAM_CFGColdResetValue

uint32_t

DDR SDRAM control configuration

SDRAM_CFGForcedBits

uint32_t

DDR SDRAM control configuration

SDRAM_CFGForcedFlippedBits

uint32_t

DDR SDRAM control configuration

SDRAM_CFGReadMask

uint32_t

DDR SDRAM control configuration

SDRAM_CFGResetMask

uint32_t

DDR SDRAM control configuration

SDRAM_CFGResetValue

uint32_t

DDR SDRAM control configuration

SDRAM_CFGWriteMask

uint32_t

DDR SDRAM control configuration

SDRAM_CFG_2

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ColdResetValue

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ForcedBits

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ForcedFlippedBits

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ReadMask

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ResetMask

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ResetValue

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2WriteMask

uint32_t

DDR SDRAM control configuration 2

SDRAM_CLK_CNTL

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLColdResetValue

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLForcedBits

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLForcedFlippedBits

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLReadMask

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLResetMask

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLResetValue

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLWriteMask

uint32_t

DDR SDRAM clock control

SDRAM_INTERVAL

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALColdResetValue

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALForcedBits

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALForcedFlippedBits

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALReadMask

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALResetMask

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALResetValue

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALWriteMask

uint32_t

DDR SDRAM interval configuration

SDRAM_MD_CNTL

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLColdResetValue

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLForcedBits

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLForcedFlippedBits

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLReadMask

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLResetMask

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLResetValue

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLWriteMask

uint32_t

DDR SDRAM mode control

SDRAM_MODE

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEColdResetValue

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEForcedBits

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEForcedFlippedBits

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEReadMask

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEResetMask

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEResetValue

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEWriteMask

uint32_t

DDR SDRAM mode configuration

SDRAM_MODE_2

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ColdResetValue

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ForcedBits

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ForcedFlippedBits

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ReadMask

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ResetMask

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ResetValue

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2WriteMask

uint32_t

DDR SDRAM mode configuration 2

SDRAM_RCW_1

uint32_t

DDR register control words 1

SDRAM_RCW_1ColdResetValue

uint32_t

DDR register control words 1

SDRAM_RCW_1ForcedBits

uint32_t

DDR register control words 1

SDRAM_RCW_1ForcedFlippedBits

uint32_t

DDR register control words 1

SDRAM_RCW_1ReadMask

uint32_t

DDR register control words 1

SDRAM_RCW_1ResetMask

uint32_t

DDR register control words 1

SDRAM_RCW_1ResetValue

uint32_t

DDR register control words 1

SDRAM_RCW_1WriteMask

uint32_t

DDR register control words 1

SDRAM_RCW_2

uint32_t

DDR register control words 2

SDRAM_RCW_2ColdResetValue

uint32_t

DDR register control words 2

SDRAM_RCW_2ForcedBits

uint32_t

DDR register control words 2

SDRAM_RCW_2ForcedFlippedBits

uint32_t

DDR register control words 2

SDRAM_RCW_2ReadMask

uint32_t

DDR register control words 2

SDRAM_RCW_2ResetMask

uint32_t

DDR register control words 2

SDRAM_RCW_2ResetValue

uint32_t

DDR register control words 2

SDRAM_RCW_2WriteMask

uint32_t

DDR register control words 2

SR_CNTR

uint32_t

DDR self refresh counter

SR_CNTRColdResetValue

uint32_t

DDR self refresh counter

SR_CNTRForcedBits

uint32_t

DDR self refresh counter

SR_CNTRForcedFlippedBits

uint32_t

DDR self refresh counter

SR_CNTRReadMask

uint32_t

DDR self refresh counter

SR_CNTRResetMask

uint32_t

DDR self refresh counter

SR_CNTRResetValue

uint32_t

DDR self refresh counter

SR_CNTRWriteMask

uint32_t

DDR self refresh counter

TIMING_CFG_0

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ColdResetValue

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ForcedBits

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ReadMask

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ResetMask

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ResetValue

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0WriteMask

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_1

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ColdResetValue

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ForcedBits

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ReadMask

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ResetMask

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ResetValue

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1WriteMask

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_2

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ColdResetValue

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ForcedBits

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ReadMask

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ResetMask

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ResetValue

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2WriteMask

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_3

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ColdResetValue

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ForcedBits

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ReadMask

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ResetMask

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ResetValue

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3WriteMask

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_4

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ColdResetValue

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ForcedBits

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ReadMask

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ResetMask

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ResetValue

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4WriteMask

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_5

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ColdResetValue

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ForcedBits

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ReadMask

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ResetMask

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ResetValue

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5WriteMask

uint32_t

DDR SDRAM timing configuration 5

TimeSource

*void

Time source object

WRLVL_CNTL

uint32_t

DDR write leveling control

WRLVL_CNTLColdResetValue

uint32_t

DDR write leveling control

WRLVL_CNTLForcedBits

uint32_t

DDR write leveling control

WRLVL_CNTLForcedFlippedBits

uint32_t

DDR write leveling control

WRLVL_CNTLReadMask

uint32_t

DDR write leveling control

WRLVL_CNTLResetMask

uint32_t

DDR write leveling control

WRLVL_CNTLResetValue

uint32_t

DDR write leveling control

WRLVL_CNTLWriteMask

uint32_t

DDR write leveling control

WRLVL_CNTL_2

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ColdResetValue

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ForcedBits

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ForcedFlippedBits

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ReadMask

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ResetMask

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ResetValue

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2WriteMask

uint32_t

DDR write leveling control 2

WRLVL_CNTL_3

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ColdResetValue

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ForcedBits

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ForcedFlippedBits

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ReadMask

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ResetMask

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ResetValue

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3WriteMask

uint32_t

DDR write leveling control 3

ZQ_CNTL

uint32_t

DDR ZQ calibration control

ZQ_CNTLColdResetValue

uint32_t

DDR ZQ calibration control

ZQ_CNTLForcedBits

uint32_t

DDR ZQ calibration control

ZQ_CNTLForcedFlippedBits

uint32_t

DDR ZQ calibration control

ZQ_CNTLReadMask

uint32_t

DDR ZQ calibration control

ZQ_CNTLResetMask

uint32_t

DDR ZQ calibration control

ZQ_CNTLResetValue

uint32_t

DDR ZQ calibration control

ZQ_CNTLWriteMask

uint32_t

DDR ZQ calibration control

config.IRQ

uint8_t

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller

memorySpace

temu_IfaceRef/ <unknown>

Memory space.

Interfaces

Name Type Description

CorrectableErrorIface

MemAccessIface

DeviceIface

DeviceIface

MemAccessIface

MemAccessIface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

UncorrectableErrorIface

MemAccessIface

Registers

Register support is currently experimental!

Register Bank Regs

Register TIMING_CFG_3
Description

DDR SDRAM timing configuration 3

Reset value

0x00000000

Warm reset mask

0x010f1007

Diagram
Field Mask Reset Description

EXT_ACTTOPRE

0x01000000

0x0

Extended activate to precharge interval

EXT_REFREC

0x000f0000

0x0

Extended refresh recovery time

EXT_CASLAT

0x00001000

0x0

Extended CAS latency

CNTL_ADJ

0x00000007

0x0

Control signal launch adjustment
Register TIMING_CFG_0
Description

DDR SDRAM timing configuration 0

Reset value

0x00110105

Warm reset mask

0xff7f0f0f

Diagram
Field Mask Reset Description

RWT

0xc0000000

0x0

Read-to-write turnaround

WRT

0x30000000

0x0

Write-to-read turnaround

RRT

0x0c000000

0x0

Read-to-read turnaround

WWT

0x03000000

0x0

Write-to-write turnaround

ACT_PD_EXIT

0x00700000

0x1

Active powerdown exit timing

PRE_PD_EXIT

0x000f0000

0x1

Precharge powerdown exit timing

ODT_PD_EXIT

0x00000f00

0x1

ODT powerdown exit timing

MRS_CYC

0x0000000f

0x5

Mode register set cycle time
Register TIMING_CFG_1
Description

DDR SDRAM timing configuration 1

Reset value

0x00000000

Warm reset mask

0xffffff77

Diagram
Field Mask Reset Description

PRETOACT

0xf0000000

0x0

Precharge-to-activate interval

ACTTOPRE

0x0f000000

0x0

Activate-to-precharge interval

ACTTORW

0x00f00000

0x0

Activate-to-read/write interval

CASLAT

0x000f0000

0x0

CAS latency

REFREC

0x0000f000

0x0

Refresh recovery time

WRREC

0x00000f00

0x0

Last data to precharge minimum interval

ACTTOACT

0x00000070

0x0

Activate-to-activate interval

WRTORD

0x00000007

0x0

Last write data pair to read command issue interval
Register TIMING_CFG_2
Description

DDR SDRAM timing configuration 2

Reset value

0x00000000

Warm reset mask

0xfff8fdff

Diagram
Field Mask Reset Description

ADD_LAT

0xf0000000

0x0

Additive latency

CPO

0x0f800000

0x0

MCAS-to-preamble override

WR_LAT

0x00780000

0x0

Write latency

RD_TO_PRE

0x0000e000

0x0

Read to precharge

WR_DATA_DELAY

0x00001c00

0x0

Write command to write data strobe timing adjustment

CKE_PLS

0x000001c0

0x0

Minimum CKE pulse width

FOUR_ACT

0x0000003f

0x0

Four activates window
Register SDRAM_CFG
Description

DDR SDRAM control configuration

Reset value

0x03000000

Warm reset mask

0xf73dff3b

Diagram
Field Mask Reset Description

MEM_EN

0x80000000

0x0

DDR SDRAM interface logic enable

SREN

0x40000000

0x0

Self refresh enable during sleep

ECC_EN

0x20000000

0x0

ECC enable

RD_EN

0x10000000

0x0

Registered DIMM enable

SDRAM_TYPE

0x07000000

0x3

Type of SDRAM device

DYN_PWR

0x00200000

0x0

Dynamic power management mode

DBW

0x00180000

0x0

DRAM data bus width

8_BE

0x00040000

0x0

8-beat burst enable

3T_EN

0x00010000

0x0

Enable 3T timing

2T_EN

0x00008000

0x0

Enable 2T timing

BA_INTLV_CTL

0x00007f00

0x0

Bank interleaving control

x32_EN

0x00000020

0x0

x32 enable

PCHB8

0x00000010

0x0

Precharge bit 8 enable

HSE

0x00000008

0x0

Global half-strength override

MEM_HALT

0x00000002

0x0

DDR memory controller halt

BI

0x00000001

0x0

Bypass initialization
Register SDRAM_CFG_2
Description

DDR SDRAM control configuration 2

Reset value

0x00000000

Warm reset mask

0xec60f075

Diagram
Field Mask Reset Description

FRC_SR

0x80000000

0x0

Force self-refresh

SR_IE

0x40000000

0x0

Self-refresh interrupt enable

DLL_RST_DIS

0x20000000

0x0

DLL reset disable

DQS_CFG

0x0c000000

0x0

DQS configuration

ODT_CFG

0x00600000

0x0

ODT configuration

NUM_PR

0x0000f000

0x0

Number of posted refreshes

OBC_CFG

0x00000040

0x0

On-the-fly burst chop configuration

AP_EN

0x00000020

0x0

Address parity enable

D_INIT

0x00000010

0x0

DRAM data initialization

RCW_EN

0x00000004

0x0

Register control word enable

MD_EN

0x00000001

0x0

Mirrored DIMM enable
Register SDRAM_MODE
Description

DDR SDRAM mode configuration

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ESDMODE

0xffff0000

0x0

Extended SDRAM mode

SDMODE

0x0000ffff

0x0

SDRAM mode
Register SDRAM_MODE_2
Description

DDR SDRAM mode configuration 2

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

ESDMODE2

0xffff0000

0x0

Extended SDRAM mode 2

ESDMODE3

0x0000ffff

0x0

Extended SDRAM mode 3
Register SDRAM_MD_CNTL
Description

DDR SDRAM mode control

Reset value

0x00000000

Warm reset mask

0xb7f0ffff

Diagram
Field Mask Reset Description

MD_EN

0x80000000

0x0

Mode enable

CS_SEL

0x30000000

0x0

Select chip select

MD_SEL

0x07000000

0x0

Mode register select

SET_REF

0x00800000

0x0

Set refresh

SET_PRE

0x00400000

0x0

Set precharge

CKE_CNTL

0x00300000

0x0

Clock enable control

MD_VALUE

0x0000ffff

0x0

Mode register value
Register SDRAM_INTERVAL
Description

DDR SDRAM interval configuration

Reset value

0x00000000

Warm reset mask

0xffff3fff

Diagram
Field Mask Reset Description

REFINT

0xffff0000

0x0

Refresh interval

BSTOPRE

0x00003fff

0x0

Precharge interval
Register DATA_INIT
Description

DDR SDRAM data initialization

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

INIT_VALUE

0xffffffff

0x0

Initialization value
Register SDRAM_CLK_CNTL
Description

DDR SDRAM clock control

Reset value

0x01000000

Warm reset mask

0x07800000

Diagram
Field Mask Reset Description

CLK_ADJUST

0x07800000

0x2

Clock adjust
Register INIT_ADDR
Description

DDR training initialization address

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

INIT_ADDR

0xffffffff

0x0

Training initialization address
Register INIT_EXT_ADDR
Description

DDR training initialization extended address

Reset value

0x00000000

Warm reset mask

0x8000000f

Diagram
Field Mask Reset Description

UIA

0x80000000

0x0

Use initialization address

INIT_EXT_ADDR

0x0000000f

0x0

Training initialization extended address
Register TIMING_CFG_4
Description

DDR SDRAM timing configuration 4

Reset value

0x00000000

Warm reset mask

0xffff0003

Diagram
Field Mask Reset Description

RWT

0xf0000000

0x0

Read-to-write turnaround for same chip select

WRT

0x0f000000

0x0

Write-to-read turnaround for same chip select

RRT

0x00f00000

0x0

Read-to-read turnaround for same chip select

WWT

0x000f0000

0x0

Write-to-write turnaround for same chip select

DLL_LOCK

0x00000003

0x0

DDR SDRAM DLL lock time
Register TIMING_CFG_5
Description

DDR SDRAM timing configuration 5

Reset value

0x00000000

Warm reset mask

0x1f71f700

Diagram
Field Mask Reset Description

RODT_ON

0x1f000000

0x0

Read to ODT on

RODT_OFF

0x00700000

0x0

Read to ODT off

WODT_ON

0x0001f000

0x0

Write to ODT on

WODT_OFF

0x00000700

0x0

Write to ODT off
Register ZQ_CNTL
Description

DDR ZQ calibration control

Reset value

0x00000000

Warm reset mask

0x8f0f0f00

Diagram
Field Mask Reset Description

ZQ_EN

0x80000000

0x0

ZQ calibration enable

ZQINIT

0x0f000000

0x0

POR ZQ calibration time

ZQOPER

0x000f0000

0x0

Normal operation full calibration time

ZQCS

0x00000f00

0x0

Normal operation short calibration time
Register WRLVL_CNTL
Description

DDR write leveling control

Reset value

0x00000000

Warm reset mask

0x8777f70f

Diagram
Field Mask Reset Description

WRLVL_EN

0x80000000

0x0

Write leveling enable

WRLVL_MRD

0x07000000

0x0

First DQS pulse rising edge delay

WRLVL_ODTEN

0x00700000

0x0

ODT delay after margining mode is programmed

WRLVL_DQSEN

0x00070000

0x0

DQS delay after margining mode is programmed

WRLVL_SMPL

0x0000f000

0x0

Write leveling sample time

WRLVL_WLR

0x00000700

0x0

Write leveling repetition time

WRLVL_START

0x0000000f

0x0

Write leveling start time
Register SR_CNTR
Description

DDR self refresh counter

Reset value

0x00000000

Warm reset mask

0x000f0000

Diagram
Field Mask Reset Description

SR_IT

0x000f0000

0x0

Self refresh idle threshold
Register SDRAM_RCW_1
Description

DDR register control words 1

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

RCW0

0xf0000000

0x0

Register control word 0

RCW1

0x0f000000

0x0

Register control word 1

RCW2

0x00f00000

0x0

Register control word 2

RCW3

0x000f0000

0x0

Register control word 3

RCW4

0x0000f000

0x0

Register control word 4

RCW5

0x00000f00

0x0

Register control word 5

RCW6

0x000000f0

0x0

Register control word 6

RCW7

0x0000000f

0x0

Register control word 7
Register SDRAM_RCW_2
Description

DDR register control words 2

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

RCW8

0xf0000000

0x0

Register control word 8

RCW9

0x0f000000

0x0

Register control word 9

RCW10

0x00f00000

0x0

Register control word 10

RCW11

0x000f0000

0x0

Register control word 11

RCW12

0x0000f000

0x0

Register control word 12

RCW13

0x00000f00

0x0

Register control word 13

RCW14

0x000000f0

0x0

Register control word 14

RCW15

0x0000000f

0x0

Register control word 15
Register WRLVL_CNTL_2
Description

DDR write leveling control 2

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

WRLVL_START_1

0x1f000000

0x0

Write leveling start time for DQS1

WRLVL_START_2

0x001f0000

0x0

Write leveling start time for DQS2

WRLVL_START_3

0x00001f00

0x0

Write leveling start time for DQS3

WRLVL_START_4

0x0000001f

0x0

Write leveling start time for DQS4
Register WRLVL_CNTL_3
Description

DDR write leveling control 3

Reset value

0x00000000

Warm reset mask

0x1f1f1f1f

Diagram
Field Mask Reset Description

WRLVL_START_5

0x1f000000

0x0

Write leveling start time for DQS5

WRLVL_START_6

0x001f0000

0x0

Write leveling start time for DQS6

WRLVL_START_7

0x00001f00

0x0

Write leveling start time for DQS7

WRLVL_START_8

0x0000001f

0x0

Write leveling start time for DQS8
Register DDRDSR_1
Description

DDR debug status register 1

Reset value

0x00000000

Warm reset mask

0xffc0ffff

Diagram
Field Mask Reset Description

DDRDC

0xc0000000

0x0

DDR driver compensation input value

MDICPZ

0x3c000000

0x0

Current setting of PFET driver MDIC impedance

MDICNZ

0x03c00000

0x0

Current setting of NFET driver MDIC impedance

CPZ

0x0000f000

0x0

Current setting of PFET command impedance

CNZ

0x00000f00

0x0

Current setting of NFET command impedance

DPZ

0x000000f0

0x0

Current setting of PFET data impedance

DNZ

0x0000000f

0x0

Current setting of NFET data impedance
Register DDRDSR_2
Description

DDR debug status register 2

Reset value

0x00000000

Warm reset mask

0xff000000

Diagram
Field Mask Reset Description

CLKPZ

0xf0000000

0x0

Current setting of PFET clock impedance

CLKNZ

0x0f000000

0x0

Current setting of NFET clock impedance
Register DDRCDR_1
Description

DDR control driver register 1

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

DHC_EN

0x80000000

0x0

DDR driver hardware compensation enable

DSO_MDIC_EN

0x40000000

0x0

Driver software override enable for MDIC

DSO_MDICPZ

0x3c000000

0x0

DDR driver software MDIC p-impedance override

DSO_MDICNZ

0x03c00000

0x0

DDR driver software MDIC n-impedance override

DSO_MDIC_PZ_OE

0x00200000

0x0

Driver software override p-impedance output enable

DSO_MDIC_NZ_OE

0x00100000

0x0

Driver software override n-impedance output enable

ODT

0x000c0000

0x0

ODT termination value for IOs

DSO_C_EN

0x00020000

0x0

Driver software override enable for address/command

DSO_D_EN

0x00010000

0x0

Driver software override enable for data

DSO_CPZ

0x0000f000

0x0

DDR driver software command p-impedance override

DSO_CNZ

0x00000f00

0x0

DDR driver software command n-impedance override

DSO_DPZ

0x000000f0

0x0

DDR driver software data p-impedance override

DSO_DNZ

0x0000000f

0x0

DDR driver software data n-impedance override
Register DDRCDR_2
Description

DDR control driver register 2

Reset value

0x00000000

Warm reset mask

0x8ff00001

Diagram
Field Mask Reset Description

DSO_CLK_EN

0x80000000

0x0

Driver software override enable for clocks

DSO_CLKPZ

0x0f000000

0x0

Driver software clocks p-impedance override

DSO_CLKNZ

0x00f00000

0x0

Driver software clocks n-impedance override

ODT

0x00000001

0x0

ODT termination value for IOs
Register IP_REV1
Description

DDR IP block revision 1

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

IP_ID

0xffff0000

-

IP block ID

IP_MJ

0x0000ff00

-

Major revision

IP_MN

0x000000ff

-

Minor revision
Register IP_REV2
Description

DDR IP block revision 2

Reset value

0x00000003

Warm reset mask

0x00ff00ff

Diagram
Field Mask Reset Description

IP_INT

0x00ff0000

0x0

IP block integration options

IP_CFG

0x000000ff

0x3

IP block configuration options
Register DATA_ERR_INJECT_HI
Description

Memory data path error injection mask high

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

EIMH

0xffffffff

0x0

Error injection mask high data path
Register DATA_ERR_INJECT_LO
Description

Memory data path error injection mask low

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

EIML

0xffffffff

0x0

Error injection mask low data path
Register ERR_INJECT
Description

Memory data path error injection mask ECC

Reset value

0x00000000

Warm reset mask

0xff000001

Diagram
Field Mask Reset Description

EEIM

0xff000000

0x0

Error injection mask ECC

EIEN

0x00000001

0x0

Error injection enable
Register CAPTURE_DATA_HI
Description

Memory data path read capture high

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

CDH

0xffffffff

0x0

Captured high data path
Register CAPTURE_DATA_LO
Description

Memory data path read capture low

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

CDL

0xffffffff

0x0

Captured low data path
Register CAPTURE_ECC
Description

Memory data path read capture ECC

Reset value

0x00000000

Warm reset mask

0xff000000

Diagram
Field Mask Reset Description

CE

0xff000000

0x0

Captured ECC
Register ERR_DETECT
Description

Memory error detect

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

MME

0x80000000

-

Multiple memory errors

APE

0x00000100

-

Address parity error

ACE

0x00000080

-

Automatic calibration error

MBE

0x00000008

-

Multiple-bit ECC error

SBE

0x00000004

-

Single-bit ECC error

MSE

0x00000001

-

Memory select error
Register ERR_DISABLE
Description

Memory error disable

Reset value

0x00000000

Warm reset mask

0x0000018d

Diagram
Field Mask Reset Description

APED

0x00000100

0x0

Address parity error disable

ACED

0x00000080

0x0

Automatic calibration error disable

MBED

0x00000008

0x0

Multiple-bit ECC error disable

SBED

0x00000004

0x0

Single-bit ECC error disable

MSED

0x00000001

0x0

Memory select error disable
Register ERR_INT_EN
Description

Memory error interrupt enable

Reset value

0x00000000

Warm reset mask

0x0000018d

Diagram
Field Mask Reset Description

APEE

0x00000100

0x0

Address parity error interrupt enable

ACEE

0x00000080

0x0

Automatic calibration error interrupt enable

MBEE

0x00000008

0x0

Multiple-bit ECC error interrupt enable

SBEE

0x00000004

0x0

Single-bit ECC error interrupt enable

MSEE

0x00000001

0x0

Memory select error interrupt enable
Register CAPTURE_ATTRIBUTES
Description

Memory error attributes capture

Reset value

0x00000000

Warm reset mask

0x771f3001

Diagram
Field Mask Reset Description

BNUM

0x70000000

0x0

Data beat number

TSIZ

0x07000000

0x0

Transaction size for the error

TSRC

0x001f0000

0x0

Source ID

TTYP

0x00003000

0x0

Transaction type for the error

VLD

0x00000001

0x0

Valid capture data
Register CAPTURE_ADDRESS
Description

Memory error address capture

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

CADDR

0xffffffff

0x0

Captured address
Register CAPTURE_EXT_ADDRESS
Description

Memory error extended address capture

Reset value

0x00000000

Warm reset mask

0x0000000f

Diagram
Field Mask Reset Description

CEADDR

0x0000000f

0x0

Captured extended address
Register ERR_SBE
Description

Single-bit ECC memory error management

Reset value

0x00000000

Warm reset mask

0x00ff00ff

Diagram
Field Mask Reset Description

SBET

0x00ff0000

0x0

Single-bit error threshold

SBEC

0x000000ff

0x0

Single-bit error counter
Register CS_BNDS
Description

Chip select memory bounds register

Reset value

0x00000000

Warm reset mask

0x0fff0fff

Diagram
Field Mask Reset Description

SA

0x0fff0000

0x0

Chip select starting address

EA

0x00000fff

0x0

Chip select ending address
Register CS_BNDS
Description

Chip select memory bounds register

Reset value

0x00000000

Warm reset mask

0x0fff0fff

Diagram
Field Mask Reset Description

SA

0x0fff0000

0x0

Chip select starting address

EA

0x00000fff

0x0

Chip select ending address
Register CS_BNDS
Description

Chip select memory bounds register

Reset value

0x00000000

Warm reset mask

0x0fff0fff

Diagram
Field Mask Reset Description

SA

0x0fff0000

0x0

Chip select starting address

EA

0x00000fff

0x0

Chip select ending address
Register CS_BNDS
Description

Chip select memory bounds register

Reset value

0x00000000

Warm reset mask

0x0fff0fff

Diagram
Field Mask Reset Description

SA

0x0fff0000

0x0

Chip select starting address

EA

0x00000fff

0x0

Chip select ending address
Register CS_CONFIG
Description

Chip select configuration register

Reset value

0x00000000

Warm reset mask

0x80f7c707

Diagram
Field Mask Reset Description

CS_EN

0x80000000

0x0

Chip select enable

AP_EN

0x00800000

0x0

Chip select auto-precharge enable

ODT_RD_CFG

0x00700000

0x0

ODT for reads configuration

ODT_WR_CFG

0x00070000

0x0

ODT for writes configuration

BA_BITS_CS

0x0000c000

0x0

Number of bank bits for SDRAM

ROW_BITS_CS

0x00000700

0x0

Number of row bits for SDRAM

COL_BITS_CS

0x00000007

0x0

Number of column bits for SDRAM
Register CS_CONFIG
Description

Chip select configuration register

Reset value

0x00000000

Warm reset mask

0x80f7c707

Diagram
Field Mask Reset Description

CS_EN

0x80000000

0x0

Chip select enable

AP_EN

0x00800000

0x0

Chip select auto-precharge enable

ODT_RD_CFG

0x00700000

0x0

ODT for reads configuration

ODT_WR_CFG

0x00070000

0x0

ODT for writes configuration

BA_BITS_CS

0x0000c000

0x0

Number of bank bits for SDRAM

ROW_BITS_CS

0x00000700

0x0

Number of row bits for SDRAM

COL_BITS_CS

0x00000007

0x0

Number of column bits for SDRAM
Register CS_CONFIG
Description

Chip select configuration register

Reset value

0x00000000

Warm reset mask

0x80f7c707

Diagram
Field Mask Reset Description

CS_EN

0x80000000

0x0

Chip select enable

AP_EN

0x00800000

0x0

Chip select auto-precharge enable

ODT_RD_CFG

0x00700000

0x0

ODT for reads configuration

ODT_WR_CFG

0x00070000

0x0

ODT for writes configuration

BA_BITS_CS

0x0000c000

0x0

Number of bank bits for SDRAM

ROW_BITS_CS

0x00000700

0x0

Number of row bits for SDRAM

COL_BITS_CS

0x00000007

0x0

Number of column bits for SDRAM
Register CS_CONFIG
Description

Chip select configuration register

Reset value

0x00000000

Warm reset mask

0x80f7c707

Diagram
Field Mask Reset Description

CS_EN

0x80000000

0x0

Chip select enable

AP_EN

0x00800000

0x0

Chip select auto-precharge enable

ODT_RD_CFG

0x00700000

0x0

ODT for reads configuration

ODT_WR_CFG

0x00070000

0x0

ODT for writes configuration

BA_BITS_CS

0x0000c000

0x0

Number of bank bits for SDRAM

ROW_BITS_CS

0x00000700

0x0

Number of row bits for SDRAM

COL_BITS_CS

0x00000007

0x0

Number of column bits for SDRAM
Register CS_CONFIG_2
Description

Chip select configuration 2 register

Reset value

0x00000000

Warm reset mask

0x07000000

Diagram
Field Mask Reset Description

PASR_CFG

0x07000000

0x0

Partial array self refresh configuration
Register CS_CONFIG_2
Description

Chip select configuration 2 register

Reset value

0x00000000

Warm reset mask

0x07000000

Diagram
Field Mask Reset Description

PASR_CFG

0x07000000

0x0

Partial array self refresh configuration
Register CS_CONFIG_2
Description

Chip select configuration 2 register

Reset value

0x00000000

Warm reset mask

0x07000000

Diagram
Field Mask Reset Description

PASR_CFG

0x07000000

0x0

Partial array self refresh configuration
Register CS_CONFIG_2
Description

Chip select configuration 2 register

Reset value

0x00000000

Warm reset mask

0x07000000

Diagram
Field Mask Reset Description

PASR_CFG

0x07000000

0x0

Partial array self refresh configuration

Commands

Name Description

delete

Dispose instance of DDR

Limitations

Only registers handling SEU and MEU events are implemented, other parts of the model are dummy non-functional registers.