P2020 DDR Model
This section describes the DDR controller model.
The model supports the handling of SEU and MEU events (i.e. correctable and uncorrectable ECC errors). Such events will update the counters and raise interrupts accordingly.
Configuration
To use SEU and MEU events connect the memoryspace upset/faulty handlers to the DDR model and allow interrupts as follows:
# Connect the memoryspace upset/faulty handlers to the ddr
connect a=mem.upsetHandlers b=ddr:CorrectableErrorIface
connect a=mem.faultyHandlers b=ddr:UncorrectableErrorIface
# Enable ECC error interrupts
ddr.ERR_INT_EN = 0x0000000c
# Set/clear faulty attribute on the given memory range
memory-set-faulty addr=0x08 obj=mem
memory-clear-faulty addr=0x08 obj=mem
# Set/clear upset attribute on the given memory range
memory-set-upset addr=0x08 obj=mem
memory-clear-upset addr=0x08 obj=mem
// Connect the memoryspace upset/faulty handlers to the ddr
temu_connect(mem, "upsetHandlers", ddr, "CorrectableErrorIface");
temu_connect(mem, "faultyHandlers", ddr, "UncorrectableErrorIface");
// Enable ECC error interrupts
temu_writeValueU32(ddr, "ERR_INT_EN", 0x0000000c, 0);
// Set/clear faulty attribute on the given memory range
temu_memorySetAttr(mem, 0x08, 4, teMA_Faulty);
temu_memoryClearAttr(mem, 0x08, 4, teMA_Faulty);
// Set/clear upset attribute on the given memory range
temu_memorySetAttr(mem, 0x08, 4, teMA_Upset);
temu_memoryClearAttr(mem, 0x08, 4, teMA_Upset);
@DDR Reference
DDR Reference
Properties
Name | Type | Description |
---|---|---|
CAPTURE_ADDRESS |
uint32_t |
|
CAPTURE_ATTRIBUTES |
uint32_t |
|
CAPTURE_DATA_HI |
uint32_t |
|
CAPTURE_DATA_LO |
uint32_t |
|
CAPTURE_ECC |
uint32_t |
|
CAPTURE_EXT_ADDRESS |
uint32_t |
|
CS_BNDS |
[uint32_t; 4] |
|
CS_CONFIG |
[uint32_t; 4] |
|
CS_CONFIG_2 |
[uint32_t; 4] |
|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
DATA_ERR_INJECT_HI |
uint32_t |
|
DATA_ERR_INJECT_LO |
uint32_t |
|
DATA_INIT |
uint32_t |
|
DDRCDR |
[uint32_t; 2] |
|
DDRDSR |
[uint32_t; 2] |
|
ERR_DETECT |
uint32_t |
|
ERR_DISABLE |
uint32_t |
|
ERR_INJECT |
uint32_t |
|
ERR_INT_EN |
uint32_t |
|
ERR_SBE |
uint32_t |
|
INIT_ADDR |
uint32_t |
|
INIT_EXT_ADDR |
uint32_t |
|
IP_REV |
[uint32_t; 2] |
|
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
SDRAM_CFG |
[uint32_t; 2] |
|
SDRAM_CLK_CNTL |
uint32_t |
|
SDRAM_INTERVAL |
uint32_t |
|
SDRAM_MD_CNTL |
uint32_t |
|
SDRAM_MODE |
[uint32_t; 2] |
|
SDRAM_RCW |
[uint32_t; 2] |
|
SR_CNTR |
uint32_t |
|
TIMING_CFG |
[uint32_t; 6] |
|
TimeSource |
*void |
Time source object |
WRLVL_CNTL |
[uint32_t; 3] |
|
ZQ_CNTL |
uint32_t |
|
config.IRQ |
uint8_t |
|
irqCtrl |
temu_IfaceRef/ <unknown> |
Interrupt controller |
memorySpace |
temu_IfaceRef/ <unknown> |
Memory space. |
Interfaces
Name | Type | Description |
---|---|---|
CorrectableErrorIface |
MemAccessIface |
|
DeviceIface |
DeviceIface |
|
MemAccessIface |
MemAccessIface |
|
ResetIface |
ResetIface |
|
UncorrectableErrorIface |
MemAccessIface |
Registers
Register support is currently experimental! |
Register Bank default
Register CAPTURE_ADDRESS
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register CAPTURE_ATTRIBUTES
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register CAPTURE_DATA_HI
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register CAPTURE_DATA_LO
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register CAPTURE_ECC
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register CAPTURE_EXT_ADDRESS
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register CS_BNDS
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register CS_CONFIG_2
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register DATA_ERR_INJECT_HI
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register DATA_ERR_INJECT_LO
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register DATA_INIT
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register DDRCDR
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register DDRDSR
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register ERR_DETECT
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register ERR_DISABLE
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register ERR_INJECT
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register ERR_INT_EN
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register ERR_SBE
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register INIT_ADDR
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register INIT_EXT_ADDR
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register IP_REV
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register SDRAM_CFG
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register SDRAM_CLK_CNTL
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register SDRAM_INTERVAL
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register SDRAM_MD_CNTL
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register SDRAM_MODE
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register SDRAM_RCW
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register SR_CNTR
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register TIMING_CFG
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |