P2020 DDR Model

This section describes the DDR controller model.

The model supports the handling of SEU and MEU events (i.e. correctable and uncorrectable ECC errors). Such events will update the counters and raise interrupts accordingly.

Loading the Plugin

import P2020

Configuration

To use SEU and MEU events connect the memoryspace upset/faulty handlers to the DDR model and allow interrupts as follows:

Connecting SEU and MEU events via Command Line
# Connect the memoryspace upset/faulty handlers to the ddr
connect a=mem.upsetHandlers b=ddr:CorrectableErrorIface
connect a=mem.faultyHandlers b=ddr:UncorrectableErrorIface

# Enable ECC error interrupts
ddr.ERR_INT_EN = 0x0000000c

# Set/clear faulty attribute on the given memory range
memory-set-faulty addr=0x08 obj=mem
memory-clear-faulty addr=0x08 obj=mem

# Set/clear upset attribute on the given memory range
memory-set-upset addr=0x08 obj=mem
memory-clear-upset addr=0x08 obj=mem
Connecting SEU and MEU events via API
// Connect the memoryspace upset/faulty handlers to the ddr
temu_connect(mem, "upsetHandlers", ddr, "CorrectableErrorIface");
temu_connect(mem, "faultyHandlers", ddr, "UncorrectableErrorIface");

// Enable ECC error interrupts
temu_writeValueU32(ddr, "ERR_INT_EN", 0x0000000c, 0);

// Set/clear faulty attribute on the given memory range
temu_memorySetAttr(mem, 0x08, 4, teMA_Faulty);
temu_memoryClearAttr(mem, 0x08, 4, teMA_Faulty);

// Set/clear upset attribute on the given memory range
temu_memorySetAttr(mem, 0x08, 4, teMA_Upset);
temu_memoryClearAttr(mem, 0x08, 4, teMA_Upset);

@DDR Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @DDR

new

Create new instance of DDR

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

DDR Reference

Properties

Name Type Description

CAPTURE_ADDRESS

uint32_t

Memory error address capture

CAPTURE_ADDRESSColdResetValue

uint32_t

Memory error address capture

CAPTURE_ADDRESSForcedBits

uint32_t

Memory error address capture

CAPTURE_ADDRESSForcedFlippedBits

uint32_t

Memory error address capture

CAPTURE_ADDRESSReadMask

uint32_t

Memory error address capture

CAPTURE_ADDRESSResetMask

uint32_t

Memory error address capture

CAPTURE_ADDRESSResetValue

uint32_t

Memory error address capture

CAPTURE_ADDRESSWriteMask

uint32_t

Memory error address capture

CAPTURE_ATTRIBUTES

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESColdResetValue

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESForcedBits

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESForcedFlippedBits

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESReadMask

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESResetMask

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESResetValue

uint32_t

Memory error attributes capture

CAPTURE_ATTRIBUTESWriteMask

uint32_t

Memory error attributes capture

CAPTURE_DATA_HI

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIColdResetValue

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIForcedBits

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIForcedFlippedBits

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIReadMask

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIResetMask

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIResetValue

uint32_t

Memory data path read capture high

CAPTURE_DATA_HIWriteMask

uint32_t

Memory data path read capture high

CAPTURE_DATA_LO

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOColdResetValue

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOForcedBits

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOForcedFlippedBits

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOReadMask

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOResetMask

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOResetValue

uint32_t

Memory data path read capture low

CAPTURE_DATA_LOWriteMask

uint32_t

Memory data path read capture low

CAPTURE_ECC

uint32_t

Memory data path read capture ECC

CAPTURE_ECCColdResetValue

uint32_t

Memory data path read capture ECC

CAPTURE_ECCForcedBits

uint32_t

Memory data path read capture ECC

CAPTURE_ECCForcedFlippedBits

uint32_t

Memory data path read capture ECC

CAPTURE_ECCReadMask

uint32_t

Memory data path read capture ECC

CAPTURE_ECCResetMask

uint32_t

Memory data path read capture ECC

CAPTURE_ECCResetValue

uint32_t

Memory data path read capture ECC

CAPTURE_ECCWriteMask

uint32_t

Memory data path read capture ECC

CAPTURE_EXT_ADDRESS

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSColdResetValue

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSForcedBits

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSForcedFlippedBits

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSReadMask

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSResetMask

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSResetValue

uint32_t

Memory error extended address capture

CAPTURE_EXT_ADDRESSWriteMask

uint32_t

Memory error extended address capture

CS_BNDS

[uint32_t; 4]

Chip select memory bounds register

CS_CONFIG

[uint32_t; 4]

Chip select configuration register

CS_CONFIG_2

[uint32_t; 4]

Chip select configuration 2 register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DATA_ERR_INJECT_HI

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIColdResetValue

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIForcedBits

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIForcedFlippedBits

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIReadMask

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIResetMask

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIResetValue

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_HIWriteMask

uint32_t

Memory data path error injection mask high

DATA_ERR_INJECT_LO

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOColdResetValue

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOForcedBits

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOForcedFlippedBits

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOReadMask

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOResetMask

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOResetValue

uint32_t

Memory data path error injection mask low

DATA_ERR_INJECT_LOWriteMask

uint32_t

Memory data path error injection mask low

DATA_INIT

uint32_t

DDR SDRAM data initialization

DATA_INITColdResetValue

uint32_t

DDR SDRAM data initialization

DATA_INITForcedBits

uint32_t

DDR SDRAM data initialization

DATA_INITForcedFlippedBits

uint32_t

DDR SDRAM data initialization

DATA_INITReadMask

uint32_t

DDR SDRAM data initialization

DATA_INITResetMask

uint32_t

DDR SDRAM data initialization

DATA_INITResetValue

uint32_t

DDR SDRAM data initialization

DATA_INITWriteMask

uint32_t

DDR SDRAM data initialization

DDRCDR_1

uint32_t

DDR control driver register 1

DDRCDR_1ColdResetValue

uint32_t

DDR control driver register 1

DDRCDR_1ForcedBits

uint32_t

DDR control driver register 1

DDRCDR_1ForcedFlippedBits

uint32_t

DDR control driver register 1

DDRCDR_1ReadMask

uint32_t

DDR control driver register 1

DDRCDR_1ResetMask

uint32_t

DDR control driver register 1

DDRCDR_1ResetValue

uint32_t

DDR control driver register 1

DDRCDR_1WriteMask

uint32_t

DDR control driver register 1

DDRCDR_2

uint32_t

DDR control driver register 2

DDRCDR_2ColdResetValue

uint32_t

DDR control driver register 2

DDRCDR_2ForcedBits

uint32_t

DDR control driver register 2

DDRCDR_2ForcedFlippedBits

uint32_t

DDR control driver register 2

DDRCDR_2ReadMask

uint32_t

DDR control driver register 2

DDRCDR_2ResetMask

uint32_t

DDR control driver register 2

DDRCDR_2ResetValue

uint32_t

DDR control driver register 2

DDRCDR_2WriteMask

uint32_t

DDR control driver register 2

DDRDSR_1

uint32_t

DDR debug status register 1

DDRDSR_1ColdResetValue

uint32_t

DDR debug status register 1

DDRDSR_1ForcedBits

uint32_t

DDR debug status register 1

DDRDSR_1ForcedFlippedBits

uint32_t

DDR debug status register 1

DDRDSR_1ReadMask

uint32_t

DDR debug status register 1

DDRDSR_1ResetMask

uint32_t

DDR debug status register 1

DDRDSR_1ResetValue

uint32_t

DDR debug status register 1

DDRDSR_1WriteMask

uint32_t

DDR debug status register 1

DDRDSR_2

uint32_t

DDR debug status register 2

DDRDSR_2ColdResetValue

uint32_t

DDR debug status register 2

DDRDSR_2ForcedBits

uint32_t

DDR debug status register 2

DDRDSR_2ForcedFlippedBits

uint32_t

DDR debug status register 2

DDRDSR_2ReadMask

uint32_t

DDR debug status register 2

DDRDSR_2ResetMask

uint32_t

DDR debug status register 2

DDRDSR_2ResetValue

uint32_t

DDR debug status register 2

DDRDSR_2WriteMask

uint32_t

DDR debug status register 2

ERR_DETECT

uint32_t

Memory error detect

ERR_DETECTColdResetValue

uint32_t

Memory error detect

ERR_DETECTForcedBits

uint32_t

Memory error detect

ERR_DETECTForcedFlippedBits

uint32_t

Memory error detect

ERR_DETECTReadMask

uint32_t

Memory error detect

ERR_DETECTResetMask

uint32_t

Memory error detect

ERR_DETECTResetValue

uint32_t

Memory error detect

ERR_DETECTWriteMask

uint32_t

Memory error detect

ERR_DISABLE

uint32_t

Memory error disable

ERR_DISABLEColdResetValue

uint32_t

Memory error disable

ERR_DISABLEForcedBits

uint32_t

Memory error disable

ERR_DISABLEForcedFlippedBits

uint32_t

Memory error disable

ERR_DISABLEReadMask

uint32_t

Memory error disable

ERR_DISABLEResetMask

uint32_t

Memory error disable

ERR_DISABLEResetValue

uint32_t

Memory error disable

ERR_DISABLEWriteMask

uint32_t

Memory error disable

ERR_INJECT

uint32_t

Memory data path error injection mask ECC

ERR_INJECTColdResetValue

uint32_t

Memory data path error injection mask ECC

ERR_INJECTForcedBits

uint32_t

Memory data path error injection mask ECC

ERR_INJECTForcedFlippedBits

uint32_t

Memory data path error injection mask ECC

ERR_INJECTReadMask

uint32_t

Memory data path error injection mask ECC

ERR_INJECTResetMask

uint32_t

Memory data path error injection mask ECC

ERR_INJECTResetValue

uint32_t

Memory data path error injection mask ECC

ERR_INJECTWriteMask

uint32_t

Memory data path error injection mask ECC

ERR_INT_EN

uint32_t

Memory error interrupt enable

ERR_INT_ENColdResetValue

uint32_t

Memory error interrupt enable

ERR_INT_ENForcedBits

uint32_t

Memory error interrupt enable

ERR_INT_ENForcedFlippedBits

uint32_t

Memory error interrupt enable

ERR_INT_ENReadMask

uint32_t

Memory error interrupt enable

ERR_INT_ENResetMask

uint32_t

Memory error interrupt enable

ERR_INT_ENResetValue

uint32_t

Memory error interrupt enable

ERR_INT_ENWriteMask

uint32_t

Memory error interrupt enable

ERR_SBE

uint32_t

Single-bit ECC memory error management

ERR_SBEColdResetValue

uint32_t

Single-bit ECC memory error management

ERR_SBEForcedBits

uint32_t

Single-bit ECC memory error management

ERR_SBEForcedFlippedBits

uint32_t

Single-bit ECC memory error management

ERR_SBEReadMask

uint32_t

Single-bit ECC memory error management

ERR_SBEResetMask

uint32_t

Single-bit ECC memory error management

ERR_SBEResetValue

uint32_t

Single-bit ECC memory error management

ERR_SBEWriteMask

uint32_t

Single-bit ECC memory error management

INIT_ADDR

uint32_t

DDR training initialization address

INIT_ADDRColdResetValue

uint32_t

DDR training initialization address

INIT_ADDRForcedBits

uint32_t

DDR training initialization address

INIT_ADDRForcedFlippedBits

uint32_t

DDR training initialization address

INIT_ADDRReadMask

uint32_t

DDR training initialization address

INIT_ADDRResetMask

uint32_t

DDR training initialization address

INIT_ADDRResetValue

uint32_t

DDR training initialization address

INIT_ADDRWriteMask

uint32_t

DDR training initialization address

INIT_EXT_ADDR

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRColdResetValue

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRForcedBits

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRForcedFlippedBits

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRReadMask

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRResetMask

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRResetValue

uint32_t

DDR training initialization extended address

INIT_EXT_ADDRWriteMask

uint32_t

DDR training initialization extended address

IP_REV1

uint32_t

DDR IP block revision 1

IP_REV1ColdResetValue

uint32_t

DDR IP block revision 1

IP_REV1ForcedBits

uint32_t

DDR IP block revision 1

IP_REV1ForcedFlippedBits

uint32_t

DDR IP block revision 1

IP_REV1ReadMask

uint32_t

DDR IP block revision 1

IP_REV1ResetMask

uint32_t

DDR IP block revision 1

IP_REV1ResetValue

uint32_t

DDR IP block revision 1

IP_REV1WriteMask

uint32_t

DDR IP block revision 1

IP_REV2

uint32_t

DDR IP block revision 2

IP_REV2ColdResetValue

uint32_t

DDR IP block revision 2

IP_REV2ForcedBits

uint32_t

DDR IP block revision 2

IP_REV2ForcedFlippedBits

uint32_t

DDR IP block revision 2

IP_REV2ReadMask

uint32_t

DDR IP block revision 2

IP_REV2ResetMask

uint32_t

DDR IP block revision 2

IP_REV2ResetValue

uint32_t

DDR IP block revision 2

IP_REV2WriteMask

uint32_t

DDR IP block revision 2

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

SDRAM_CFG

uint32_t

DDR SDRAM control configuration

SDRAM_CFGColdResetValue

uint32_t

DDR SDRAM control configuration

SDRAM_CFGForcedBits

uint32_t

DDR SDRAM control configuration

SDRAM_CFGForcedFlippedBits

uint32_t

DDR SDRAM control configuration

SDRAM_CFGReadMask

uint32_t

DDR SDRAM control configuration

SDRAM_CFGResetMask

uint32_t

DDR SDRAM control configuration

SDRAM_CFGResetValue

uint32_t

DDR SDRAM control configuration

SDRAM_CFGWriteMask

uint32_t

DDR SDRAM control configuration

SDRAM_CFG_2

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ColdResetValue

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ForcedBits

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ForcedFlippedBits

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ReadMask

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ResetMask

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2ResetValue

uint32_t

DDR SDRAM control configuration 2

SDRAM_CFG_2WriteMask

uint32_t

DDR SDRAM control configuration 2

SDRAM_CLK_CNTL

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLColdResetValue

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLForcedBits

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLForcedFlippedBits

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLReadMask

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLResetMask

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLResetValue

uint32_t

DDR SDRAM clock control

SDRAM_CLK_CNTLWriteMask

uint32_t

DDR SDRAM clock control

SDRAM_INTERVAL

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALColdResetValue

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALForcedBits

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALForcedFlippedBits

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALReadMask

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALResetMask

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALResetValue

uint32_t

DDR SDRAM interval configuration

SDRAM_INTERVALWriteMask

uint32_t

DDR SDRAM interval configuration

SDRAM_MD_CNTL

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLColdResetValue

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLForcedBits

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLForcedFlippedBits

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLReadMask

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLResetMask

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLResetValue

uint32_t

DDR SDRAM mode control

SDRAM_MD_CNTLWriteMask

uint32_t

DDR SDRAM mode control

SDRAM_MODE

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEColdResetValue

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEForcedBits

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEForcedFlippedBits

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEReadMask

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEResetMask

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEResetValue

uint32_t

DDR SDRAM mode configuration

SDRAM_MODEWriteMask

uint32_t

DDR SDRAM mode configuration

SDRAM_MODE_2

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ColdResetValue

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ForcedBits

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ForcedFlippedBits

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ReadMask

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ResetMask

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2ResetValue

uint32_t

DDR SDRAM mode configuration 2

SDRAM_MODE_2WriteMask

uint32_t

DDR SDRAM mode configuration 2

SDRAM_RCW_1

uint32_t

DDR register control words 1

SDRAM_RCW_1ColdResetValue

uint32_t

DDR register control words 1

SDRAM_RCW_1ForcedBits

uint32_t

DDR register control words 1

SDRAM_RCW_1ForcedFlippedBits

uint32_t

DDR register control words 1

SDRAM_RCW_1ReadMask

uint32_t

DDR register control words 1

SDRAM_RCW_1ResetMask

uint32_t

DDR register control words 1

SDRAM_RCW_1ResetValue

uint32_t

DDR register control words 1

SDRAM_RCW_1WriteMask

uint32_t

DDR register control words 1

SDRAM_RCW_2

uint32_t

DDR register control words 2

SDRAM_RCW_2ColdResetValue

uint32_t

DDR register control words 2

SDRAM_RCW_2ForcedBits

uint32_t

DDR register control words 2

SDRAM_RCW_2ForcedFlippedBits

uint32_t

DDR register control words 2

SDRAM_RCW_2ReadMask

uint32_t

DDR register control words 2

SDRAM_RCW_2ResetMask

uint32_t

DDR register control words 2

SDRAM_RCW_2ResetValue

uint32_t

DDR register control words 2

SDRAM_RCW_2WriteMask

uint32_t

DDR register control words 2

SR_CNTR

uint32_t

DDR self refresh counter

SR_CNTRColdResetValue

uint32_t

DDR self refresh counter

SR_CNTRForcedBits

uint32_t

DDR self refresh counter

SR_CNTRForcedFlippedBits

uint32_t

DDR self refresh counter

SR_CNTRReadMask

uint32_t

DDR self refresh counter

SR_CNTRResetMask

uint32_t

DDR self refresh counter

SR_CNTRResetValue

uint32_t

DDR self refresh counter

SR_CNTRWriteMask

uint32_t

DDR self refresh counter

TIMING_CFG_0

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ColdResetValue

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ForcedBits

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ReadMask

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ResetMask

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0ResetValue

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_0WriteMask

uint32_t

DDR SDRAM timing configuration 0

TIMING_CFG_1

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ColdResetValue

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ForcedBits

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ReadMask

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ResetMask

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1ResetValue

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_1WriteMask

uint32_t

DDR SDRAM timing configuration 1

TIMING_CFG_2

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ColdResetValue

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ForcedBits

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ReadMask

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ResetMask

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2ResetValue

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_2WriteMask

uint32_t

DDR SDRAM timing configuration 2

TIMING_CFG_3

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ColdResetValue

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ForcedBits

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ReadMask

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ResetMask

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3ResetValue

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_3WriteMask

uint32_t

DDR SDRAM timing configuration 3

TIMING_CFG_4

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ColdResetValue

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ForcedBits

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ReadMask

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ResetMask

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4ResetValue

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_4WriteMask

uint32_t

DDR SDRAM timing configuration 4

TIMING_CFG_5

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ColdResetValue

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ForcedBits

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ForcedFlippedBits

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ReadMask

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ResetMask

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5ResetValue

uint32_t

DDR SDRAM timing configuration 5

TIMING_CFG_5WriteMask

uint32_t

DDR SDRAM timing configuration 5

TimeSource

*void

Time source object

WRLVL_CNTL

uint32_t

DDR write leveling control

WRLVL_CNTLColdResetValue

uint32_t

DDR write leveling control

WRLVL_CNTLForcedBits

uint32_t

DDR write leveling control

WRLVL_CNTLForcedFlippedBits

uint32_t

DDR write leveling control

WRLVL_CNTLReadMask

uint32_t

DDR write leveling control

WRLVL_CNTLResetMask

uint32_t

DDR write leveling control

WRLVL_CNTLResetValue

uint32_t

DDR write leveling control

WRLVL_CNTLWriteMask

uint32_t

DDR write leveling control

WRLVL_CNTL_2

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ColdResetValue

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ForcedBits

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ForcedFlippedBits

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ReadMask

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ResetMask

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2ResetValue

uint32_t

DDR write leveling control 2

WRLVL_CNTL_2WriteMask

uint32_t

DDR write leveling control 2

WRLVL_CNTL_3

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ColdResetValue

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ForcedBits

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ForcedFlippedBits

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ReadMask

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ResetMask

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3ResetValue

uint32_t

DDR write leveling control 3

WRLVL_CNTL_3WriteMask

uint32_t

DDR write leveling control 3

ZQ_CNTL

uint32_t

DDR ZQ calibration control

ZQ_CNTLColdResetValue

uint32_t

DDR ZQ calibration control

ZQ_CNTLForcedBits

uint32_t

DDR ZQ calibration control

ZQ_CNTLForcedFlippedBits

uint32_t

DDR ZQ calibration control

ZQ_CNTLReadMask

uint32_t

DDR ZQ calibration control

ZQ_CNTLResetMask

uint32_t

DDR ZQ calibration control

ZQ_CNTLResetValue

uint32_t

DDR ZQ calibration control

ZQ_CNTLWriteMask

uint32_t

DDR ZQ calibration control

config.IRQ

uint8_t

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller

memorySpace

temu_IfaceRef/ <unknown>

Memory space.

Interfaces

Name Type Description

CorrectableErrorIface

MemAccessIface

DeviceIface

DeviceIface

MemAccessIface

MemAccessIface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

UncorrectableErrorIface

MemAccessIface

Commands

Name Description

delete

Dispose instance of DDR

Limitations

Only registers handling SEU and MEU events are implemented, other parts of the model are dummy non-functional registers.