Configuration
Interrupt Delivery
The property irqControl should be connected to the device which the MEC raises interrupts on, this is normally a CPU object. The connection should be made to the CPU-object’s interface of type IrqIface. Note that the CPU must support interrupts 1 through 15, this is in general case correct for SPARC based processors, but other CPUs may not be compatible.
UART Connections
Two serial interfaces exist, the UartAIface and the UartBIface, these can be connected to in order to receive data from remote serial port terminals (i.e. this is the RX direction). The uarta and uartb properties can be used to connect the TX direction of the UARTs.
Infinite UART Speed
Set config.infiniteUartSpeed to nonzero to enable infinite speed on the Tx channels. With infinite speed, a written byte is immediately forwarded to the destination device, with limited UART speed (the variable being zero) the timing due to UART scaler bits (upper 8 bits of the MecCtrlReg) will be simulated, leading to realistic byte rates over the serial port device. Note that individual bits are not transmitted only the bytes.
@Mec Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
Mec Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
accessProtSegment1Base |
uint32_t |
Access protection segment 1 base register |
accessProtSegment1BaseColdResetValue |
uint32_t |
Access protection segment 1 base register |
accessProtSegment1BaseForcedBits |
uint32_t |
Access protection segment 1 base register |
accessProtSegment1BaseForcedFlippedBits |
uint32_t |
Access protection segment 1 base register |
accessProtSegment1BaseReadMask |
uint32_t |
Access protection segment 1 base register |
accessProtSegment1BaseResetMask |
uint32_t |
Access protection segment 1 base register |
accessProtSegment1BaseResetValue |
uint32_t |
Access protection segment 1 base register |
accessProtSegment1BaseWriteMask |
uint32_t |
Access protection segment 1 base register |
accessProtSegment1End |
uint32_t |
Access protection segment 1 end register |
accessProtSegment1EndColdResetValue |
uint32_t |
Access protection segment 1 end register |
accessProtSegment1EndForcedBits |
uint32_t |
Access protection segment 1 end register |
accessProtSegment1EndForcedFlippedBits |
uint32_t |
Access protection segment 1 end register |
accessProtSegment1EndReadMask |
uint32_t |
Access protection segment 1 end register |
accessProtSegment1EndResetMask |
uint32_t |
Access protection segment 1 end register |
accessProtSegment1EndResetValue |
uint32_t |
Access protection segment 1 end register |
accessProtSegment1EndWriteMask |
uint32_t |
Access protection segment 1 end register |
accessProtSegment2Base |
uint32_t |
Access protection segment 2 base register |
accessProtSegment2BaseColdResetValue |
uint32_t |
Access protection segment 2 base register |
accessProtSegment2BaseForcedBits |
uint32_t |
Access protection segment 2 base register |
accessProtSegment2BaseForcedFlippedBits |
uint32_t |
Access protection segment 2 base register |
accessProtSegment2BaseReadMask |
uint32_t |
Access protection segment 2 base register |
accessProtSegment2BaseResetMask |
uint32_t |
Access protection segment 2 base register |
accessProtSegment2BaseResetValue |
uint32_t |
Access protection segment 2 base register |
accessProtSegment2BaseWriteMask |
uint32_t |
Access protection segment 2 base register |
accessProtSegment2End |
uint32_t |
Access protection segment 2 end register |
accessProtSegment2EndColdResetValue |
uint32_t |
Access protection segment 2 end register |
accessProtSegment2EndForcedBits |
uint32_t |
Access protection segment 2 end register |
accessProtSegment2EndForcedFlippedBits |
uint32_t |
Access protection segment 2 end register |
accessProtSegment2EndReadMask |
uint32_t |
Access protection segment 2 end register |
accessProtSegment2EndResetMask |
uint32_t |
Access protection segment 2 end register |
accessProtSegment2EndResetValue |
uint32_t |
Access protection segment 2 end register |
accessProtSegment2EndWriteMask |
uint32_t |
Access protection segment 2 end register |
config.infiniteUartSpeed |
uint32_t |
|
cpu |
temu_IfaceRef/ <unknown> |
Processor |
errorAndResetStatus |
uint32_t |
Error and reset status register |
errorAndResetStatusColdResetValue |
uint32_t |
Error and reset status register |
errorAndResetStatusForcedBits |
uint32_t |
Error and reset status register |
errorAndResetStatusForcedFlippedBits |
uint32_t |
Error and reset status register |
errorAndResetStatusReadMask |
uint32_t |
Error and reset status register |
errorAndResetStatusResetMask |
uint32_t |
Error and reset status register |
errorAndResetStatusResetValue |
uint32_t |
Error and reset status register |
errorAndResetStatusWriteMask |
uint32_t |
Error and reset status register |
failingAddr |
uint32_t |
Failing address register |
failingAddrColdResetValue |
uint32_t |
Failing address register |
failingAddrForcedBits |
uint32_t |
Failing address register |
failingAddrForcedFlippedBits |
uint32_t |
Failing address register |
failingAddrReadMask |
uint32_t |
Failing address register |
failingAddrResetMask |
uint32_t |
Failing address register |
failingAddrResetValue |
uint32_t |
Failing address register |
failingAddrWriteMask |
uint32_t |
Failing address register |
gpiConfig |
uint32_t |
GPIO configuration register |
gpiConfigColdResetValue |
uint32_t |
GPIO configuration register |
gpiConfigForcedBits |
uint32_t |
GPIO configuration register |
gpiConfigForcedFlippedBits |
uint32_t |
GPIO configuration register |
gpiConfigReadMask |
uint32_t |
GPIO configuration register |
gpiConfigResetMask |
uint32_t |
GPIO configuration register |
gpiConfigResetValue |
uint32_t |
GPIO configuration register |
gpiConfigWriteMask |
uint32_t |
GPIO configuration register |
gpiData |
uint32_t |
GPIO data register |
gpiDataColdResetValue |
uint32_t |
GPIO data register |
gpiDataForcedBits |
uint32_t |
GPIO data register |
gpiDataForcedFlippedBits |
uint32_t |
GPIO data register |
gpiDataReadMask |
uint32_t |
GPIO data register |
gpiDataResetMask |
uint32_t |
GPIO data register |
gpiDataResetValue |
uint32_t |
GPIO data register |
gpiDataWriteMask |
uint32_t |
GPIO data register |
gptCounter |
uint32_t |
General purpose timer counter register |
gptCounterColdResetValue |
uint32_t |
General purpose timer counter register |
gptCounterForcedBits |
uint32_t |
General purpose timer counter register |
gptCounterForcedFlippedBits |
uint32_t |
General purpose timer counter register |
gptCounterProgramReg |
uint32_t |
|
gptCounterReadMask |
uint32_t |
General purpose timer counter register |
gptCounterResetMask |
uint32_t |
General purpose timer counter register |
gptCounterResetValue |
uint32_t |
General purpose timer counter register |
gptCounterWriteMask |
uint32_t |
General purpose timer counter register |
gptScaler |
uint32_t |
General purpose timer scaler register |
gptScalerColdResetValue |
uint32_t |
General purpose timer scaler register |
gptScalerForcedBits |
uint32_t |
General purpose timer scaler register |
gptScalerForcedFlippedBits |
uint32_t |
General purpose timer scaler register |
gptScalerProgramReg |
uint32_t |
|
gptScalerReadMask |
uint32_t |
General purpose timer scaler register |
gptScalerResetMask |
uint32_t |
General purpose timer scaler register |
gptScalerResetValue |
uint32_t |
General purpose timer scaler register |
gptScalerWriteMask |
uint32_t |
General purpose timer scaler register |
ioConfig |
uint32_t |
I/O configuration register |
ioConfigColdResetValue |
uint32_t |
I/O configuration register |
ioConfigForcedBits |
uint32_t |
I/O configuration register |
ioConfigForcedFlippedBits |
uint32_t |
I/O configuration register |
ioConfigReadMask |
uint32_t |
I/O configuration register |
ioConfigResetMask |
uint32_t |
I/O configuration register |
ioConfigResetValue |
uint32_t |
I/O configuration register |
ioConfigWriteMask |
uint32_t |
I/O configuration register |
irqClear |
uint32_t |
Interrupt clear register |
irqClearColdResetValue |
uint32_t |
Interrupt clear register |
irqClearForcedBits |
uint32_t |
Interrupt clear register |
irqClearForcedFlippedBits |
uint32_t |
Interrupt clear register |
irqClearReadMask |
uint32_t |
Interrupt clear register |
irqClearResetMask |
uint32_t |
Interrupt clear register |
irqClearResetValue |
uint32_t |
Interrupt clear register |
irqClearWriteMask |
uint32_t |
Interrupt clear register |
irqControl |
temu_IfaceRef/ <unknown> |
Upstream interrupt controller (e.g. CPU) |
irqForce |
uint32_t |
Interrupt force register |
irqForceColdResetValue |
uint32_t |
Interrupt force register |
irqForceForcedBits |
uint32_t |
Interrupt force register |
irqForceForcedFlippedBits |
uint32_t |
Interrupt force register |
irqForceReadMask |
uint32_t |
Interrupt force register |
irqForceResetMask |
uint32_t |
Interrupt force register |
irqForceResetValue |
uint32_t |
Interrupt force register |
irqForceWriteMask |
uint32_t |
Interrupt force register |
irqMask |
uint32_t |
Interrupt mask register |
irqMaskColdResetValue |
uint32_t |
Interrupt mask register |
irqMaskForcedBits |
uint32_t |
Interrupt mask register |
irqMaskForcedFlippedBits |
uint32_t |
Interrupt mask register |
irqMaskReadMask |
uint32_t |
Interrupt mask register |
irqMaskResetMask |
uint32_t |
Interrupt mask register |
irqMaskResetValue |
uint32_t |
Interrupt mask register |
irqMaskWriteMask |
uint32_t |
Interrupt mask register |
irqPending |
uint32_t |
Interrupt pending register |
irqPendingColdResetValue |
uint32_t |
Interrupt pending register |
irqPendingForcedBits |
uint32_t |
Interrupt pending register |
irqPendingForcedFlippedBits |
uint32_t |
Interrupt pending register |
irqPendingReadMask |
uint32_t |
Interrupt pending register |
irqPendingResetMask |
uint32_t |
Interrupt pending register |
irqPendingResetValue |
uint32_t |
Interrupt pending register |
irqPendingWriteMask |
uint32_t |
Interrupt pending register |
irqShape |
uint32_t |
Interrupt shape register |
irqShapeColdResetValue |
uint32_t |
Interrupt shape register |
irqShapeForcedBits |
uint32_t |
Interrupt shape register |
irqShapeForcedFlippedBits |
uint32_t |
Interrupt shape register |
irqShapeReadMask |
uint32_t |
Interrupt shape register |
irqShapeResetMask |
uint32_t |
Interrupt shape register |
irqShapeResetValue |
uint32_t |
Interrupt shape register |
irqShapeWriteMask |
uint32_t |
Interrupt shape register |
irqSignalStatus |
uint16_t |
Interrupt signal status (should be the same as pending in CPU) |
mecCtrl |
uint32_t |
MEC control register |
mecCtrlColdResetValue |
uint32_t |
MEC control register |
mecCtrlForcedBits |
uint32_t |
MEC control register |
mecCtrlForcedFlippedBits |
uint32_t |
MEC control register |
mecCtrlReadMask |
uint32_t |
MEC control register |
mecCtrlResetMask |
uint32_t |
MEC control register |
mecCtrlResetValue |
uint32_t |
MEC control register |
mecCtrlWriteMask |
uint32_t |
MEC control register |
memoryConfig |
uint32_t |
Memory configuration register |
memoryConfigColdResetValue |
uint32_t |
Memory configuration register |
memoryConfigForcedBits |
uint32_t |
Memory configuration register |
memoryConfigForcedFlippedBits |
uint32_t |
Memory configuration register |
memoryConfigReadMask |
uint32_t |
Memory configuration register |
memoryConfigResetMask |
uint32_t |
Memory configuration register |
memoryConfigResetValue |
uint32_t |
Memory configuration register |
memoryConfigWriteMask |
uint32_t |
Memory configuration register |
outSignals |
[temu_IfaceRef; 8]/ <unknown> |
GPIO signals |
powerDown |
uint32_t |
Power down register |
powerDownColdResetValue |
uint32_t |
Power down register |
powerDownForcedBits |
uint32_t |
Power down register |
powerDownForcedFlippedBits |
uint32_t |
Power down register |
powerDownReadMask |
uint32_t |
Power down register |
powerDownResetMask |
uint32_t |
Power down register |
powerDownResetValue |
uint32_t |
Power down register |
powerDownWriteMask |
uint32_t |
Power down register |
rtcCounter |
uint32_t |
Real-time clock counter register |
rtcCounterColdResetValue |
uint32_t |
Real-time clock counter register |
rtcCounterForcedBits |
uint32_t |
Real-time clock counter register |
rtcCounterForcedFlippedBits |
uint32_t |
Real-time clock counter register |
rtcCounterProgramReg |
uint32_t |
|
rtcCounterReadMask |
uint32_t |
Real-time clock counter register |
rtcCounterResetMask |
uint32_t |
Real-time clock counter register |
rtcCounterResetValue |
uint32_t |
Real-time clock counter register |
rtcCounterWriteMask |
uint32_t |
Real-time clock counter register |
rtcScaler |
uint32_t |
Real-time clock scaler register |
rtcScalerColdResetValue |
uint32_t |
Real-time clock scaler register |
rtcScalerForcedBits |
uint32_t |
Real-time clock scaler register |
rtcScalerForcedFlippedBits |
uint32_t |
Real-time clock scaler register |
rtcScalerProgramReg |
uint32_t |
|
rtcScalerReadMask |
uint32_t |
Real-time clock scaler register |
rtcScalerResetMask |
uint32_t |
Real-time clock scaler register |
rtcScalerResetValue |
uint32_t |
Real-time clock scaler register |
rtcScalerWriteMask |
uint32_t |
Real-time clock scaler register |
softwareReset |
uint32_t |
Software reset register |
softwareResetColdResetValue |
uint32_t |
Software reset register |
softwareResetForcedBits |
uint32_t |
Software reset register |
softwareResetForcedFlippedBits |
uint32_t |
Software reset register |
softwareResetReadMask |
uint32_t |
Software reset register |
softwareResetResetMask |
uint32_t |
Software reset register |
softwareResetResetValue |
uint32_t |
Software reset register |
softwareResetWriteMask |
uint32_t |
Software reset register |
systemFaultStatus |
uint32_t |
System fault status register |
systemFaultStatusColdResetValue |
uint32_t |
System fault status register |
systemFaultStatusForcedBits |
uint32_t |
System fault status register |
systemFaultStatusForcedFlippedBits |
uint32_t |
System fault status register |
systemFaultStatusReadMask |
uint32_t |
System fault status register |
systemFaultStatusResetMask |
uint32_t |
System fault status register |
systemFaultStatusResetValue |
uint32_t |
System fault status register |
systemFaultStatusWriteMask |
uint32_t |
System fault status register |
testControl |
uint32_t |
Test control register |
testControlColdResetValue |
uint32_t |
Test control register |
testControlForcedBits |
uint32_t |
Test control register |
testControlForcedFlippedBits |
uint32_t |
Test control register |
testControlReadMask |
uint32_t |
Test control register |
testControlResetMask |
uint32_t |
Test control register |
testControlResetValue |
uint32_t |
Test control register |
testControlWriteMask |
uint32_t |
Test control register |
timerControl |
uint32_t |
Timer control register |
timerControlColdResetValue |
uint32_t |
Timer control register |
timerControlForcedBits |
uint32_t |
Timer control register |
timerControlForcedFlippedBits |
uint32_t |
Timer control register |
timerControlReadMask |
uint32_t |
Timer control register |
timerControlResetMask |
uint32_t |
Timer control register |
timerControlResetValue |
uint32_t |
Timer control register |
timerControlWriteMask |
uint32_t |
Timer control register |
uartChanARxTx |
uint32_t |
UART channel A receive/transmit register |
uartChanARxTxColdResetValue |
uint32_t |
UART channel A receive/transmit register |
uartChanARxTxForcedBits |
uint32_t |
UART channel A receive/transmit register |
uartChanARxTxForcedFlippedBits |
uint32_t |
UART channel A receive/transmit register |
uartChanARxTxReadMask |
uint32_t |
UART channel A receive/transmit register |
uartChanARxTxResetMask |
uint32_t |
UART channel A receive/transmit register |
uartChanARxTxResetValue |
uint32_t |
UART channel A receive/transmit register |
uartChanARxTxWriteMask |
uint32_t |
UART channel A receive/transmit register |
uartChanBRxTx |
uint32_t |
UART channel B receive/transmit register |
uartChanBRxTxColdResetValue |
uint32_t |
UART channel B receive/transmit register |
uartChanBRxTxForcedBits |
uint32_t |
UART channel B receive/transmit register |
uartChanBRxTxForcedFlippedBits |
uint32_t |
UART channel B receive/transmit register |
uartChanBRxTxReadMask |
uint32_t |
UART channel B receive/transmit register |
uartChanBRxTxResetMask |
uint32_t |
UART channel B receive/transmit register |
uartChanBRxTxResetValue |
uint32_t |
UART channel B receive/transmit register |
uartChanBRxTxWriteMask |
uint32_t |
UART channel B receive/transmit register |
uartStatus |
uint32_t |
UART status register |
uartStatusColdResetValue |
uint32_t |
UART status register |
uartStatusForcedBits |
uint32_t |
UART status register |
uartStatusForcedFlippedBits |
uint32_t |
UART status register |
uartStatusReadMask |
uint32_t |
UART status register |
uartStatusResetMask |
uint32_t |
UART status register |
uartStatusResetValue |
uint32_t |
UART status register |
uartStatusWriteMask |
uint32_t |
UART status register |
uarta |
temu_IfaceRef/ <unknown> |
Serial port A |
uartb |
temu_IfaceRef/ <unknown> |
Serial port B |
waitStateConfig |
uint32_t |
Wait-state configuration register |
waitStateConfigColdResetValue |
uint32_t |
Wait-state configuration register |
waitStateConfigForcedBits |
uint32_t |
Wait-state configuration register |
waitStateConfigForcedFlippedBits |
uint32_t |
Wait-state configuration register |
waitStateConfigReadMask |
uint32_t |
Wait-state configuration register |
waitStateConfigResetMask |
uint32_t |
Wait-state configuration register |
waitStateConfigResetValue |
uint32_t |
Wait-state configuration register |
waitStateConfigWriteMask |
uint32_t |
Wait-state configuration register |
wdogProgAndTimeoutAck |
uint32_t |
Watchdog program and timeout acknowledge register |
wdogProgAndTimeoutAckColdResetValue |
uint32_t |
Watchdog program and timeout acknowledge register |
wdogProgAndTimeoutAckForcedBits |
uint32_t |
Watchdog program and timeout acknowledge register |
wdogProgAndTimeoutAckForcedFlippedBits |
uint32_t |
Watchdog program and timeout acknowledge register |
wdogProgAndTimeoutAckReadMask |
uint32_t |
Watchdog program and timeout acknowledge register |
wdogProgAndTimeoutAckResetMask |
uint32_t |
Watchdog program and timeout acknowledge register |
wdogProgAndTimeoutAckResetValue |
uint32_t |
Watchdog program and timeout acknowledge register |
wdogProgAndTimeoutAckWriteMask |
uint32_t |
Watchdog program and timeout acknowledge register |
wdogTrapDoorSet |
uint32_t |
Watchdog trap door set register |
wdogTrapDoorSetColdResetValue |
uint32_t |
Watchdog trap door set register |
wdogTrapDoorSetForcedBits |
uint32_t |
Watchdog trap door set register |
wdogTrapDoorSetForcedFlippedBits |
uint32_t |
Watchdog trap door set register |
wdogTrapDoorSetReadMask |
uint32_t |
Watchdog trap door set register |
wdogTrapDoorSetResetMask |
uint32_t |
Watchdog trap door set register |
wdogTrapDoorSetResetValue |
uint32_t |
Watchdog trap door set register |
wdogTrapDoorSetWriteMask |
uint32_t |
Watchdog trap door set register |
Interfaces
| Name | Type | Description |
|---|---|---|
DeviceIface |
DeviceIface |
|
IrqClientIface |
IrqClientIface |
|
IrqIface |
IrqIface |
|
MemAccessIface |
MemAccessIface |
|
RegisterIface |
temu::RegisterIface |
Auto-generated Register Interface Impl. |
ResetIface |
ResetIface |
|
SignalIface |
SignalIface |
Incomming signals |
UartAIface |
SerialIface |
|
UartBIface |
SerialIface |
Ports
| Prop | Iface | Description |
|---|---|---|
irqControl |
IrqClientIface |
uart a |
uarta |
UartAIface |
uart a |
uartb |
UartBIface |
uart b |
Registers
| Register support is currently experimental! |
Register Bank Regs
Register mecCtrl
- Description
-
MEC control register
- Reset value
-
0x01b50014
- Warm reset mask
-
0xffff7fff
| Field | Mask | Reset | Description |
|---|---|---|---|
Scaler |
|
|
UART scaler |
UCS |
|
|
UART clock supply |
USB |
|
|
UART stop bits |
UP |
|
|
UART parity |
UPE |
|
|
UART parity enable |
UBR |
|
|
UART baud rate divider select |
DST |
|
|
DMA session timeout enable |
DPE |
|
|
DMA parity enable |
DMAE |
|
|
DMA enable |
reserved |
|
|
Reserved |
RHMECHE |
|
|
Reset or halt on MEC hardware error |
MECHEMSK |
|
|
MEC hardware error mask |
RHFPUCMP |
|
|
Reset or halt on FPU comparison error |
FPUCMPMSK |
|
|
FPU comparison error mask |
RHIUCMP |
|
|
Reset or halt on IU comparison error |
IUCMPMSK |
|
|
IU comparison error mask |
RHIUHE |
|
|
Reset or halt on IU hardware error |
IUHEMSK |
|
|
IU hardware error mask |
RHIUEM |
|
|
Reset or halt on IU error mode |
IUEMMSK |
|
|
IU error mode mask |
WDCS |
|
|
Watchdog clock supply |
BP |
|
|
Block protection instead of normal access protection |
BTO |
|
|
Bus timeout enable |
SWR |
|
|
Software reset enable |
PRD |
|
|
Power-down mode enable |
Register softwareReset
- Description
-
Software reset register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
SFR |
|
|
Software reset trigger |
Register powerDown
- Description
-
Power down register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
PD |
|
|
Power-down trigger |
Register memoryConfig
- Description
-
Memory configuration register
- Reset value
-
0x00010000
- Warm reset mask
-
0x3f1f7fff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
EEX |
|
|
Exchange memory enable |
EEC |
|
|
Exchange memory EDAC enable |
EPA |
|
|
Exchange memory parity enable |
ESIZ |
|
|
Exchange memory size |
reserved |
|
|
Reserved |
PSIZ |
|
|
PROM size |
P8 |
|
|
PROM 8-bit mode |
PWR |
|
|
PROM write enable |
reserved |
|
|
Reserved |
REC |
|
|
RAM EDAC enable |
RPA |
|
|
RAM parity enable |
RSIZ |
|
|
RAM size |
RBR1 |
|
|
Redundant RAM block 1 replace |
RBS1 |
|
|
Redundant RAM block 1 selected |
RBR0 |
|
|
Redundant RAM block 0 replace |
RBS0 |
|
|
Redundant RAM block 0 selected |
RBCS |
|
|
Number of RAM block chip selects |
Register ioConfig
- Description
-
I/O configuration register
- Reset value
-
0x00000000
- Warm reset mask
-
0x3f3f3f3f
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
PA3 |
|
|
I/O unit 3 parity enable |
IO3 |
|
|
I/O unit 3 enable |
SIZ3 |
|
|
I/O unit 3 size |
reserved |
|
|
Reserved |
PA2 |
|
|
I/O unit 2 parity enable |
IO2 |
|
|
I/O unit 2 enable |
SIZ2 |
|
|
I/O unit 2 size |
reserved |
|
|
Reserved |
PA1 |
|
|
I/O unit 1 parity enable |
IO1 |
|
|
I/O unit 1 enable |
SIZ1 |
|
|
I/O unit 1 size |
reserved |
|
|
Reserved |
PA0 |
|
|
I/O unit 0 parity enable |
IO0 |
|
|
I/O unit 0 enable |
SIZ0 |
|
|
I/O unit 0 size |
Register waitStateConfig
- Description
-
Wait-state configuration register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
IO3RW |
|
|
I/O unit 3 read/write waitstates |
IO2RW |
|
|
I/O unit 2 read/write waitstates |
IO1RW |
|
|
I/O unit 1 read/write waitstates |
IO0RW |
|
|
I/O unit 0 read/write waitstates |
EXRW |
|
|
Exchange memory read/write waitstates |
PRW |
|
|
PROM write waitstates |
PRR |
|
|
PROM read waitstates |
RAW |
|
|
RAM write waitstates |
RAR |
|
|
RAM read waitstates |
Register accessProtSegment1Base
- Description
-
Access protection segment 1 base register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
SE |
|
|
Supervisor mode enable |
UE |
|
|
User mode enable |
SEGBASE |
|
|
Segment base address |
Register accessProtSegment1End
- Description
-
Access protection segment 1 end register
- Reset value
-
0x00000000
- Warm reset mask
-
0x007fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
SEGEND |
|
|
Segment end address |
Register accessProtSegment2Base
- Description
-
Access protection segment 2 base register
- Reset value
-
0x00000000
- Warm reset mask
-
0x01ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
SE |
|
|
Supervisor mode enable |
UE |
|
|
User mode enable |
SEGBASE |
|
|
Segment base address |
Register accessProtSegment2End
- Description
-
Access protection segment 2 end register
- Reset value
-
0x00000000
- Warm reset mask
-
0x007fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
SEGEND |
|
|
Segment end address |
Register irqShape
- Description
-
Interrupt shape register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00001fff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
POL |
|
|
External interrupt polarity select |
ACK |
|
|
External interrupt acknowledge select |
EDGE |
|
|
External interrupt edge/level select |
Register irqPending
- Description
-
Interrupt pending register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000fffe
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
IP |
|
|
Interrupt pending bits |
reserved |
|
|
Reserved |
Register irqMask
- Description
-
Interrupt mask register
- Reset value
-
0x00007ffe
- Warm reset mask
-
0x00007ffe
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
IM |
|
|
Interrupt mask bits |
reserved |
|
|
Reserved |
Register irqClear
- Description
-
Interrupt clear register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
IC |
|
|
Interrupt clear bits |
reserved |
|
|
Reserved |
Register irqForce
- Description
-
Interrupt force register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000fffe
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
IF |
|
|
Interrupt force bits |
reserved |
|
|
Reserved |
Register wdogProgAndTimeoutAck
- Description
-
Watchdog program and timeout acknowledge register
- Reset value
-
0xffffffff
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
WDR |
|
|
Watchdog reset counter value |
WDS |
|
|
Watchdog preset scaler value |
WDC |
|
|
Watchdog preset counter value |
Register wdogTrapDoorSet
- Description
-
Watchdog trap door set register
- Reset value
-
0xffffffff
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
TD |
|
|
Watchdog trap door set |
Register rtcCounter
- Description
-
Real-time clock counter register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
RTCC |
|
|
Real-time clock counter |
Register rtcScaler
- Description
-
Real-time clock scaler register
- Reset value
-
0x000000ff
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
RTCS |
|
|
Real-time clock scaler |
Register gptCounter
- Description
-
General purpose timer counter register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
GPTC |
|
|
General purpose timer counter |
Register gptScaler
- Description
-
General purpose timer scaler register
- Reset value
-
0x0000ffff
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
GPTS |
|
|
General purpose timer scaler |
Register timerControl
- Description
-
Timer control register
- Reset value
-
0x00000100
- Warm reset mask
-
0x00000f0f
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
RTCSL |
|
|
Real-time clock scaler load |
RTCSE |
|
|
Real-time clock scaler enable |
RTCCL |
|
|
Real-time clock counter load |
RTCCR |
|
|
Real-time clock counter reload |
reserved |
|
|
Reserved |
GSL |
|
|
General purpose timer scaler load |
GSE |
|
|
General purpose timer enable |
GCL |
|
|
General purpose timer counter load |
GCR |
|
|
General purpose timer counter reload |
Register systemFaultStatus
- Description
-
System fault status register
- Reset value
-
0x00000078
- Warm reset mask
-
0x0000f77c
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
AT |
|
|
Access type |
reserved |
|
|
Reserved |
ASFT |
|
|
Asynchronous fault type |
ASFV |
|
|
Asynchronous fault valid |
reserved |
|
|
Reserved |
SRFT |
|
|
Data fault type or DMA error type |
SDFV |
|
|
IU data fault valid |
reserved |
|
|
Reserved |
Register failingAddr
- Description
-
Failing address register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FFA |
|
|
Failing address |
Register gpiConfig
- Description
-
GPIO configuration register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
RF |
|
|
GPIO read flag |
IO |
|
|
GPIO input/output select |
Register gpiData
- Description
-
GPIO data register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
IOD |
|
|
GPIO data |
Register errorAndResetStatus
- Description
-
Error and reset status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000f03f
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
RSTC |
|
|
Reset cause |
HLT |
|
|
IU/FPU halted |
SYSAV |
|
|
ERC32 system availability |
reserved |
|
|
Reserved |
MECHE |
|
|
MEC hardware error |
FPUCMP |
|
|
FPU comparison error |
FPUHE |
|
|
FPU hardware error |
IUCMP |
|
|
IU comparison error |
IUHE |
|
|
IU hardware error |
IUEM |
|
|
IU error mode |
Register testControl
- Description
-
Test control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x001e007f
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
EWE |
|
|
Error write enable |
IT |
|
|
Interrupt test enable |
PT |
|
|
Memory parity test enable |
ET |
|
|
EDAC test enable |
reserved |
|
|
Reserved |
CB |
|
|
EDAC test checkbits |
Register uartChanARxTx
- Description
-
UART channel A receive/transmit register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
Data |
|
|
UART channel A receive/transmit data |
Register uartChanBRxTx
- Description
-
UART channel B receive/transmit register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
Data |
|
|
UART channel B receive/transmit data |
Register uartStatus
- Description
-
UART status register
- Reset value
-
0x00060006
- Warm reset mask
-
0x00f700f7
| Field | Mask | Reset | Description |
|---|---|---|---|
reserved |
|
|
Reserved |
CLB |
|
|
UART B clear |
OEB |
|
|
UART B overrun error |
PEB |
|
|
UART B parity error |
FEB |
|
|
UART B framing error |
reserved |
|
|
Reserved |
THEB |
|
|
UART B transmitter holding register empty |
TSEB |
|
|
UART B transmitter send register empty |
DRB |
|
|
UART B data ready |
reserved |
|
|
Reserved |
CL |
|
|
UART A clear |
OE |
|
|
UART A overrun error |
PE |
|
|
UART A parity error |
FE |
|
|
UART A framing error |
reserved |
|
|
Reserved |
THEA |
|
|
UART A transmitter holding register empty |
TSEA |
|
|
UART A transmitter send register empty |
DR |
|
|
UART A data ready |