GRLIB GRSPW2 Model

The Grspw2 model is part of the GRLIB IP library feature. It is available in the Grspw2 plugin.

Loading the Plugin

import Grspw2

Configuration

To work correctly, the device must be connected to an interrupt controller, a memory and another SpaceWire device.

There are several configuration parameters in the GrSpw2 device. These are summarized in the following table:

Name Description

config.infiniteSpeed

With this set, messages are sent immediately instead of being scheduled for the future based on the message length. This is the default option.

config.transmitter.frequency

Specify the SpaceWire transmitter frequency in Hz. Affects transfer speed when infinite speed is disabled.

config.transmitter.dataRate

SpaceWire port datarate: 1=single, 2=double, etc. Affects transfer speed when infinite speed is disabled.

config.dma.rxdescnum

Specifies the amount of rx description (0=128, 1=256, 2=512, 3=1024). This affect the regs.dmaRxDescTableAddr

config.dma.txdescnum

Specifies the amount of tx descriptors (0=64, 1=128, 2=256, 3=512). This affect the regs.dmaTxDescTableAddr

config.interrupt

Influences the interrupt that is raised with the IRQ controller (setting this property also updates the APB PnP info).

config.realCrcCheck

Set to use real crc check instead of packet crc flags. Real crc costs in terms of performance.

@Grspw2 Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @Grspw2

new

Create new instance of Grspw2

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

Grspw2 Reference

Properties

Name Type Description

CLKDIVColdResetValue

uint32_t

Clock divisor register

CLKDIVForcedBits

uint32_t

Clock divisor register

CLKDIVForcedFlippedBits

uint32_t

Clock divisor register

CLKDIVReadMask

uint32_t

Clock divisor register

CLKDIVResetMask

uint32_t

Clock divisor register

CLKDIVResetValue

uint32_t

Clock divisor register

CLKDIVWriteMask

uint32_t

Clock divisor register

CTRLColdResetValue

uint32_t

Control register

CTRLForcedBits

uint32_t

Control register

CTRLForcedFlippedBits

uint32_t

Control register

CTRLReadMask

uint32_t

Control register

CTRLResetMask

uint32_t

Control register

CTRLResetValue

uint32_t

Control register

CTRLWriteMask

uint32_t

Control register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DEFADDRColdResetValue

uint32_t

Node address register

DEFADDRForcedBits

uint32_t

Node address register

DEFADDRForcedFlippedBits

uint32_t

Node address register

DEFADDRReadMask

uint32_t

Node address register

DEFADDRResetMask

uint32_t

Node address register

DEFADDRResetValue

uint32_t

Node address register

DEFADDRWriteMask

uint32_t

Node address register

DKEYColdResetValue

uint32_t

Destination key register

DKEYForcedBits

uint32_t

Destination key register

DKEYForcedFlippedBits

uint32_t

Destination key register

DKEYReadMask

uint32_t

Destination key register

DKEYResetMask

uint32_t

Destination key register

DKEYResetValue

uint32_t

Destination key register

DKEYWriteMask

uint32_t

Destination key register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

STSColdResetValue

uint32_t

Status / interrupt-source register

STSForcedBits

uint32_t

Status / interrupt-source register

STSForcedFlippedBits

uint32_t

Status / interrupt-source register

STSReadMask

uint32_t

Status / interrupt-source register

STSResetMask

uint32_t

Status / interrupt-source register

STSResetValue

uint32_t

Status / interrupt-source register

STSWriteMask

uint32_t

Status / interrupt-source register

TCColdResetValue

uint32_t

Time register

TCForcedBits

uint32_t

Time register

TCForcedFlippedBits

uint32_t

Time register

TCReadMask

uint32_t

Time register

TCResetMask

uint32_t

Time register

TCResetValue

uint32_t

Time register

TCWriteMask

uint32_t

Time register

TimeSource

*void

Time source object

config.dma.rxdescnum

uint8_t

Number of rx descriptors

config.dma.txdescnum

uint8_t

Number of tx descriptors

config.infiniteSpeed

uint8_t

Set to use infinite speed for transfers.

config.interrupt

uint8_t

The interrupt index

config.realCrcCheck

uint8_t

Set to use real crc check instead of packet crc flags

config.transmitter.dataRate

uint8_t

SpaceWire port datarate: 1=single, 2=double,…​

config.transmitter.frequency

uint32_t

SpaceWire transmitter frequency in Hz

internal.linkState

int32_t

Link state

internal.txCurrChan

uint8_t

Channel scheduled for transmission

internal.txDAddr

uint32_t

Data address for the scheduled dma engine transfer

internal.txDLength

uint32_t

Data length for the scheduled dma engine transfer

internal.txFlags

uint32_t

Flags for the scheduled dma engine transfer

internal.txHAddr

uint32_t

Header address for the scheduled dma engine transfer

internal.txType

uint8_t

Scheduled transmission type (dma engine/rmap)

internal.uplinkNsPerByte

uint32_t

Transmitter speed

irqCtrl

temu_IfaceRef/ <unknown>

Irq controller

memAccess

temu_IfaceRef/ <unknown>

Memory used for DMA accesses

pnp.bar

uint32_t

Pnp BAR

pnp.config

uint32_t

Pnp configuration

regs.clockDiv

uint32_t

Clock divisor register

regs.control

uint32_t

Control register

regs.destKey

uint32_t

Destination key register

regs.dmaAddr

[uint32_t; 4]

DMA address register

regs.dmaControl

[uint32_t; 4]

DMA control/status register

regs.dmaRxDescTableAddr

[uint32_t; 4]

DMA receive descriptor table address register

regs.dmaRxMaxLen

[uint32_t; 4]

DMA RX maximum length register

regs.dmaTxDescTableAddr

[uint32_t; 4]

DMA transmit descriptor table address register

regs.nodeAddress

uint32_t

Node address register

regs.statusIrqSrc

uint32_t

Status / interrupt-source register

regs.time

uint32_t

Time register

spwUplink

[temu_IfaceRef; 2]/ <unknown>

SpaceWire devices connected to the port

Interfaces

Name Type Description

ApbIface

ApbIface

Apb interface

DeviceIface

DeviceIface

Device interface

MemAccessIface

MemAccessIface

Memory Access Interface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

SpwPortIface

SpwPortIface

SpaceWire ports interfaces

Registers

Register support is currently experimental!

Register Bank Regs

Register CTRL
Description

Control register

Reset value

0xc8000000

Warm reset mask

0xfc033f7f

Diagram
Field Mask Reset Description

RA

0x80000000

0x1

RMAP available

RX

0x40000000

0x1

RX unaligned access

RC

0x20000000

0x0

RMAP CRC available

NCH

0x18000000

0x1

Number of DMA channels minus one

PO

0x04000000

0x0

Number of ports minus one

RD

0x00020000

0x0

RMAP buffer disable

RE

0x00010000

0x0

RMAP enable

TL

0x00002000

0x0

Transmitter enable lock control

TF

0x00001000

0x0

Time-code control flag filter

TR

0x00000800

0x0

Time RX enable

TT

0x00000400

0x0

Time TX enable

LI

0x00000200

0x0

Link error IRQ

TQ

0x00000100

0x0

Tick-out IRQ

RS

0x00000040

0x0

Reset

PM

0x00000020

0x0

Promiscuous mode

TI

0x00000010

0x0

Tick in

IE

0x00000008

0x0

Interrupt enable

AS

0x00000004

0x0

Autostart

LS

0x00000002

0x0

Link start

LD

0x00000001

0x0

Link disable
Register STS
Description

Status / interrupt-source register

Reset value

0x00000000

Warm reset mask

0x0f000000

Diagram
Field Mask Reset Description

NRXD

0x0c000000

0x0

Number of receive descriptors

NTXD

0x03000000

0x0

Number of transmit descriptors

EE

0x00000100

-

Early EOP/EEP

IA

0x00000080

-

Invalid address

PE

0x00000010

-

Parity error

DE

0x00000008

-

Disconnect error

ER

0x00000004

-

Escape error

CE

0x00000002

-

Credit error

TO

0x00000001

-

Tick out
Register DEFADDR
Description

Node address register

Reset value

0x000000fe

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

DEFMASK

0x0000ff00

0x0

Default mask

DEFADDR

0x000000ff

0xfe

Default address
Register CLKDIV
Description

Clock divisor register

Reset value

0x00002727

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

CLKDIVSTART

0x0000ff00

0x27

Clock divisor startup

CLKDIVRUN

0x000000ff

0x27

Clock divisor run
Register DKEY
Description

Destination key register

Reset value

0x00000000

Warm reset mask

0x000000ff

Diagram
Field Mask Reset Description

DESTKEY

0x000000ff

0x0

Destination key
Register TC
Description

Time register

Reset value

0x00000000

Warm reset mask

0x000000ff

Diagram
Field Mask Reset Description

TCTRL

0x000000c0

0x0

Time control flags

TIMECNT

0x0000003f

0x0

Time counter
Register DMACTRL
Description

DMA control/status register

Reset value

0x00000000

Warm reset mask

0x0001fe1f

Diagram
Field Mask Reset Description

EP

0x00800000

-

EEP termination

TR

0x00400000

-

Truncated

RP

0x00080000

-

Receive packet IRQ

TP

0x00040000

-

Transmit packet IRQ

TL

0x00020000

-

Transmitter enable lock

LE

0x00010000

0x0

Link error disable

SP

0x00008000

0x0

Strip PID

SA

0x00004000

0x0

Strip address

EN

0x00002000

0x0

Enable address

NS

0x00001000

0x0

No spill

RD

0x00000800

0x0

RX descriptors available

RX

0x00000400

0x0

RX active

AT

0x00000200

0x0

Abort TX

RA

0x00000100

-

RX AHB error

TA

0x00000080

-

TX AHB error

PR

0x00000040

-

Packet received

PS

0x00000020

-

Packet sent

AI

0x00000010

0x0

AHB error interrupt

RI

0x00000008

0x0

Receive interrupt

TI

0x00000004

0x0

Transmit interrupt

RE

0x00000002

0x0

Receiver enable

TE

0x00000001

0x0

Transmitter enable
Register DMACTRL
Description

DMA control/status register

Reset value

0x00000000

Warm reset mask

0x0001fe1f

Diagram
Field Mask Reset Description

EP

0x00800000

-

EEP termination

TR

0x00400000

-

Truncated

RP

0x00080000

-

Receive packet IRQ

TP

0x00040000

-

Transmit packet IRQ

TL

0x00020000

-

Transmitter enable lock

LE

0x00010000

0x0

Link error disable

SP

0x00008000

0x0

Strip PID

SA

0x00004000

0x0

Strip address

EN

0x00002000

0x0

Enable address

NS

0x00001000

0x0

No spill

RD

0x00000800

0x0

RX descriptors available

RX

0x00000400

0x0

RX active

AT

0x00000200

0x0

Abort TX

RA

0x00000100

-

RX AHB error

TA

0x00000080

-

TX AHB error

PR

0x00000040

-

Packet received

PS

0x00000020

-

Packet sent

AI

0x00000010

0x0

AHB error interrupt

RI

0x00000008

0x0

Receive interrupt

TI

0x00000004

0x0

Transmit interrupt

RE

0x00000002

0x0

Receiver enable

TE

0x00000001

0x0

Transmitter enable
Register DMACTRL
Description

DMA control/status register

Reset value

0x00000000

Warm reset mask

0x0001fe1f

Diagram
Field Mask Reset Description

EP

0x00800000

-

EEP termination

TR

0x00400000

-

Truncated

RP

0x00080000

-

Receive packet IRQ

TP

0x00040000

-

Transmit packet IRQ

TL

0x00020000

-

Transmitter enable lock

LE

0x00010000

0x0

Link error disable

SP

0x00008000

0x0

Strip PID

SA

0x00004000

0x0

Strip address

EN

0x00002000

0x0

Enable address

NS

0x00001000

0x0

No spill

RD

0x00000800

0x0

RX descriptors available

RX

0x00000400

0x0

RX active

AT

0x00000200

0x0

Abort TX

RA

0x00000100

-

RX AHB error

TA

0x00000080

-

TX AHB error

PR

0x00000040

-

Packet received

PS

0x00000020

-

Packet sent

AI

0x00000010

0x0

AHB error interrupt

RI

0x00000008

0x0

Receive interrupt

TI

0x00000004

0x0

Transmit interrupt

RE

0x00000002

0x0

Receiver enable

TE

0x00000001

0x0

Transmitter enable
Register DMACTRL
Description

DMA control/status register

Reset value

0x00000000

Warm reset mask

0x0001fe1f

Diagram
Field Mask Reset Description

EP

0x00800000

-

EEP termination

TR

0x00400000

-

Truncated

RP

0x00080000

-

Receive packet IRQ

TP

0x00040000

-

Transmit packet IRQ

TL

0x00020000

-

Transmitter enable lock

LE

0x00010000

0x0

Link error disable

SP

0x00008000

0x0

Strip PID

SA

0x00004000

0x0

Strip address

EN

0x00002000

0x0

Enable address

NS

0x00001000

0x0

No spill

RD

0x00000800

0x0

RX descriptors available

RX

0x00000400

0x0

RX active

AT

0x00000200

0x0

Abort TX

RA

0x00000100

-

RX AHB error

TA

0x00000080

-

TX AHB error

PR

0x00000040

-

Packet received

PS

0x00000020

-

Packet sent

AI

0x00000010

0x0

AHB error interrupt

RI

0x00000008

0x0

Receive interrupt

TI

0x00000004

0x0

Transmit interrupt

RE

0x00000002

0x0

Receiver enable

TE

0x00000001

0x0

Transmitter enable
Register DMAMAXLEN
Description

DMA RX maximum length register

Reset value

0x00000000

Warm reset mask

0x01fffffc

Diagram
Field Mask Reset Description

RXMAXLEN

0x01fffffc

0x0

RX maximum length
Register DMAMAXLEN
Description

DMA RX maximum length register

Reset value

0x00000000

Warm reset mask

0x01fffffc

Diagram
Field Mask Reset Description

RXMAXLEN

0x01fffffc

0x0

RX maximum length
Register DMAMAXLEN
Description

DMA RX maximum length register

Reset value

0x00000000

Warm reset mask

0x01fffffc

Diagram
Field Mask Reset Description

RXMAXLEN

0x01fffffc

0x0

RX maximum length
Register DMAMAXLEN
Description

DMA RX maximum length register

Reset value

0x00000000

Warm reset mask

0x01fffffc

Diagram
Field Mask Reset Description

RXMAXLEN

0x01fffffc

0x0

RX maximum length
Register DMATXDESC
Description

DMA transmit descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff0

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f0

0x0

Descriptor selector
Register DMATXDESC
Description

DMA transmit descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff0

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f0

0x0

Descriptor selector
Register DMATXDESC
Description

DMA transmit descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff0

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f0

0x0

Descriptor selector
Register DMATXDESC
Description

DMA transmit descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff0

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f0

0x0

Descriptor selector
Register DMARXDESC
Description

DMA receive descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff8

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f8

0x0

Descriptor selector
Register DMARXDESC
Description

DMA receive descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff8

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f8

0x0

Descriptor selector
Register DMARXDESC
Description

DMA receive descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff8

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f8

0x0

Descriptor selector
Register DMARXDESC
Description

DMA receive descriptor table address register

Reset value

0x00000000

Warm reset mask

0xfffffff8

Diagram
Field Mask Reset Description

DESCBASEADDR

0xfffffc00

0x0

Descriptor table base address

DESCSEL

0x000003f8

0x0

Descriptor selector
Register DMAADDR
Description

DMA address register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

MASK

0x0000ff00

0x0

Mask

ADDR

0x000000ff

0x0

Address
Register DMAADDR
Description

DMA address register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

MASK

0x0000ff00

0x0

Mask

ADDR

0x000000ff

0x0

Address
Register DMAADDR
Description

DMA address register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

MASK

0x0000ff00

0x0

Mask

ADDR

0x000000ff

0x0

Address
Register DMAADDR
Description

DMA address register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

MASK

0x0000ff00

0x0

Mask

ADDR

0x000000ff

0x0

Address

Commands

Name Description

delete

Dispose instance of Grspw2

Limitations

The following deviations from real hardware are known to exist with this model:

  • The device already provides two ports, dual port is not yet implemented. Let us know if you need this feature implemented.

  • The link interface currently effectively uses only ErrorReset, Ready, Connecting and Run states. These are the only values that will be visible on the status register.

  • RMAPEN and PNPEN signals not available.

Examples

This example shows how to create two Grspw2 devices and connect them:

Creating and Connecting GRSPW2 Devices
import BusModels
import TEMUGrspw2
Grspw2.new name=grspw0
Grspw2.new name=grspw1
spw-connect port1=grspw0:SpwPortIface[0] port2=grspw1:SpwPortIface[0]