GRLIB IRQMP Model

The IrqMP is part of the GRLIB device library from Gaisler. It is a multiprocessor capable interrupt controller.

The controller supports routing interrupts to different processor cores and broadcasted interrupts.

Loading the Plugin

import IrqMp

Configuration

config.nCpu

Number of processors supported.

config.enExtIrq

Enable extended IRQs.

pnp.config

Plug and play configuration word for APB plug-and-play.

cpu

Up to 16 CPUs supported. IfaceRef property should be connected to the different CPUs.

@IrqMp Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @IrqMp

new

Create new instance of IrqMp

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

IrqMp Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

bootAddress

[uint32_t; 16]

broadcast

uint32_t

config.bootReg

uint8_t

Enable boot address registers

config.enExtIrq

uint8_t

config.irqMapping

uint8_t

Enable interrupt mapping

config.logInterrupts

uint8_t

config.nCpu

uint8_t

config.traceReads

uint8_t

config.traceWrites

uint8_t

cpu

[temu_IfaceRef; 16]/ <unknown>

Processors

extIntAck

[uint32_t; 16]

force

[uint32_t; 16]

interruptMap

[uint32_t; 8]

irqClear

uint32_t

irqCtrl

[temu_IfaceRef; 16]/ <unknown>

Upstream interrupt controllers (e.g. processor)

irqForce0

uint32_t

irqLevel

uint32_t

irqPending

uint32_t

irqSignalStatus

[uint16_t; 16]

mask

[uint32_t; 16]

mpStatus

uint32_t

pnp.bar

uint32_t

pnp.config

uint32_t

Interfaces

Name Type Description

ApbIface

ApbIface

DeviceIface

DeviceIface

IrqClientIface

IrqClientIface

uptree interrupt handlers (e.g. CPUs)

IrqIface

IrqCtrlIface

MemAccessIface

MemAccessIface

ResetIface

ResetIface

Ports

Prop Iface Description

irqCtrl

IrqClientIface

irq port

Registers

Register support is currently experimental!

Register Bank default

Register bootAddress
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register broadcast
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register extIntAck
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register force
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register interruptMap
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register irqClear
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register irqForce0
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register irqLevel
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register irqPending
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register mask
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-
Register mpStatus
Description
Reset value

0x00000000

Warm reset mask

0x00000000

Field Mask Reset Description

-

-

-

-

Commands

Name Description

delete

Dispose instance of IrqMp

raiseExternalIrq

Raise interrupt

Command raiseExternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number

Limitations

The following deviations from real hardware are known to exist with this model:

  • Broadcasted interrupts are broadcasted at the current time to all CPUs. If it was triggered by a non-synchronized event, the interrupt is raised at different times on the different cores. Consider the IRQ frequency and the configured quanta length.