Configuration
Interrupt Delivery
Set the irqControl property to point out the processor’s irq interface. The model will deliver normal SPARC interrupts (1 up to 15). The LEON2 also exports the IrqCtrlIface as IrqIface. IrqClientIface should be wired from the CPU the LEON2 model is connected to.
The IrqIface enables the use of external interrupts using the raise and lower functions. The LEON2 has 8 external IRQs mapped according to the following table (the mappings cannot be customised at present):
| External | Internal (Sparc IRL) |
|---|---|
0 |
4 |
1 |
5 |
2 |
6 |
3 |
7 |
4 |
10 |
5 |
12 |
6 |
13 |
7 |
15 |
The rules for IRQ raising is controlled by the GPIO IRQ config registers (it is also possible to raise IRQs by setting and lowering GPIO pins).
UART Connections
The UARTs are connected to the destination using the uarta and uartb properties. For the remote end points, these should be connected to UartAIface and UartBIface.
Infinite UART Speed
The UARTs can run either at infinite speed, or at simulated real-time speed. This can be configured using the infiniteUartSpeed property. Set this property to non-zero to enable infinite UART speed.
Note that this controls the speed of both UARTs.
When infinite speed is enabled, bytes are emitted to the destination serial device as soon as they have been written by the OBSW.
GPIO
The GPIO support in the LEON2 model supports interrupt generation using the GPIO interface instead of the IRQ controller interface. Model implements both the GpioClientIface and a property with a GpioBusIface reference (called gpioBus). The GPIO bus connection is not mandatory to set. If it is set, writes to the GPIO data register’s out bits will be forwarded over the GPIO port. Note that the LEON2 only have 16 GPIO pins.
Both the legacy multipin GpioBusIface and the new single pin SignalIface are supported. The model will prioritise the legacy interface for backwards compatibility. If you wish to use the SignalIface interface you should not set the gpioBus property.
Caches
The LEON2 SoC can act as a cache controller. That means that a cache model can notify the SoC about when it starts an evict/flush operation. The controller will also notify any connected caches about enabling, disabling and freezing events happening.
The cache parameters in the cache control register and the product configuration register are set automatically when connecting the dCache and iCache interface references to conforming objects.
| When connecting the cache references, make sure the caches are configured before they are connected. |
The caches that these interface references are connected to should normally be compliant with the supported LEON2 cache parameters. That is, there is a limitation on the sizes, lines and ways.
While the model does a best effort in trying to report errors when a miss-configured cache model is supplied, take care to ensure that the model is correctly configured.
@Leon2SoC Reference
Leon2SoC Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
TimeSource |
*void |
Time source object |
ahbfailaddr |
uint32_t |
Fail address register |
ahbstat |
uint32_t |
Fail status register |
behaviour |
uint8_t |
Set to 1 for COLE mode |
cachectrl |
uint32_t |
Cache control register |
config.levelMask |
uint32_t |
Level triggered internal interrupts (mask) |
config.logInterrupts |
uint8_t |
Enable interrupt logging |
cpu |
temu_IfaceRef/ <unknown> |
CPU to control with powerdown |
dCache |
temu_IfaceRef/ <unknown> |
Data cache (optional) |
gpioBus |
temu_IfaceRef/ <unknown> |
GPIO bus (deprecated, use signal interface instead) |
gpioIrqLevel |
uint32_t |
|
gpioIrqMask |
uint32_t |
|
gpioIrqPolarity |
uint32_t |
|
gpiodir |
uint32_t |
I/O port direction register |
gpioinout |
uint32_t |
I/O port data register |
gpioirqcfg |
uint32_t |
I/O port interrupt register 1 |
gpioirqcfg2 |
uint32_t |
I/O port interrupt register 2 |
iCache |
temu_IfaceRef/ <unknown> |
Instruction cache (optional) |
infiniteUartSpeed |
uint32_t |
|
inputBits |
uint32_t |
Input signals |
irqControl |
temu_IfaceRef/ <unknown> |
Next level IRQ controller object (e.g. CPU) |
irqSignalStatus |
uint16_t |
Interrupt signal status (should be the same as pending in CPU) |
irqclear |
uint32_t |
Interrupt clear register |
irqforce |
uint32_t |
Interrupt force register |
irqmask |
uint32_t |
Interrupt mask and priority register |
irqpend |
uint32_t |
Interrupt pending register |
leoncfg |
uint32_t |
Product configuration register |
memcfg1 |
uint32_t |
Memory configuration register 1 |
memcfg2 |
uint32_t |
Memory configuration register 2 |
memcfg3 |
uint32_t |
Memory configuration register 3 |
memcfg4 |
uint32_t |
Memory configuration 4 (COLE) |
memcfg5 |
uint32_t |
Memory configuration 5 (COLE) |
mr |
uint32_t |
Map register (COLE) |
outSignals |
[temu_IfaceRef; 16]/ <unknown> |
Outgoing GPIO signals |
powerdown |
uint32_t |
Idle register |
presccntr |
uint32_t |
Prescaler counter register |
prescrld |
uint32_t |
Prescaler reload register |
timer1cntr |
uint32_t |
Timer 1 counter register |
timer1ctrl |
uint32_t |
Timer 1 control register |
timer1rld |
uint32_t |
Timer 1 reload register |
timer2cntr |
uint32_t |
Timer 2 counter register |
timer2ctrl |
uint32_t |
Timer 2 control register |
timer2rld |
uint32_t |
Timer 2 reload register |
uart1DatTxHold |
uint32_t |
UART1 data TX hold register |
uart1DatTxShift |
uint32_t |
UART 1 data TX shift |
uart1ctrl |
uint32_t |
UART 1 control register |
uart1datrx |
uint32_t |
UART 1 RX data register |
uart1scal |
uint32_t |
UART 1 scaler register |
uart1stat |
uint32_t |
UART 1 status register |
uart2DatTxHold |
uint32_t |
|
uart2DatTxShift |
uint32_t |
|
uart2ctrl |
uint32_t |
UART 2 control register |
uart2datrx |
uint32_t |
UART 1 RX data register |
uart2scal |
uint32_t |
UART 2 scaler register |
uart2stat |
uint32_t |
UART 2 status register |
uarta |
temu_IfaceRef/ <unknown> |
Serial port A |
uartb |
temu_IfaceRef/ <unknown> |
Serial port B |
watchdog |
uint32_t |
Watchdog register |
writeprot1 |
uint32_t |
Write protection register 1 |
writeprot2 |
uint32_t |
Write protection register 2 |
writeprotstart1 |
uint32_t |
Write protection start address 1 |
writeprotstart2 |
uint32_t |
Write protection start address 2 |
writeprotstop1 |
uint32_t |
Write protection end address 1 |
writeprotstop2 |
uint32_t |
Write protection end address 2 |
Interfaces
| Name | Type | Description |
|---|---|---|
DCacheCtrlIface |
temu::CacheCtrlIface |
D-cache to control |
DeviceIface |
DeviceIface |
|
GpioClientIface |
GpioClientIface |
|
ICacheCtrlIface |
temu::CacheCtrlIface |
I-cache to control |
InternalIrqIface |
IrqCtrlIface |
Internal IRQ controller (native LEON numbering), post your IRQs here. |
IrqClientIface |
IrqClientIface |
IRQ acknowledgement (from CPU) |
IrqIface |
IrqCtrlIface |
External IRQ controller, post your IRQs here. |
MemAccessIface |
MemAccessIface |
|
RegisterIface |
temu::RegisterIface |
Register introspection interface |
ResetIface |
ResetIface |
|
SignalIface |
SignalIface |
Incomming signals |
UartAIface |
SerialIface |
UART A |
UartBIface |
SerialIface |
UART B |
Ports
| Prop | Iface | Description |
|---|---|---|
irqControl |
IrqClientIface |
Interrupt |
uarta |
UartAIface |
uart a |
uartb |
UartBIface |
uart b |
Registers
| Register support is currently experimental! |
Register Bank registers
Register ahbfailaddr
- Description
-
Fail address register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register ahbstat
- Description
-
Fail status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
eed |
|
|
EDAC-correctable error detected |
hed |
|
|
Hardware error detected |
het |
|
|
Hardware error type |
hem |
|
|
Hardware error module |
hes |
|
|
Hardware error size |
Register cachectrl
- Description
-
Cache control register
- Reset value
-
0xfd178000
- Warm reset mask
-
0x00f9c00f
| Field | Mask | Reset | Description |
|---|---|---|---|
drepl |
|
|
Data cache replacement policy |
irepl |
|
|
Instruction cache replacement policy |
isets |
|
|
Instruction cache associativity |
dsets |
|
|
Data cache associativity |
ds |
|
|
Data cache snoop enable |
fd |
|
|
Flush data cache |
fi |
|
|
Flush instruction cache |
cpc |
|
|
Cache parity bits |
cptb |
|
|
Cache parity test bits |
ib |
|
|
Instruction burst fetch |
ip |
|
|
Instruction cache flush pending |
dp |
|
|
Data cache flush pending |
ite |
|
|
Instruction cache tag error counter |
ide |
|
|
Instruction cache data error counter |
dte |
|
|
Data cache tag error counter |
dde |
|
|
Data cache data error counter |
df |
|
|
Data cache freeze on interrupt |
if |
|
|
Instruction cache freeze on interrupt |
dcs |
|
|
Data cache state |
ics |
|
|
Instruction cache state |
Register gpiodir
- Description
-
I/O port direction register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register gpioinout
- Description
-
I/O port data register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register gpioirqcfg
- Description
-
I/O port interrupt register 1
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register gpioirqcfg2
- Description
-
I/O port interrupt register 2
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register irqclear
- Description
-
Interrupt clear register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register irqforce
- Description
-
Interrupt force register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register irqmask
- Description
-
Interrupt mask and priority register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000fffe
| Field | Mask | Reset | Description |
|---|---|---|---|
ilevel_io7 |
|
|
Interrupt level |
ilevel_pci |
|
|
Interrupt level |
ilevel_io6 |
|
|
Interrupt level |
ilevel_io5 |
|
|
Interrupt level |
ilevel_dsu |
|
|
Interrupt level |
ilevel_io4 |
|
|
Interrupt level |
ilevel_timer2 |
|
|
Interrupt level |
ilevel_timer1 |
|
|
Interrupt level |
ilevel_io3 |
|
|
Interrupt level |
ilevel_io2 |
|
|
Interrupt level |
ilevel_io1 |
|
|
Interrupt level |
ilevel_io0 |
|
|
Interrupt level |
ilevel_uart1 |
|
|
Interrupt level |
ilevel_uart2 |
|
|
Interrupt level |
ilevel_amba |
|
|
Interrupt level |
imask_io7 |
|
|
Interrupt mask |
imask_pci |
|
|
Interrupt mask |
imask_io6 |
|
|
Interrupt mask |
imask_io5 |
|
|
Interrupt mask |
imask_dsu |
|
|
Interrupt mask |
imask_io4 |
|
|
Interrupt mask |
imask_timer2 |
|
|
Interrupt mask |
imask_timer1 |
|
|
Interrupt mask |
imask_io3 |
|
|
Interrupt mask |
imask_io2 |
|
|
Interrupt mask |
imask_io1 |
|
|
Interrupt mask |
imask_io0 |
|
|
Interrupt mask |
imask_uart1 |
|
|
Interrupt mask |
imask_uart2 |
|
|
Interrupt mask |
imask_amba |
|
|
Interrupt mask |
Register irqpend
- Description
-
Interrupt pending register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register leoncfg
- Description
-
Product configuration register
- Reset value
-
0x7077bbd5
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
mmu |
|
|
Memory management unit |
dsu |
|
|
Debug support unit |
sdrctrl |
|
|
SDRAM controller |
wtpnb |
|
|
IU watchpoints |
imac |
|
|
UMAC/SMAC instructions |
nwin |
|
|
IU register file windows |
icsz |
|
|
Instruction cache set size |
ilsz |
|
|
Instruction cache line size |
dcsz |
|
|
Data cache set size |
dlsz |
|
|
Data cache line size |
divinst |
|
|
UDIV/SDIV instructions |
mulinst |
|
|
UMUL/SMUL instructions |
wdog |
|
|
Watchdog |
memstat |
|
|
Memory status and address failing register |
fpu |
|
|
FPU type |
pci |
|
|
PCI core type |
wprt |
|
|
Write protections |
Register memcfg1
- Description
-
Memory configuration register 1
- Reset value
-
0x000000ff
- Warm reset mask
-
0x7ef80bff
| Field | Mask | Reset | Description |
|---|---|---|---|
pbrdy |
|
|
PROM area bus-ready enable |
abrdy |
|
|
Asynchronous bus ready |
iowdh |
|
|
I/O bus width |
iobrdy |
|
|
I/O area bus ready enable |
bexc |
|
|
Bus error enable for RAM PROM and I/O access |
iows |
|
|
I/O waitstates |
ioen |
|
|
I/O area enable |
prwen |
|
|
PROM write enable |
prwdh |
|
|
PROM width |
prwws |
|
|
PROM write waitstates |
prrws |
|
|
PROM read waitstates |
Register memcfg2
- Description
-
Memory configuration register 2
- Reset value
-
0x7c400020
- Warm reset mask
-
0xfff86000
| Field | Mask | Reset | Description |
|---|---|---|---|
sdrref |
|
|
SDRAM refresh |
trp |
|
|
SDRAM t_rp timing |
trfc |
|
|
SDRAM t_rfp timing |
sdrcas |
|
|
SDRAM CAS delay |
sdrbs |
|
|
SDRAM bank size |
sdrcls |
|
|
SDRAM column size |
sdrcmd |
|
|
SDRAM command |
se |
|
|
SDRAM enable |
si |
|
|
SDRAM disable |
rambs |
|
|
SRAM bank size |
rambrdy |
|
|
SRAM area bus ready enable |
ramrmw |
|
|
SRAM read-modify-write |
ramwdh |
|
|
SRAM bus width |
ramwws |
|
|
SRAM write waitstates |
ramrws |
|
|
SRAM read waitstates |
Register memcfg3
- Description
-
Memory configuration register 3
- Reset value
-
0xc8000000
- Warm reset mask
-
0xc8000c00
| Field | Mask | Reset | Description |
|---|---|---|---|
rfc |
|
|
Register file checkbits |
me |
|
|
Memory EDAC |
srcrv |
|
|
SDRAM refresh counter reload value |
wb |
|
|
EDAC diagnostic write bypass |
rb |
|
|
EDAC diagnostic read |
re |
|
|
RAM EDAC enable |
pe |
|
|
PROM EDAC enable |
tcb |
|
|
Test checkbits |
Register powerdown
- Description
-
Idle register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register presccntr
- Description
-
Prescaler counter register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000003ff
| Field | Mask | Reset | Description |
|---|---|---|---|
cnt |
|
|
Prescaler counter value |
Register prescrld
- Description
-
Prescaler reload register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000003ff
| Field | Mask | Reset | Description |
|---|---|---|---|
rv |
|
|
Prescaler reload value |
Register timer1cntr
- Description
-
Timer 1 counter register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register timer1ctrl
- Description
-
Timer 1 control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
ld |
|
|
Load counter |
rl |
|
|
Reload counter |
en |
|
|
Enable counter |
Register timer1rld
- Description
-
Timer 1 reload register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register timer2cntr
- Description
-
Timer 2 counter register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register timer2ctrl
- Description
-
Timer 2 control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
ld |
|
|
Load counter |
rl |
|
|
Reload counter |
en |
|
|
Enable counter |
Register timer2rld
- Description
-
Timer 2 reload register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register uart1ctrl
- Description
-
UART 1 control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000143
| Field | Mask | Reset | Description |
|---|---|---|---|
ec |
|
|
External clock |
lb |
|
|
Loop back |
fl |
|
|
Flow control |
pe |
|
|
Parity enable |
ps |
|
|
Parity select |
ti |
|
|
Transmitter interrupt enable |
ri |
|
|
Receiver interrupt enable |
te |
|
|
Transmitter enable |
re |
|
|
Receiver enable |
Register uart1datrx
- Description
-
UART 1 RX data register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
rtd |
|
|
Received/transmit data |
Register uart1scal
- Description
-
UART 1 scaler register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register uart1stat
- Description
-
UART 1 status register
- Reset value
-
0x00000006
- Warm reset mask
-
0x0000007f
| Field | Mask | Reset | Description |
|---|---|---|---|
fe |
|
|
Framing error |
pe |
|
|
Parity error |
ov |
|
|
Overrun |
br |
|
|
Break received |
th |
|
|
Transmitter hold register empty |
ts |
|
|
Transmitter shift register empty |
dr |
|
|
Data ready |
Register uart2ctrl
- Description
-
UART 2 control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000143
| Field | Mask | Reset | Description |
|---|---|---|---|
ec |
|
|
External clock |
lb |
|
|
Loop back |
fl |
|
|
Flow control |
pe |
|
|
Parity enable |
ps |
|
|
Parity select |
ti |
|
|
Transmitter interrupt enable |
ri |
|
|
Receiver interrupt enable |
te |
|
|
Transmitter enable |
re |
|
|
Receiver enable |
Register uart2datrx
- Description
-
UART 1 RX data register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
rtd |
|
|
Received/transmit data |
Register uart2scal
- Description
-
UART 2 scaler register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register uart2stat
- Description
-
UART 2 status register
- Reset value
-
0x00000006
- Warm reset mask
-
0x0000007f
| Field | Mask | Reset | Description |
|---|---|---|---|
fe |
|
|
Framing error |
pe |
|
|
Parity error |
ov |
|
|
Overrun |
br |
|
|
Break received |
th |
|
|
Transmitter hold register empty |
ts |
|
|
Transmitter shift register empty |
dr |
|
|
Data ready |
Register watchdog
- Description
-
Watchdog register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register writeprot1
- Description
-
Write protection register 1
- Reset value
-
0x00000000
- Warm reset mask
-
0x80000000
| Field | Mask | Reset | Description |
|---|---|---|---|
en |
|
|
Enable |
bp |
|
|
Block protect |
tag |
|
|
Address tag |
mask |
|
|
Address mask |
Register writeprot2
- Description
-
Write protection register 2
- Reset value
-
0x00000000
- Warm reset mask
-
0x80000000
| Field | Mask | Reset | Description |
|---|---|---|---|
en |
|
|
Enable |
bp |
|
|
Block protect |
tag |
|
|
Address tag |
mask |
|
|
Address mask |
Register writeprotstart1
- Description
-
Write protection start address 1
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
start |
|
|
Start address |
bp |
|
|
Block protect |
Register writeprotstart2
- Description
-
Write protection start address 2
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
start |
|
|
Start address |
bp |
|
|
Block protect |
