Configuration

Interrupt Delivery

Set the irqControl property to point out the processor’s irq interface. The model will deliver normal SPARC interrupts (1 up to 15). The LEON2 also exports the IrqCtrlIface as IrqIface. IrqClientIface should be wired from the CPU the LEON2 model is connected to.

The IrqIface enables the use of external interrupts using the raise and lower functions. The LEON2 has 8 external IRQs mapped according to the following table (the mappings cannot be customised at present):

Table 1. External to Internal IRQ Mapping
External Internal (Sparc IRL)

0

4

1

5

2

6

3

7

4

10

5

12

6

13

7

15

The rules for IRQ raising is controlled by the GPIO IRQ config registers (it is also possible to raise IRQs by setting and lowering GPIO pins).

UART Connections

The UARTs are connected to the destination using the uarta and uartb properties. For the remote end points, these should be connected to UartAIface and UartBIface.

Infinite UART Speed

The UARTs can run either at infinite speed, or at simulated real-time speed. This can be configured using the infiniteUartSpeed property. Set this property to non-zero to enable infinite UART speed.

Note that this controls the speed of both UARTs.

When infinite speed is enabled, bytes are emitted to the destination serial device as soon as they have been written by the OBSW.

GPIO

The GPIO support in the LEON2 model supports interrupt generation using the GPIO interface instead of the IRQ controller interface. Model implements both the GpioClientIface and a property with a GpioBusIface reference (called gpioBus). The GPIO bus connection is not mandatory to set. If it is set, writes to the GPIO data register’s out bits will be forwarded over the GPIO port. Note that the LEON2 only have 16 GPIO pins.

Both the legacy multipin GpioBusIface and the new single pin SignalIface are supported. The model will prioritise the legacy interface for backwards compatibility. If you wish to use the SignalIface interface you should not set the gpioBus property.

Caches

The LEON2 SoC can act as a cache controller. That means that a cache model can notify the SoC about when it starts an evict/flush operation. The controller will also notify any connected caches about enabling, disabling and freezing events happening.

The cache parameters in the cache control register and the product configuration register are set automatically when connecting the dCache and iCache interface references to conforming objects.

When connecting the cache references, make sure the caches are configured before they are connected.

The caches that these interface references are connected to should normally be compliant with the supported LEON2 cache parameters. That is, there is a limitation on the sizes, lines and ways.

While the model does a best effort in trying to report errors when a miss-configured cache model is supplied, take care to ensure that the model is correctly configured.

@Leon2SoC Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @Leon2SoC

new

Create new instance of Leon2SoC

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

Leon2SoC Reference

Properties

Name Type Description

CCRColdResetValue

uint32_t

Cache Control Register

CCRForcedBits

uint32_t

Cache Control Register

CCRForcedFlippedBits

uint32_t

Cache Control Register

CCRReadMask

uint32_t

Cache Control Register

CCRResetMask

uint32_t

Cache Control Register

CCRResetValue

uint32_t

Cache Control Register

CCRWriteMask

uint32_t

Cache Control Register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

FAILARColdResetValue

uint32_t

Fail Address Register

FAILARForcedBits

uint32_t

Fail Address Register

FAILARForcedFlippedBits

uint32_t

Fail Address Register

FAILARReadMask

uint32_t

Fail Address Register

FAILARResetMask

uint32_t

Fail Address Register

FAILARResetValue

uint32_t

Fail Address Register

FAILARWriteMask

uint32_t

Fail Address Register

FAILSRColdResetValue

uint32_t

Fail Status Register

FAILSRForcedBits

uint32_t

Fail Status Register

FAILSRForcedFlippedBits

uint32_t

Fail Status Register

FAILSRReadMask

uint32_t

Fail Status Register

FAILSRResetMask

uint32_t

Fail Status Register

FAILSRResetValue

uint32_t

Fail Status Register

FAILSRWriteMask

uint32_t

Fail Status Register

IDLEColdResetValue

uint32_t

Idle Register

IDLEForcedBits

uint32_t

Idle Register

IDLEForcedFlippedBits

uint32_t

Idle Register

IDLEReadMask

uint32_t

Idle Register

IDLEResetMask

uint32_t

Idle Register

IDLEResetValue

uint32_t

Idle Register

IDLEWriteMask

uint32_t

Idle Register

IODATColdResetValue

uint32_t

I/O Port Data Register

IODATForcedBits

uint32_t

I/O Port Data Register

IODATForcedFlippedBits

uint32_t

I/O Port Data Register

IODATReadMask

uint32_t

I/O Port Data Register

IODATResetMask

uint32_t

I/O Port Data Register

IODATResetValue

uint32_t

I/O Port Data Register

IODATWriteMask

uint32_t

I/O Port Data Register

IODIRColdResetValue

uint32_t

I/O Port Direction Register

IODIRForcedBits

uint32_t

I/O Port Direction Register

IODIRForcedFlippedBits

uint32_t

I/O Port Direction Register

IODIRReadMask

uint32_t

I/O Port Direction Register

IODIRResetMask

uint32_t

I/O Port Direction Register

IODIRResetValue

uint32_t

I/O Port Direction Register

IODIRWriteMask

uint32_t

I/O Port Direction Register

IOIT1ColdResetValue

uint32_t

I/O Port Interrupt Register 1

IOIT1ForcedBits

uint32_t

I/O Port Interrupt Register 1

IOIT1ForcedFlippedBits

uint32_t

I/O Port Interrupt Register 1

IOIT1ReadMask

uint32_t

I/O Port Interrupt Register 1

IOIT1ResetMask

uint32_t

I/O Port Interrupt Register 1

IOIT1ResetValue

uint32_t

I/O Port Interrupt Register 1

IOIT1WriteMask

uint32_t

I/O Port Interrupt Register 1

IOIT2ColdResetValue

uint32_t

I/O Port Interrupt Register 2

IOIT2ForcedBits

uint32_t

I/O Port Interrupt Register 2

IOIT2ForcedFlippedBits

uint32_t

I/O Port Interrupt Register 2

IOIT2ReadMask

uint32_t

I/O Port Interrupt Register 2

IOIT2ResetMask

uint32_t

I/O Port Interrupt Register 2

IOIT2ResetValue

uint32_t

I/O Port Interrupt Register 2

IOIT2WriteMask

uint32_t

I/O Port Interrupt Register 2

ITCColdResetValue

uint32_t

Interrupt Clear Register

ITCForcedBits

uint32_t

Interrupt Clear Register

ITCForcedFlippedBits

uint32_t

Interrupt Clear Register

ITCReadMask

uint32_t

Interrupt Clear Register

ITCResetMask

uint32_t

Interrupt Clear Register

ITCResetValue

uint32_t

Interrupt Clear Register

ITCWriteMask

uint32_t

Interrupt Clear Register

ITFColdResetValue

uint32_t

Interrupt Force Register

ITFForcedBits

uint32_t

Interrupt Force Register

ITFForcedFlippedBits

uint32_t

Interrupt Force Register

ITFReadMask

uint32_t

Interrupt Force Register

ITFResetMask

uint32_t

Interrupt Force Register

ITFResetValue

uint32_t

Interrupt Force Register

ITFWriteMask

uint32_t

Interrupt Force Register

ITMPColdResetValue

uint32_t

Interrupt Mask and Priority Register

ITMPForcedBits

uint32_t

Interrupt Mask and Priority Register

ITMPForcedFlippedBits

uint32_t

Interrupt Mask and Priority Register

ITMPReadMask

uint32_t

Interrupt Mask and Priority Register

ITMPResetMask

uint32_t

Interrupt Mask and Priority Register

ITMPResetValue

uint32_t

Interrupt Mask and Priority Register

ITMPWriteMask

uint32_t

Interrupt Mask and Priority Register

ITPColdResetValue

uint32_t

Interrupt Pending Register

ITPForcedBits

uint32_t

Interrupt Pending Register

ITPForcedFlippedBits

uint32_t

Interrupt Pending Register

ITPReadMask

uint32_t

Interrupt Pending Register

ITPResetMask

uint32_t

Interrupt Pending Register

ITPResetValue

uint32_t

Interrupt Pending Register

ITPWriteMask

uint32_t

Interrupt Pending Register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

MCFG1ColdResetValue

uint32_t

Memory Configuration Register 1

MCFG1ForcedBits

uint32_t

Memory Configuration Register 1

MCFG1ForcedFlippedBits

uint32_t

Memory Configuration Register 1

MCFG1ReadMask

uint32_t

Memory Configuration Register 1

MCFG1ResetMask

uint32_t

Memory Configuration Register 1

MCFG1ResetValue

uint32_t

Memory Configuration Register 1

MCFG1WriteMask

uint32_t

Memory Configuration Register 1

MCFG2ColdResetValue

uint32_t

Memory Configuration Register 2

MCFG2ForcedBits

uint32_t

Memory Configuration Register 2

MCFG2ForcedFlippedBits

uint32_t

Memory Configuration Register 2

MCFG2ReadMask

uint32_t

Memory Configuration Register 2

MCFG2ResetMask

uint32_t

Memory Configuration Register 2

MCFG2ResetValue

uint32_t

Memory Configuration Register 2

MCFG2WriteMask

uint32_t

Memory Configuration Register 2

MCFG3ColdResetValue

uint32_t

Memory Configuration Register 3

MCFG3ForcedBits

uint32_t

Memory Configuration Register 3

MCFG3ForcedFlippedBits

uint32_t

Memory Configuration Register 3

MCFG3ReadMask

uint32_t

Memory Configuration Register 3

MCFG3ResetMask

uint32_t

Memory Configuration Register 3

MCFG3ResetValue

uint32_t

Memory Configuration Register 3

MCFG3WriteMask

uint32_t

Memory Configuration Register 3

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

PCRColdResetValue

uint32_t

Product Configuration Register

PCRForcedBits

uint32_t

Product Configuration Register

PCRForcedFlippedBits

uint32_t

Product Configuration Register

PCRReadMask

uint32_t

Product Configuration Register

PCRResetMask

uint32_t

Product Configuration Register

PCRResetValue

uint32_t

Product Configuration Register

PCRWriteMask

uint32_t

Product Configuration Register

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

SCACColdResetValue

uint32_t

Prescaler Counter Register

SCACForcedBits

uint32_t

Prescaler Counter Register

SCACForcedFlippedBits

uint32_t

Prescaler Counter Register

SCACReadMask

uint32_t

Prescaler Counter Register

SCACResetMask

uint32_t

Prescaler Counter Register

SCACResetValue

uint32_t

Prescaler Counter Register

SCACWriteMask

uint32_t

Prescaler Counter Register

SCARColdResetValue

uint32_t

Prescaler Reload Register

SCARForcedBits

uint32_t

Prescaler Reload Register

SCARForcedFlippedBits

uint32_t

Prescaler Reload Register

SCARReadMask

uint32_t

Prescaler Reload Register

SCARResetMask

uint32_t

Prescaler Reload Register

SCARResetValue

uint32_t

Prescaler Reload Register

SCARWriteMask

uint32_t

Prescaler Reload Register

TIMC1ColdResetValue

uint32_t

Timer 1 Counter Register

TIMC1ForcedBits

uint32_t

Timer 1 Counter Register

TIMC1ForcedFlippedBits

uint32_t

Timer 1 Counter Register

TIMC1ReadMask

uint32_t

Timer 1 Counter Register

TIMC1ResetMask

uint32_t

Timer 1 Counter Register

TIMC1ResetValue

uint32_t

Timer 1 Counter Register

TIMC1WriteMask

uint32_t

Timer 1 Counter Register

TIMC2ColdResetValue

uint32_t

Timer 2 Counter Register

TIMC2ForcedBits

uint32_t

Timer 2 Counter Register

TIMC2ForcedFlippedBits

uint32_t

Timer 2 Counter Register

TIMC2ReadMask

uint32_t

Timer 2 Counter Register

TIMC2ResetMask

uint32_t

Timer 2 Counter Register

TIMC2ResetValue

uint32_t

Timer 2 Counter Register

TIMC2WriteMask

uint32_t

Timer 2 Counter Register

TIMCTR1ColdResetValue

uint32_t

Timer 1 Control Register

TIMCTR1ForcedBits

uint32_t

Timer 1 Control Register

TIMCTR1ForcedFlippedBits

uint32_t

Timer 1 Control Register

TIMCTR1ReadMask

uint32_t

Timer 1 Control Register

TIMCTR1ResetMask

uint32_t

Timer 1 Control Register

TIMCTR1ResetValue

uint32_t

Timer 1 Control Register

TIMCTR1WriteMask

uint32_t

Timer 1 Control Register

TIMCTR2ColdResetValue

uint32_t

Timer 2 Control Register

TIMCTR2ForcedBits

uint32_t

Timer 2 Control Register

TIMCTR2ForcedFlippedBits

uint32_t

Timer 2 Control Register

TIMCTR2ReadMask

uint32_t

Timer 2 Control Register

TIMCTR2ResetMask

uint32_t

Timer 2 Control Register

TIMCTR2ResetValue

uint32_t

Timer 2 Control Register

TIMCTR2WriteMask

uint32_t

Timer 2 Control Register

TIMR1ColdResetValue

uint32_t

Timer 1 Reload Register

TIMR1ForcedBits

uint32_t

Timer 1 Reload Register

TIMR1ForcedFlippedBits

uint32_t

Timer 1 Reload Register

TIMR1ReadMask

uint32_t

Timer 1 Reload Register

TIMR1ResetMask

uint32_t

Timer 1 Reload Register

TIMR1ResetValue

uint32_t

Timer 1 Reload Register

TIMR1WriteMask

uint32_t

Timer 1 Reload Register

TIMR2ColdResetValue

uint32_t

Timer 2 Reload Register

TIMR2ForcedBits

uint32_t

Timer 2 Reload Register

TIMR2ForcedFlippedBits

uint32_t

Timer 2 Reload Register

TIMR2ReadMask

uint32_t

Timer 2 Reload Register

TIMR2ResetMask

uint32_t

Timer 2 Reload Register

TIMR2ResetValue

uint32_t

Timer 2 Reload Register

TIMR2WriteMask

uint32_t

Timer 2 Reload Register

TimeSource

*void

Time source object

UAC1ColdResetValue

uint32_t

UART 1 Control Register

UAC1ForcedBits

uint32_t

UART 1 Control Register

UAC1ForcedFlippedBits

uint32_t

UART 1 Control Register

UAC1ReadMask

uint32_t

UART 1 Control Register

UAC1ResetMask

uint32_t

UART 1 Control Register

UAC1ResetValue

uint32_t

UART 1 Control Register

UAC1WriteMask

uint32_t

UART 1 Control Register

UAC2ColdResetValue

uint32_t

UART 2 Control Register

UAC2ForcedBits

uint32_t

UART 2 Control Register

UAC2ForcedFlippedBits

uint32_t

UART 2 Control Register

UAC2ReadMask

uint32_t

UART 2 Control Register

UAC2ResetMask

uint32_t

UART 2 Control Register

UAC2ResetValue

uint32_t

UART 2 Control Register

UAC2WriteMask

uint32_t

UART 2 Control Register

UAD1ColdResetValue

uint32_t

UART 1 Data Register

UAD1ForcedBits

uint32_t

UART 1 Data Register

UAD1ForcedFlippedBits

uint32_t

UART 1 Data Register

UAD1ReadMask

uint32_t

UART 1 Data Register

UAD1ResetMask

uint32_t

UART 1 Data Register

UAD1ResetValue

uint32_t

UART 1 Data Register

UAD1WriteMask

uint32_t

UART 1 Data Register

UAD2ColdResetValue

uint32_t

UART 2 Data Register

UAD2ForcedBits

uint32_t

UART 2 Data Register

UAD2ForcedFlippedBits

uint32_t

UART 2 Data Register

UAD2ReadMask

uint32_t

UART 2 Data Register

UAD2ResetMask

uint32_t

UART 2 Data Register

UAD2ResetValue

uint32_t

UART 2 Data Register

UAD2WriteMask

uint32_t

UART 2 Data Register

UAS1ColdResetValue

uint32_t

UART 1 Status Register

UAS1ForcedBits

uint32_t

UART 1 Status Register

UAS1ForcedFlippedBits

uint32_t

UART 1 Status Register

UAS1ReadMask

uint32_t

UART 1 Status Register

UAS1ResetMask

uint32_t

UART 1 Status Register

UAS1ResetValue

uint32_t

UART 1 Status Register

UAS1WriteMask

uint32_t

UART 1 Status Register

UAS2ColdResetValue

uint32_t

UART 2 Status Register

UAS2ForcedBits

uint32_t

UART 2 Status Register

UAS2ForcedFlippedBits

uint32_t

UART 2 Status Register

UAS2ReadMask

uint32_t

UART 2 Status Register

UAS2ResetMask

uint32_t

UART 2 Status Register

UAS2ResetValue

uint32_t

UART 2 Status Register

UAS2WriteMask

uint32_t

UART 2 Status Register

UASCA1ColdResetValue

uint32_t

UART 1 Scaler Register

UASCA1ForcedBits

uint32_t

UART 1 Scaler Register

UASCA1ForcedFlippedBits

uint32_t

UART 1 Scaler Register

UASCA1ReadMask

uint32_t

UART 1 Scaler Register

UASCA1ResetMask

uint32_t

UART 1 Scaler Register

UASCA1ResetValue

uint32_t

UART 1 Scaler Register

UASCA1WriteMask

uint32_t

UART 1 Scaler Register

UASCA2ColdResetValue

uint32_t

UART 2 Scaler Register

UASCA2ForcedBits

uint32_t

UART 2 Scaler Register

UASCA2ForcedFlippedBits

uint32_t

UART 2 Scaler Register

UASCA2ReadMask

uint32_t

UART 2 Scaler Register

UASCA2ResetMask

uint32_t

UART 2 Scaler Register

UASCA2ResetValue

uint32_t

UART 2 Scaler Register

UASCA2WriteMask

uint32_t

UART 2 Scaler Register

WDGColdResetValue

uint32_t

Watchdog Register

WDGForcedBits

uint32_t

Watchdog Register

WDGForcedFlippedBits

uint32_t

Watchdog Register

WDGReadMask

uint32_t

Watchdog Register

WDGResetMask

uint32_t

Watchdog Register

WDGResetValue

uint32_t

Watchdog Register

WDGWriteMask

uint32_t

Watchdog Register

WPR1ColdResetValue

uint32_t

Write Protection Register 1

WPR1ForcedBits

uint32_t

Write Protection Register 1

WPR1ForcedFlippedBits

uint32_t

Write Protection Register 1

WPR1ReadMask

uint32_t

Write Protection Register 1

WPR1ResetMask

uint32_t

Write Protection Register 1

WPR1ResetValue

uint32_t

Write Protection Register 1

WPR1WriteMask

uint32_t

Write Protection Register 1

WPR2ColdResetValue

uint32_t

Write Protection Register 2

WPR2ForcedBits

uint32_t

Write Protection Register 2

WPR2ForcedFlippedBits

uint32_t

Write Protection Register 2

WPR2ReadMask

uint32_t

Write Protection Register 2

WPR2ResetMask

uint32_t

Write Protection Register 2

WPR2ResetValue

uint32_t

Write Protection Register 2

WPR2WriteMask

uint32_t

Write Protection Register 2

WPSTA1ColdResetValue

uint32_t

Write Protection Start Address 1

WPSTA1ForcedBits

uint32_t

Write Protection Start Address 1

WPSTA1ForcedFlippedBits

uint32_t

Write Protection Start Address 1

WPSTA1ReadMask

uint32_t

Write Protection Start Address 1

WPSTA1ResetMask

uint32_t

Write Protection Start Address 1

WPSTA1ResetValue

uint32_t

Write Protection Start Address 1

WPSTA1WriteMask

uint32_t

Write Protection Start Address 1

WPSTA2ColdResetValue

uint32_t

Write Protection Start Address 2

WPSTA2ForcedBits

uint32_t

Write Protection Start Address 2

WPSTA2ForcedFlippedBits

uint32_t

Write Protection Start Address 2

WPSTA2ReadMask

uint32_t

Write Protection Start Address 2

WPSTA2ResetMask

uint32_t

Write Protection Start Address 2

WPSTA2ResetValue

uint32_t

Write Protection Start Address 2

WPSTA2WriteMask

uint32_t

Write Protection Start Address 2

WPSTO1ColdResetValue

uint32_t

Write Protection End Address 1

WPSTO1ForcedBits

uint32_t

Write Protection End Address 1

WPSTO1ForcedFlippedBits

uint32_t

Write Protection End Address 1

WPSTO1ReadMask

uint32_t

Write Protection End Address 1

WPSTO1ResetMask

uint32_t

Write Protection End Address 1

WPSTO1ResetValue

uint32_t

Write Protection End Address 1

WPSTO1WriteMask

uint32_t

Write Protection End Address 1

WPSTO2ColdResetValue

uint32_t

Write Protection End Address 2

WPSTO2ForcedBits

uint32_t

Write Protection End Address 2

WPSTO2ForcedFlippedBits

uint32_t

Write Protection End Address 2

WPSTO2ReadMask

uint32_t

Write Protection End Address 2

WPSTO2ResetMask

uint32_t

Write Protection End Address 2

WPSTO2ResetValue

uint32_t

Write Protection End Address 2

WPSTO2WriteMask

uint32_t

Write Protection End Address 2

ahbfailaddr

uint32_t

Fail address register

ahbstat

uint32_t

Fail status register

behaviour

uint8_t

Set to 1 for COLE mode

cachectrl

uint32_t

Cache control register

config.levelMask

uint32_t

Level triggered internal interrupts (mask)

config.logInterrupts

uint8_t

Enable interrupt logging

cpu

temu_IfaceRef/ <unknown>

CPU to control with powerdown

dCache

temu_IfaceRef/ <unknown>

Data cache (optional)

gpioBus

temu_IfaceRef/ <unknown>

GPIO bus (deprecated, use signal interface instead)

gpioIrqLevel

uint32_t

gpioIrqMask

uint32_t

gpioIrqPolarity

uint32_t

gpiodir

uint32_t

I/O port direction register

gpioinout

uint32_t

I/O port data register

gpioirqcfg

uint32_t

I/O port interrupt register 1

gpioirqcfg2

uint32_t

I/O port interrupt register 2

iCache

temu_IfaceRef/ <unknown>

Instruction cache (optional)

infiniteUartSpeed

uint32_t

inputBits

uint32_t

Input signals

irqControl

temu_IfaceRef/ <unknown>

Next level IRQ controller object (e.g. CPU)

irqSignalStatus

uint16_t

Interrupt signal status (should be the same as pending in CPU)

irqclear

uint32_t

Interrupt clear register

irqforce

uint32_t

Interrupt force register

irqmask

uint32_t

Interrupt mask and priority register

irqpend

uint32_t

Interrupt pending register

leoncfg

uint32_t

Product configuration register

memcfg1

uint32_t

Memory configuration register 1

memcfg2

uint32_t

Memory configuration register 2

memcfg3

uint32_t

Memory configuration register 3

memcfg4

uint32_t

Memory configuration 4 (COLE)

memcfg5

uint32_t

Memory configuration 5 (COLE)

mr

uint32_t

Map register (COLE)

outSignals

[temu_IfaceRef; 16]/ <unknown>

Outgoing GPIO signals

powerdown

uint32_t

Idle register

presccntr

uint32_t

Prescaler counter register

prescrld

uint32_t

Prescaler reload register

timer1cntr

uint32_t

Timer 1 counter register

timer1ctrl

uint32_t

Timer 1 control register

timer1rld

uint32_t

Timer 1 reload register

timer2cntr

uint32_t

Timer 2 counter register

timer2ctrl

uint32_t

Timer 2 control register

timer2rld

uint32_t

Timer 2 reload register

uart1DatTxHold

uint32_t

UART1 data TX hold register

uart1DatTxShift

uint32_t

UART 1 data TX shift

uart1ctrl

uint32_t

UART 1 control register

uart1datrx

uint32_t

UART 1 RX data register

uart1scal

uint32_t

UART 1 scaler register

uart1stat

uint32_t

UART 1 status register

uart2DatTxHold

uint32_t

uart2DatTxShift

uint32_t

uart2ctrl

uint32_t

UART 2 control register

uart2datrx

uint32_t

UART 2 RX data register

uart2scal

uint32_t

UART 2 scaler register

uart2stat

uint32_t

UART 2 status register

uarta

temu_IfaceRef/ <unknown>

Serial port A

uartb

temu_IfaceRef/ <unknown>

Serial port B

watchdog

uint32_t

Watchdog register

writeprot1

uint32_t

Write protection register 1

writeprot2

uint32_t

Write protection register 2

writeprotstart1

uint32_t

Write protection start address 1

writeprotstart2

uint32_t

Write protection start address 2

writeprotstop1

uint32_t

Write protection end address 1

writeprotstop2

uint32_t

Write protection end address 2

Interfaces

Name Type Description

DCacheCtrlIface

temu::CacheCtrlIface

D-cache to control

DeviceIface

DeviceIface

GpioClientIface

GpioClientIface

ICacheCtrlIface

temu::CacheCtrlIface

I-cache to control

InternalIrqIface

IrqCtrlIface

Internal IRQ controller (native LEON numbering), post your IRQs here.

IrqClientIface

IrqClientIface

IRQ acknowledgement (from CPU)

IrqIface

IrqCtrlIface

External IRQ controller, post your IRQs here.

MemAccessIface

MemAccessIface

RegisterIface

temu::RegisterIface

Register introspection interface

Registers

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

SignalIface

SignalIface

Incomming signals

UartAIface

SerialIface

UART A

UartBIface

SerialIface

UART B

Ports

Prop Iface Description

irqControl

IrqClientIface

Interrupt

uarta

UartAIface

uart a

uartb

UartBIface

uart b

Registers

Register support is currently experimental!

Register Bank Regs

Register MCFG1
Description

Memory Configuration Register 1

Reset value

0x000000ff

Warm reset mask

0x7ef80bff

Diagram
Field Mask Reset Description

pbrdy

0x40000000

0x0

PROM area bus-ready enable

abrdy

0x20000000

0x0

Asynchronous bus ready

iowdh

0x18000000

0x0

I/O bus width

iobrdy

0x04000000

0x0

I/O area bus ready enable

bexc

0x02000000

0x0

Bus error enable for RAM, PROM and I/O access

iows

0x00f00000

0x0

I/O waitstates

ioen

0x00080000

0x0

I/O area enable

prwen

0x00000800

0x0

PROM write enable

prwdh

0x00000300

0x0

PROM width

prwws

0x000000f0

0xf

PROM write waitstates

prrws

0x0000000f

0xf

PROM read waitstates
Register MCFG2
Description

Memory Configuration Register 2

Reset value

0x7c400000

Warm reset mask

0xfff87eff

Diagram
Field Mask Reset Description

sdrref

0x80000000

0x0

SDRAM refresh

trp

0x40000000

0x1

SDRAM tRP timing

trfc

0x38000000

0x7

SDRAM tRFC timing

sdrcas

0x04000000

0x1

SDRAM CAS delay

sdrbs

0x03800000

0x0

SDRAM bank size

sdrcls

0x00600000

0x2

SDRAM column size

sdrcmd

0x00180000

0x0

SDRAM command

se

0x00004000

0x0

SDRAM enable

si

0x00002000

0x0

SRAM disable

rambs

0x00001e00

0x0

SRAM bank size

rambrdy

0x00000080

0x0

SRAM area bus ready enable

ramrmw

0x00000040

0x0

Read-modify-write on the SRAM

ramwdh

0x00000030

0x0

SRAM bus width

ramwws

0x0000000c

0x0

SRAM write waitstates

ramrws

0x00000003

0x0

SRAM read waitstates
Register MCFG3
Description

Memory Configuration Register 3

Reset value

0xc8000000

Warm reset mask

0xc8000c00

Diagram
Field Mask Reset Description

rfc

0xc0000000

0x3

Register file check bits

me

0x08000000

0x1

Memory EDAC

srcrv

0x07fff000

-

SDRAM refresh counter reload value

wb

0x00000800

0x0

EDAC diagnostic write bypass

rb

0x00000400

0x0

EDAC diagnostic read

re

0x00000200

-

RAM EDAC enable

pe

0x00000100

-

PROM EDAC enable

tcb

0x000000ff

-

Test checkbits
Register FAILAR
Description

Fail Address Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

hea

0xffffffff

-

Hardware error address
Register FAILSR
Description

Fail Status Register

Reset value

0x00000000

Warm reset mask

0x00000100

Diagram
Field Mask Reset Description

eed

0x00000200

-

EDAC-correctable error detected

hed

0x00000100

0x0

Hardware error detected

het

0x00000080

-

Hardware error type

hem

0x00000078

-

Hardware error module

hes

0x00000007

-

Hardware error size
Register CCR
Description

Cache Control Register

Reset value

0xfd100000

Warm reset mask

0xff99c00f

Diagram
Field Mask Reset Description

drepl

0xc0000000

0x3

Data cache replacement policy

irepl

0x30000000

0x3

Instruction cache replacement policy

isets

0x0c000000

0x3

Instruction cache associativity

dsets

0x03000000

0x1

Data cache associativity

ds

0x00800000

0x0

Data cache snoop enable

fd

0x00400000

-

Flush data cache

fi

0x00200000

-

Flush instruction cache

cpc

0x00180000

0x2

Cache parity bits

cptb

0x00060000

-

Cache parity test bits

ib

0x00010000

0x0

Instruction burst fetch

ip

0x00008000

0x0

Instruction cache flush pending

dp

0x00004000

0x0

Data cache flush pending

ite

0x00003000

-

Instruction cache tag error counter

ide

0x00000c00

-

Instruction cache data error counter

dte

0x00000300

-

Data cache tag error counter

dde

0x000000c0

-

Data cache data error counter

df

0x00000020

-

Data cache freeze on interrupt

if

0x00000010

-

Instruction cache freeze on interrupt

dcs

0x0000000c

0x0

Data cache state

ics

0x00000003

0x0

Instruction cache state
Register IDLE
Description

Idle Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

idle

0xffffffff

-

Idle mode trigger
Register WPR1
Description

Write Protection Register 1

Reset value

0x00000000

Warm reset mask

0x80000000

Diagram
Field Mask Reset Description

en

0x80000000

0x0

Enable

bp

0x40000000

-

Block protect

tag

0x3fff8000

-

Address tag

mask

0x00007fff

-

Address mask
Register WPR2
Description

Write Protection Register 2

Reset value

0x00000000

Warm reset mask

0x80000000

Diagram
Field Mask Reset Description

en

0x80000000

0x0

Enable

bp

0x40000000

-

Block protect

tag

0x3fff8000

-

Address tag

mask

0x00007fff

-

Address mask
Register PCR
Description

Product Configuration Register

Reset value

0x7077bbd5

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

mmu

0x80000000

0x0

Memory management unit

dsu

0x40000000

0x1

Debug support unit

sdrctrl

0x20000000

0x1

SDRAM controller

wtpnt

0x1c000000

0x4

IU watchpoints

imac

0x02000000

0x0

UMAC/SMAC instructions

nwin

0x01f00000

0x7

IU register file windows

icsz

0x000e0000

0x3

Instruction cache set size

ilsz

0x00018000

0x3

Instruction cache line size

dcsz

0x00007000

0x3

Data cache set size

dlsz

0x00000c00

0x2

Data cache line size

divinst

0x00000200

0x1

UDIV/SDIV instructions

mulinst

0x00000100

0x1

UMUL/SMUL instructions

wdog

0x00000080

0x1

Watchdog

memstat

0x00000040

0x1

Memory status and address failing register

fpu

0x00000030

0x1

FPU type

pci

0x0000000c

0x1

PCI core type

wprt

0x00000003

0x1

Write protection
Register TIMC1
Description

Timer 1 Counter Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

cnt

0xffffffff

-

Timer 1 counter value
Register TIMR1
Description

Timer 1 Reload Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

rv

0xffffffff

-

Timer 1 reload value
Register TIMCTR1
Description

Timer 1 Control Register

Reset value

0x00000000

Warm reset mask

0x00000005

Diagram
Field Mask Reset Description

ld

0x00000004

0x0

Load counter

rl

0x00000002

-

Reload counter

en

0x00000001

0x0

Enable counter
Register WDG
Description

Watchdog Register

Reset value

0xffffffff

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

cnt

0xffffffff

0xffffffff

Watchdog counter value
Register TIMC2
Description

Timer 2 Counter Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

cnt

0xffffffff

-

Timer 2 counter value
Register TIMR2
Description

Timer 2 Reload Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

rv

0xffffffff

-

Timer 2 reload value
Register TIMCTR2
Description

Timer 2 Control Register

Reset value

0x00000000

Warm reset mask

0x00000005

Diagram
Field Mask Reset Description

ld

0x00000004

0x0

Load counter

rl

0x00000002

-

Reload counter

en

0x00000001

0x0

Enable counter
Register SCAC
Description

Prescaler Counter Register

Reset value

0x00000000

Warm reset mask

0x000003ff

Diagram
Field Mask Reset Description

cnt

0x000003ff

0x0

Prescaler counter value
Register SCAR
Description

Prescaler Reload Register

Reset value

0x00000000

Warm reset mask

0x000003ff

Diagram
Field Mask Reset Description

rv

0x000003ff

0x0

Prescaler reload value
Register UAD1
Description

UART 1 Data Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

rtd

0x000000ff

-

Received/transmit data on UART 1
Register UAS1
Description

UART 1 Status Register

Reset value

0x00000006

Warm reset mask

0x0000007f

Diagram
Field Mask Reset Description

fe

0x00000040

0x0

Framing error

pe

0x00000020

0x0

Parity error

ov

0x00000010

0x0

Overrun

br

0x00000008

0x0

Break received

th

0x00000004

0x1

Transmitter hold register empty

ts

0x00000002

0x1

Transmitter shift register empty

dr

0x00000001

0x0

Data ready
Register UAC1
Description

UART 1 Control Register

Reset value

0x00000000

Warm reset mask

0x00000143

Diagram
Field Mask Reset Description

ec

0x00000100

0x0

External clock

lb

0x00000080

-

Loop back

fl

0x00000040

0x0

Flow control

pe

0x00000020

-

Parity enable

ps

0x00000010

-

Parity select

ti

0x00000008

-

Transmitter interrupt enable

ri

0x00000004

-

Receiver interrupt enable

te

0x00000002

0x0

Transmitter enable

re

0x00000001

0x0

Receiver enable
Register UASCA1
Description

UART 1 Scaler Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

rv

0x000000ff

-

UART 1 scaler reload value
Register UAD2
Description

UART 2 Data Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

rtd

0x000000ff

-

Received/transmit data on UART 2
Register UAS2
Description

UART 2 Status Register

Reset value

0x00000006

Warm reset mask

0x0000007f

Diagram
Field Mask Reset Description

fe

0x00000040

0x0

Framing error

pe

0x00000020

0x0

Parity error

ov

0x00000010

0x0

Overrun

br

0x00000008

0x0

Break received

th

0x00000004

0x1

Transmitter hold register empty

ts

0x00000002

0x1

Transmitter shift register empty

dr

0x00000001

0x0

Data ready
Register UAC2
Description

UART 2 Control Register

Reset value

0x00000000

Warm reset mask

0x00000143

Diagram
Field Mask Reset Description

ec

0x00000100

0x0

External clock

lb

0x00000080

-

Loop back

fl

0x00000040

0x0

Flow control

pe

0x00000020

-

Parity enable

ps

0x00000010

-

Parity select

ti

0x00000008

-

Transmitter interrupt enable

ri

0x00000004

-

Receiver interrupt enable

te

0x00000002

0x0

Transmitter enable

re

0x00000001

0x0

Receiver enable
Register UASCA2
Description

UART 2 Scaler Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

rv

0x000000ff

-

UART 2 scaler reload value
Register ITMP
Description

Interrupt Mask and Priority Register

Reset value

0x00000000

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

ilevel

0xffff0000

-

Interrupt level

imask

0x0000ffff

0x0

Interrupt mask
Register ITP
Description

Interrupt Pending Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

ipend

0x0000ffff

-

Interrupt pending
Register ITF
Description

Interrupt Force Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

iforce

0x0000ffff

-

Interrupt force
Register ITC
Description

Interrupt Clear Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

iclear

0x0000ffff

-

Interrupt clear
Register IODAT
Description

I/O Port Data Register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

meddat

0xff000000

-

D[15:8] bus value

lowdat

0x00ff0000

-

D[7:0] bus value

piodat

0x0000ffff

-

PIO[15:0] port value
Register IODIR
Description

I/O Port Direction Register

Reset value

0x00000000

Warm reset mask

0x0003ffff

Diagram
Field Mask Reset Description

meddir

0x00020000

0x0

D[15:8] port direction

lowdir

0x00010000

0x0

D[7:0] port direction

piodir

0x0000ffff

0x0

PIO[15:0] port direction
Register IOIT1
Description

I/O Port Interrupt Register 1

Reset value

0x00000000

Warm reset mask

0x80808080

Diagram
Field Mask Reset Description

en3

0x80000000

0x0

Interrupt 3 enable

le3

0x40000000

-

Interrupt 3 level/edge trigger

pl3

0x20000000

-

Interrupt 3 polarity

isel3

0x1f000000

-

Interrupt 3 I/O port select

en2

0x00800000

0x0

Interrupt 2 enable

le2

0x00400000

-

Interrupt 2 level/edge trigger

pl2

0x00200000

-

Interrupt 2 polarity

isel2

0x001f0000

-

Interrupt 2 I/O port select

en1

0x00008000

0x0

Interrupt 1 enable

le1

0x00004000

-

Interrupt 1 level/edge trigger

pl1

0x00002000

-

Interrupt 1 polarity

isel1

0x00001f00

-

Interrupt 1 I/O port select

en0

0x00000080

0x0

Interrupt 0 enable

le0

0x00000040

-

Interrupt 0 level/edge trigger

pl0

0x00000020

-

Interrupt 0 polarity

isel0

0x0000001f

-

Interrupt 0 I/O port select
Register IOIT2
Description

I/O Port Interrupt Register 2

Reset value

0x00000000

Warm reset mask

0x80808080

Diagram
Field Mask Reset Description

en7

0x80000000

0x0

Interrupt 7 enable

le7

0x40000000

-

Interrupt 7 level/edge trigger

pl7

0x20000000

-

Interrupt 7 polarity

isel7

0x1f000000

-

Interrupt 7 I/O port select

en6

0x00800000

0x0

Interrupt 6 enable

le6

0x00400000

-

Interrupt 6 level/edge trigger

pl6

0x00200000

-

Interrupt 6 polarity

isel6

0x001f0000

-

Interrupt 6 I/O port select

en5

0x00008000

0x0

Interrupt 5 enable

le5

0x00004000

-

Interrupt 5 level/edge trigger

pl5

0x00002000

-

Interrupt 5 polarity

isel5

0x00001f00

-

Interrupt 5 I/O port select

en4

0x00000080

0x0

Interrupt 4 enable

le4

0x00000040

-

Interrupt 4 level/edge trigger

pl4

0x00000020

-

Interrupt 4 polarity

isel4

0x0000001f

-

Interrupt 4 I/O port select
Register WPSTA1
Description

Write Protection Start Address 1

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

start

0x3ffffffc

-

Start address

bp

0x00000002

-

Block protect
Register WPSTO1
Description

Write Protection End Address 1

Reset value

0x00000000

Warm reset mask

0x00000003

Diagram
Field Mask Reset Description

end

0x3ffffffc

-

End address

us

0x00000002

0x0

User mode

su

0x00000001

0x0

Supervisor mode
Register WPSTA2
Description

Write Protection Start Address 2

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

start

0x3ffffffc

-

Start address

bp

0x00000002

-

Block protect
Register WPSTO2
Description

Write Protection End Address 2

Reset value

0x00000000

Warm reset mask

0x00000003

Diagram
Field Mask Reset Description

end

0x3ffffffc

-

End address

us

0x00000002

0x0

User mode

su

0x00000001

0x0

Supervisor mode

Commands

Name Description

delete

Dispose instance of Leon2SoC

lowerInternalIrq

Lower internally numbered interrupts

raiseExternalIrq

Raise externally numbered interrupts

raiseInternalIrq

Raise internally numbered interrupts

Command lowerInternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number

Command raiseExternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number

Command raiseInternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number