GRLIB GRCAN Model

The GRCAN model is available in the GrCan plugin.

Loading the Plugin

import GrCan

Configuration

@GRCAN Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GRCAN

new

Create new instance of GRCAN

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GRCAN Reference

Properties

Name Type Description

CONFColdResetValue

uint32_t

Configuration register

CONFForcedBits

uint32_t

Configuration register

CONFForcedFlippedBits

uint32_t

Configuration register

CONFReadMask

uint32_t

Configuration register

CONFResetMask

uint32_t

Configuration register

CONFResetValue

uint32_t

Configuration register

CONFWriteMask

uint32_t

Configuration register

CTRLColdResetValue

uint32_t

Control register

CTRLForcedBits

uint32_t

Control register

CTRLForcedFlippedBits

uint32_t

Control register

CTRLReadMask

uint32_t

Control register

CTRLResetMask

uint32_t

Control register

CTRLResetValue

uint32_t

Control register

CTRLWriteMask

uint32_t

Control register

CanIMRColdResetValue

uint32_t

Interrupt mask register

CanIMRForcedBits

uint32_t

Interrupt mask register

CanIMRForcedFlippedBits

uint32_t

Interrupt mask register

CanIMRReadMask

uint32_t

Interrupt mask register

CanIMRResetMask

uint32_t

Interrupt mask register

CanIMRResetValue

uint32_t

Interrupt mask register

CanIMRWriteMask

uint32_t

Interrupt mask register

CanPIRColdResetValue

uint32_t

Pending interrupt register

CanPIRForcedBits

uint32_t

Pending interrupt register

CanPIRForcedFlippedBits

uint32_t

Pending interrupt register

CanPIRReadMask

uint32_t

Pending interrupt register

CanPIRResetMask

uint32_t

Pending interrupt register

CanPIRResetValue

uint32_t

Pending interrupt register

CanPIRWriteMask

uint32_t

Pending interrupt register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

RXADDRColdResetValue

uint32_t

Receive channel address register

RXADDRForcedBits

uint32_t

Receive channel address register

RXADDRForcedFlippedBits

uint32_t

Receive channel address register

RXADDRReadMask

uint32_t

Receive channel address register

RXADDRResetMask

uint32_t

Receive channel address register

RXADDRResetValue

uint32_t

Receive channel address register

RXADDRWriteMask

uint32_t

Receive channel address register

RXCODEColdResetValue

uint32_t

Receive channel code register

RXCODEForcedBits

uint32_t

Receive channel code register

RXCODEForcedFlippedBits

uint32_t

Receive channel code register

RXCODEReadMask

uint32_t

Receive channel code register

RXCODEResetMask

uint32_t

Receive channel code register

RXCODEResetValue

uint32_t

Receive channel code register

RXCODEWriteMask

uint32_t

Receive channel code register

RXCTRLColdResetValue

uint32_t

Receive channel control register

RXCTRLForcedBits

uint32_t

Receive channel control register

RXCTRLForcedFlippedBits

uint32_t

Receive channel control register

RXCTRLReadMask

uint32_t

Receive channel control register

RXCTRLResetMask

uint32_t

Receive channel control register

RXCTRLResetValue

uint32_t

Receive channel control register

RXCTRLWriteMask

uint32_t

Receive channel control register

RXIRQColdResetValue

uint32_t

Receive channel interrupt register

RXIRQForcedBits

uint32_t

Receive channel interrupt register

RXIRQForcedFlippedBits

uint32_t

Receive channel interrupt register

RXIRQReadMask

uint32_t

Receive channel interrupt register

RXIRQResetMask

uint32_t

Receive channel interrupt register

RXIRQResetValue

uint32_t

Receive channel interrupt register

RXIRQWriteMask

uint32_t

Receive channel interrupt register

RXMASKColdResetValue

uint32_t

Receive channel mask register

RXMASKForcedBits

uint32_t

Receive channel mask register

RXMASKForcedFlippedBits

uint32_t

Receive channel mask register

RXMASKReadMask

uint32_t

Receive channel mask register

RXMASKResetMask

uint32_t

Receive channel mask register

RXMASKResetValue

uint32_t

Receive channel mask register

RXMASKWriteMask

uint32_t

Receive channel mask register

RXRDColdResetValue

uint32_t

Receive channel read register

RXRDForcedBits

uint32_t

Receive channel read register

RXRDForcedFlippedBits

uint32_t

Receive channel read register

RXRDReadMask

uint32_t

Receive channel read register

RXRDResetMask

uint32_t

Receive channel read register

RXRDResetValue

uint32_t

Receive channel read register

RXRDWriteMask

uint32_t

Receive channel read register

RXSIZEColdResetValue

uint32_t

Receive channel size register

RXSIZEForcedBits

uint32_t

Receive channel size register

RXSIZEForcedFlippedBits

uint32_t

Receive channel size register

RXSIZEReadMask

uint32_t

Receive channel size register

RXSIZEResetMask

uint32_t

Receive channel size register

RXSIZEResetValue

uint32_t

Receive channel size register

RXSIZEWriteMask

uint32_t

Receive channel size register

RXWRColdResetValue

uint32_t

Receive channel write register

RXWRForcedBits

uint32_t

Receive channel write register

RXWRForcedFlippedBits

uint32_t

Receive channel write register

RXWRReadMask

uint32_t

Receive channel write register

RXWRResetMask

uint32_t

Receive channel write register

RXWRResetValue

uint32_t

Receive channel write register

RXWRWriteMask

uint32_t

Receive channel write register

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

STATColdResetValue

uint32_t

Status register

STATForcedBits

uint32_t

Status register

STATForcedFlippedBits

uint32_t

Status register

STATReadMask

uint32_t

Status register

STATResetMask

uint32_t

Status register

STATResetValue

uint32_t

Status register

STATWriteMask

uint32_t

Status register

SYNCCODEColdResetValue

uint32_t

Sync code filter register

SYNCCODEForcedBits

uint32_t

Sync code filter register

SYNCCODEForcedFlippedBits

uint32_t

Sync code filter register

SYNCCODEReadMask

uint32_t

Sync code filter register

SYNCCODEResetMask

uint32_t

Sync code filter register

SYNCCODEResetValue

uint32_t

Sync code filter register

SYNCCODEWriteMask

uint32_t

Sync code filter register

SYNCMASKColdResetValue

uint32_t

Sync mask filter register

SYNCMASKForcedBits

uint32_t

Sync mask filter register

SYNCMASKForcedFlippedBits

uint32_t

Sync mask filter register

SYNCMASKReadMask

uint32_t

Sync mask filter register

SYNCMASKResetMask

uint32_t

Sync mask filter register

SYNCMASKResetValue

uint32_t

Sync mask filter register

SYNCMASKWriteMask

uint32_t

Sync mask filter register

TXADDRColdResetValue

uint32_t

Transmit channel address register

TXADDRForcedBits

uint32_t

Transmit channel address register

TXADDRForcedFlippedBits

uint32_t

Transmit channel address register

TXADDRReadMask

uint32_t

Transmit channel address register

TXADDRResetMask

uint32_t

Transmit channel address register

TXADDRResetValue

uint32_t

Transmit channel address register

TXADDRWriteMask

uint32_t

Transmit channel address register

TXCTRLColdResetValue

uint32_t

Transmit channel control register

TXCTRLForcedBits

uint32_t

Transmit channel control register

TXCTRLForcedFlippedBits

uint32_t

Transmit channel control register

TXCTRLReadMask

uint32_t

Transmit channel control register

TXCTRLResetMask

uint32_t

Transmit channel control register

TXCTRLResetValue

uint32_t

Transmit channel control register

TXCTRLWriteMask

uint32_t

Transmit channel control register

TXIRQColdResetValue

uint32_t

Transmit channel interrupt register

TXIRQForcedBits

uint32_t

Transmit channel interrupt register

TXIRQForcedFlippedBits

uint32_t

Transmit channel interrupt register

TXIRQReadMask

uint32_t

Transmit channel interrupt register

TXIRQResetMask

uint32_t

Transmit channel interrupt register

TXIRQResetValue

uint32_t

Transmit channel interrupt register

TXIRQWriteMask

uint32_t

Transmit channel interrupt register

TXRDColdResetValue

uint32_t

Transmit channel read register

TXRDForcedBits

uint32_t

Transmit channel read register

TXRDForcedFlippedBits

uint32_t

Transmit channel read register

TXRDReadMask

uint32_t

Transmit channel read register

TXRDResetMask

uint32_t

Transmit channel read register

TXRDResetValue

uint32_t

Transmit channel read register

TXRDWriteMask

uint32_t

Transmit channel read register

TXSIZEColdResetValue

uint32_t

Transmit channel size register

TXSIZEForcedBits

uint32_t

Transmit channel size register

TXSIZEForcedFlippedBits

uint32_t

Transmit channel size register

TXSIZEReadMask

uint32_t

Transmit channel size register

TXSIZEResetMask

uint32_t

Transmit channel size register

TXSIZEResetValue

uint32_t

Transmit channel size register

TXSIZEWriteMask

uint32_t

Transmit channel size register

TXWRColdResetValue

uint32_t

Transmit channel write register

TXWRForcedBits

uint32_t

Transmit channel write register

TXWRForcedFlippedBits

uint32_t

Transmit channel write register

TXWRReadMask

uint32_t

Transmit channel write register

TXWRResetMask

uint32_t

Transmit channel write register

TXWRResetValue

uint32_t

Transmit channel write register

TXWRWriteMask

uint32_t

Transmit channel write register

TimeSource

*void

Time source object

bus

temu_IfaceRef/ <unknown>

CAN bus.

cfg

uint32_t

Configuration register

config.irq

uint8_t

Interrupt number

config.littleEndian

uint8_t

Endianess of memory interface.

config.logMessages

uint8_t

Enable logging of transmitted and received messages.

config.singleIrq

uint8_t

Single interrupt

ctrl

uint32_t

Control register

irqCtrl

temu_IfaceRef/ <unknown>

IRQ controller.

irqMask

uint32_t

Interrupt mask register

memAccess

temu_IfaceRef/ <unknown>

Memory access for DMA

pendIrq

uint32_t

Pending interrupt register

pnp.bar

uint32_t

AMBA plug and play base address register

pnp.config

uint32_t

AMBA plug and play config word

rxChanAddr

uint32_t

Receive channel address register

rxChanCode

uint32_t

Receive channel code register

rxChanCtrl

uint32_t

Receive channel control register

rxChanIrq

uint32_t

Receive channel interrupt register

rxChanMask

uint32_t

Receive channel mask register

rxChanRd

uint32_t

Receive channel read register

rxChanSize

uint32_t

Receive channel size register

rxChanWr

uint32_t

Receive channel write register

stat

uint32_t

Status register

syncCodeFilt

uint32_t

Sync code filter register

syncMaskFilt

uint32_t

Sync mask filter register

txChanAddr

uint32_t

Transmit channel address register

txChanCtrl

uint32_t

Transmit channel control register

txChanIrq

uint32_t

Transmit channel interrupt register

txChanRd

uint32_t

Transmit channel read register

txChanSize

uint32_t

Transmit channel size register

txChanWr

uint32_t

Transmit channel write register

Interfaces

Name Type Description

ApbIface

ApbIface

APB P&P interface

CanDevIface

CanDevIface

CAN device interface

DeviceIface

DeviceIface

MemAccessIface

MemAccessIface

Memory access interface (registers)

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Registers

Register support is currently experimental!

Register Bank Regs

Register CONF
Description

Configuration register

Reset value

0x00000000

Warm reset mask

0xffff733f

Diagram
Field Mask Reset Description

SCALER

0xff000000

0x0

Prescaler setting

PS1

0x00f00000

0x0

Phase segment 1

PS2

0x000f0000

0x0

Phase segment 2

RSJ

0x00007000

0x0

Resynchronization jumps

BPR

0x00000300

0x0

Baud rate prescaler

SAM

0x00000020

0x0

Sample mode

SILENT

0x00000010

0x0

Listen-only mode

SELECT

0x00000008

0x0

Receiver and transmitter selection

ENABLE1

0x00000004

0x0

Output 1 enable

ENABLE0

0x00000002

0x0

Output 0 enable

ABORT

0x00000001

0x0

Abort transfer on AHB error
Register STAT
Description

Status register

Reset value

0x00000000

Warm reset mask

0xffffff0f

Diagram
Field Mask Reset Description

TxChannels

0xf0000000

0x0

Number of Tx channels minus one

RxChannels

0x0f000000

0x0

Number of Rx channels minus one

TxErrCntr

0x00ff0000

0x0

Transmission error counter

RxErrCntr

0x0000ff00

0x0

Reception error counter

AHBErr

0x00000008

0x0

AMBA AHB master interface blocked by previous AHB error

OR

0x00000004

0x0

Overrun during reception

OFF

0x00000002

0x0

Bus-off condition

PASS

0x00000001

0x0

Error-passive condition
Register CTRL
Description

Control register

Reset value

0x00000000

Warm reset mask

0x00000001

Diagram
Field Mask Reset Description

RESET

0x00000002

-

Reset complete core

ENABLE

0x00000001

0x0

Enable CAN controller
Register SYNCMASK
Description

Sync mask filter register

Reset value

0x1fffffff

Warm reset mask

0x1fffffff

Diagram
Field Mask Reset Description

MASK

0x1fffffff

0x1fffffff

SYNC message identifier mask
Register SYNCCODE
Description

Sync code filter register

Reset value

0x00000000

Warm reset mask

0x1fffffff

Diagram
Field Mask Reset Description

SYNC

0x1fffffff

0x0

SYNC message identifier
Register CanPIMSR
Description

Pending interrupt masked status register

Reset value

0x00000000

Warm reset mask

0x0001ffff

Diagram
Field Mask Reset Description

TxLoss

0x00010000

0x0

Message arbitration lost during transmission

RxMiss

0x00008000

0x0

Message filtered away during reception

TxErrCntr

0x00004000

0x0

Transmission error counter incremented

RxErrCntr

0x00002000

0x0

Reception error counter incremented

TxSync

0x00001000

0x0

Synchronization message transmitted

RxSync

0x00000800

0x0

Synchronization message received

Tx

0x00000400

0x0

Successful transmission of message

Rx

0x00000200

0x0

Successful reception of message

TxEmpty

0x00000100

0x0

Successful transmission of all messages in buffer

RxFull

0x00000080

0x0

Successful reception of all messages possible to store in buffer

TxIRQ

0x00000040

0x0

Successful transmission of a predefined number of messages

RxIRQ

0x00000020

0x0

Successful reception of a predefined number of messages

TxAHBErr

0x00000010

0x0

AHB error during transmission

RxAHBErr

0x00000008

0x0

AHB error during reception

OR

0x00000004

0x0

Overrun during reception

OFF

0x00000002

0x0

Bus-off condition

PASS

0x00000001

0x0

Error-passive condition
Register CanPIMR
Description

Pending interrupt masked register

Reset value

0x00000000

Warm reset mask

0x0001ffff

Diagram
Field Mask Reset Description

TxLoss

0x00010000

0x0

Message arbitration lost during transmission

RxMiss

0x00008000

0x0

Message filtered away during reception

TxErrCntr

0x00004000

0x0

Transmission error counter incremented

RxErrCntr

0x00002000

0x0

Reception error counter incremented

TxSync

0x00001000

0x0

Synchronization message transmitted

RxSync

0x00000800

0x0

Synchronization message received

Tx

0x00000400

0x0

Successful transmission of message

Rx

0x00000200

0x0

Successful reception of message

TxEmpty

0x00000100

0x0

Successful transmission of all messages in buffer

RxFull

0x00000080

0x0

Successful reception of all messages possible to store in buffer

TxIRQ

0x00000040

0x0

Successful transmission of a predefined number of messages

RxIRQ

0x00000020

0x0

Successful reception of a predefined number of messages

TxAHBErr

0x00000010

0x0

AHB error during transmission

RxAHBErr

0x00000008

0x0

AHB error during reception

OR

0x00000004

0x0

Overrun during reception

OFF

0x00000002

0x0

Bus-off condition

PASS

0x00000001

0x0

Error-passive condition
Register CanPISR
Description

Pending interrupt status register

Reset value

0x00000000

Warm reset mask

0x0001ffff

Diagram
Field Mask Reset Description

TxLoss

0x00010000

0x0

Message arbitration lost during transmission

RxMiss

0x00008000

0x0

Message filtered away during reception

TxErrCntr

0x00004000

0x0

Transmission error counter incremented

RxErrCntr

0x00002000

0x0

Reception error counter incremented

TxSync

0x00001000

0x0

Synchronization message transmitted

RxSync

0x00000800

0x0

Synchronization message received

Tx

0x00000400

0x0

Successful transmission of message

Rx

0x00000200

0x0

Successful reception of message

TxEmpty

0x00000100

0x0

Successful transmission of all messages in buffer

RxFull

0x00000080

0x0

Successful reception of all messages possible to store in buffer

TxIRQ

0x00000040

0x0

Successful transmission of a predefined number of messages

RxIRQ

0x00000020

0x0

Successful reception of a predefined number of messages

TxAHBErr

0x00000010

0x0

AHB error during transmission

RxAHBErr

0x00000008

0x0

AHB error during reception

OR

0x00000004

0x0

Overrun during reception

OFF

0x00000002

0x0

Bus-off condition

PASS

0x00000001

0x0

Error-passive condition
Register CanPIR
Description

Pending interrupt register

Reset value

0x00000000

Warm reset mask

0x0001ffff

Diagram
Field Mask Reset Description

TxLoss

0x00010000

0x0

Message arbitration lost during transmission

RxMiss

0x00008000

0x0

Message filtered away during reception

TxErrCntr

0x00004000

0x0

Transmission error counter incremented

RxErrCntr

0x00002000

0x0

Reception error counter incremented

TxSync

0x00001000

0x0

Synchronization message transmitted

RxSync

0x00000800

0x0

Synchronization message received

Tx

0x00000400

0x0

Successful transmission of message

Rx

0x00000200

0x0

Successful reception of message

TxEmpty

0x00000100

0x0

Successful transmission of all messages in buffer

RxFull

0x00000080

0x0

Successful reception of all messages possible to store in buffer

TxIRQ

0x00000040

0x0

Successful transmission of a predefined number of messages

RxIRQ

0x00000020

0x0

Successful reception of a predefined number of messages

TxAHBErr

0x00000010

0x0

AHB error during transmission

RxAHBErr

0x00000008

0x0

AHB error during reception

OR

0x00000004

0x0

Overrun during reception

OFF

0x00000002

0x0

Bus-off condition

PASS

0x00000001

0x0

Error-passive condition
Register CanIMR
Description

Interrupt mask register

Reset value

0x00000000

Warm reset mask

0x0001ffff

Diagram
Field Mask Reset Description

TxLoss

0x00010000

0x0

Message arbitration lost interrupt mask

RxMiss

0x00008000

0x0

Receive miss interrupt mask

TxErrCntr

0x00004000

0x0

Tx error counter interrupt mask

RxErrCntr

0x00002000

0x0

Rx error counter interrupt mask

TxSync

0x00001000

0x0

Tx synchronization interrupt mask

RxSync

0x00000800

0x0

Rx synchronization interrupt mask

Tx

0x00000400

0x0

Transmit interrupt mask

Rx

0x00000200

0x0

Receive interrupt mask

TxEmpty

0x00000100

0x0

Transmit empty interrupt mask

RxFull

0x00000080

0x0

Receive full interrupt mask

TxIRQ

0x00000040

0x0

Transmit channel interrupt mask

RxIRQ

0x00000020

0x0

Receive channel interrupt mask

TxAHBErr

0x00000010

0x0

Transmit AHB error interrupt mask

RxAHBErr

0x00000008

0x0

Receive AHB error interrupt mask

OR

0x00000004

0x0

Overrun interrupt mask

OFF

0x00000002

0x0

Bus-off interrupt mask

PASS

0x00000001

0x0

Error-passive interrupt mask
Register CanPICR
Description

Pending interrupt clear register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

INTERRUPTS

0x0001ffff

-

Pending interrupt clear
Register TXCTRL
Description

Transmit channel control register

Reset value

0x00000000

Warm reset mask

0x00000007

Diagram
Field Mask Reset Description

SINGLE

0x00000004

0x0

Single shot mode

ONGOING

0x00000002

0x0

Transmission ongoing

ENABLE

0x00000001

0x0

Enable channel
Register TXADDR
Description

Transmit channel address register

Reset value

0x00000000

Warm reset mask

0xfffffc00

Diagram
Field Mask Reset Description

ADDR

0xfffffc00

0x0

Base address for circular buffer
Register TXSIZE
Description

Transmit channel size register

Reset value

0x00000000

Warm reset mask

0x001fffc0

Diagram
Field Mask Reset Description

SIZE

0x001fffc0

0x0

Circular buffer size
Register TXWR
Description

Transmit channel write register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

WRITE

0x000ffff0

0x0

Pointer to last written message plus one
Register TXRD
Description

Transmit channel read register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

READ

0x000ffff0

0x0

Pointer to last read message plus one
Register TXIRQ
Description

Transmit channel interrupt register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

IRQ

0x000ffff0

0x0

Transmit interrupt pointer
Register RXCTRL
Description

Receive channel control register

Reset value

0x00000000

Warm reset mask

0x00000003

Diagram
Field Mask Reset Description

ONGOING

0x00000002

0x0

Reception ongoing

ENABLE

0x00000001

0x0

Enable channel
Register RXADDR
Description

Receive channel address register

Reset value

0x00000000

Warm reset mask

0xfffffc00

Diagram
Field Mask Reset Description

ADDR

0xfffffc00

0x0

Base address for circular buffer
Register RXSIZE
Description

Receive channel size register

Reset value

0x00000000

Warm reset mask

0x001fffc0

Diagram
Field Mask Reset Description

SIZE

0x001fffc0

0x0

Circular buffer size
Register RXWR
Description

Receive channel write register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

WRITE

0x000ffff0

0x0

Pointer to last written message plus one
Register RXRD
Description

Receive channel read register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

READ

0x000ffff0

0x0

Pointer to last read message plus one
Register RXIRQ
Description

Receive channel interrupt register

Reset value

0x00000000

Warm reset mask

0x000ffff0

Diagram
Field Mask Reset Description

IRQ

0x000ffff0

0x0

Receive interrupt pointer
Register RXMASK
Description

Receive channel mask register

Reset value

0x1fffffff

Warm reset mask

0x1fffffff

Diagram
Field Mask Reset Description

AM

0x1fffffff

0x1fffffff

Acceptance mask
Register RXCODE
Description

Receive channel code register

Reset value

0x00000000

Warm reset mask

0x1fffffff

Diagram
Field Mask Reset Description

AC

0x1fffffff

0x0

Acceptance code

Commands

Name Description

delete

Dispose instance of GRCAN

Limitations

  • There is no arbitration of messages in the message passing simulated world and buses are not synchronized.

  • The model does at present not register filters with the CAN bus model.