GRLIB L4STAT Model

The L4STAT device is part of the GRLIB IP library. It is available in libTEMUL4STAT.so.

Loading the Plugin

import L4STAT

Configuration

@L4STAT Reference

Properties

Name	Type	Description
Class	*void	Class object
Component	*void	Pointer to component object if part of component
LocalName	*char	Local name (in component, if applicable)
LogMessageFlags	uint64_t	Per-object log message suppression flags
LoggingFlags	uint64_t	Flags for logging info
Name	*char	Object name
ObjectID	uint64_t	Unique ObjectID.
ReplayLoggingFlags	uint64_t	Replay-time category logging flags
TimeSource	*void	Time source object

Name

Type

Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name	Description
delete	Dispose instance of @L4STAT
new	Create new instance of L4STAT

Name

Description

delete

Dispose instance of @L4STAT

new

Create new instance of L4STAT

Command new Arguments

Name	Type	Required	Description
name	string	yes	Name of object to create

Name

Type

Required

Description

name

string

yes

Name of object to create

L4STAT Reference

Properties

Name	Type	Description
CCTRL	[uint32_t; 16]	Counter control register
CSVAL	[uint32_t; 16]	Counter max/latch register
CVAL	[uint32_t; 16]	Counter value register
Class	*void	Class object
Component	*void	Pointer to component object if part of component
LocalName	*char	Local name (in component, if applicable)
LogMessageFlags	uint64_t	Per-object log message suppression flags
LoggingFlags	uint64_t	Flags for logging info
Name	*char	Object name
ObjectID	uint64_t	Unique ObjectID.
ReplayLoggingFlags	uint64_t	Replay-time category logging flags
TSTAMP	uint32_t	Timestamp register
TSTAMPColdResetValue	uint32_t	Timestamp register
TSTAMPForcedBits	uint32_t	Timestamp register
TSTAMPForcedFlippedBits	uint32_t	Timestamp register
TSTAMPReadMask	uint32_t	Timestamp register
TSTAMPResetMask	uint32_t	Timestamp register
TSTAMPResetValue	uint32_t	Timestamp register
TSTAMPWriteMask	uint32_t	Timestamp register
TimeSource	*void	Time source object
apb.pnp.bar	uint32_t
apb.pnp.config	uint32_t
config.littleEndian	uint8_t	Endianess of memory interface.

Name

Type

Description

CCTRL

[uint32_t; 16]

Counter control register

CSVAL

[uint32_t; 16]

Counter max/latch register

CVAL

[uint32_t; 16]

Counter value register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TSTAMP

uint32_t

Timestamp register

TSTAMPColdResetValue

uint32_t

Timestamp register

TSTAMPForcedBits

uint32_t

Timestamp register

TSTAMPForcedFlippedBits

uint32_t

Timestamp register

TSTAMPReadMask

uint32_t

Timestamp register

TSTAMPResetMask

uint32_t

Timestamp register

TSTAMPResetValue

uint32_t

Timestamp register

TSTAMPWriteMask

uint32_t

Timestamp register

TimeSource

*void

Time source object

apb.pnp.bar

uint32_t

apb.pnp.config

uint32_t

config.littleEndian

uint8_t

Endianess of memory interface.

Interfaces

Name	Type	Description
ApbIface	ApbIface
DeviceIface	DeviceIface
MemAccessIface	MemAccessIface
RegisterIface	temu::RegisterIface	Auto-generated Register Interface Impl.
ResetIface	ResetIface

Name

Type

Description

ApbIface

DeviceIface

MemAccessIface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

Registers

Register Bank Regs

Register TSTAMP

Description: Timestamp register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
TSTAMP	`0xffffffff`	`0x0`	Timestamp

TSTAMP

0xffffffff

0x0

Timestamp

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CVAL

Description: Counter value register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CVAL	`0xffffffff`	`0x0`	Counter value

CVAL

0xffffffff

0x0

Counter value

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CCTRL

Description: Counter control register
Reset value: 0x37fc0000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
NCPU	`0xf0000000`	`0x3`	Number of supported processors minus one
NCNT	`0x0f800000`	`0xf`	Number of implemented counters minus one
MC	`0x00400000`	`0x1`	Maximum count support
IA	`0x00200000`	`0x1`	Internal AHB count support
DS	`0x00100000`	`0x1`	DSU support
EE	`0x00080000`	`0x1`	External event support
AE	`0x00040000`	`0x1`	AHBTRACE event support
EL	`0x00020000`	`0x0`	Event level
CD	`0x00010000`	`0x0`	Count maximum duration
SU	`0x0000c000`	`0x0`	Supervisor/User mode filter
CL	`0x00002000`	`0x0`	Clear counter on read
EN	`0x00001000`	`0x0`	Enable counter
EVENT	`0x00000ff0`	`0x0`	Event ID to be counted
CPU_AHBM	`0x0000000f`	`0x0`	CPU or AHB master to monitor

NCPU

0xf0000000

0x3

Number of supported processors minus one

NCNT

0x0f800000

0xf

Number of implemented counters minus one

0x00400000

0x1

Maximum count support

0x00200000

0x1

Internal AHB count support

0x00100000

0x1

DSU support

0x00080000

0x1

External event support

0x00040000

0x1

AHBTRACE event support

0x00020000

0x0

Event level

0x00010000

0x0

Count maximum duration

0x0000c000

0x0

Supervisor/User mode filter

0x00002000

0x0

Clear counter on read

0x00001000

0x0

Enable counter

EVENT

0x00000ff0

0x0

Event ID to be counted

CPU_AHBM

0x0000000f

0x0

CPU or AHB master to monitor

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

Field	Mask	Reset	Description
CSVAL	`0xffffffff`	`0x0`	Counter max/latch value

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

CSVAL

0xffffffff

0x0

Counter max/latch value

Register CSVAL

Description: Counter max/latch register
Reset value: 0x00000000
Warm reset mask: 0xffffffff

Field Mask Reset Description

CSVAL

0xffffffff

0x0

Counter max/latch value

Commands

Name

Description

delete

Dispose instance of L4STAT

Limitations

The L4STAT device is non-functional, providing only registers and PNP data. Statistics is thus not collected by the device.

The end user is expected to write to registers manually, in order to inject statistics data.