GRLIB GPTIMER Model

The GPTIMER is part of the GRLIB device library from Gaisler. The timer runs using synchronised events in order to ensure that would a timer tick be broadcasted by the interrupt controller, then the IRQ should be taken at roughly the same time.

Loading the Plugin

import GpTimer

Configuration

Separate Interrupts

Set the "config.separateInterrupts" property to non-zero.

Interrupt Index

The interrupt number can be set by configuring the "pnp.config" property. The lower 5 bits of the property is used for this.

Number of Timers

Set the "config.numTimers" property. By default this value is 4 to be compatible with the UT699.

Clear IRQ on Set

Set the "config.clearIrqOnSet" property changes the behaviour of bit 4 in the timer control registers. ClearOnSet can be non-zero (the default), in that case writing a 1 to the bit will clear bit 4 (i.e. it will read out as 0), if clearOnSet is zero, the bit is cleared if bit 4 is 0 in the written word.

The reason for this are ambiguities in the LEON3 and UT699 manuals.

@GpTimer Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GpTimer

new

Create new instance of GpTimer

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GpTimer Reference

Properties

Name Type Description

CONFIGColdResetValue

uint32_t

Configuration register

CONFIGForcedBits

uint32_t

Configuration register

CONFIGForcedFlippedBits

uint32_t

Configuration register

CONFIGReadMask

uint32_t

Configuration register

CONFIGResetMask

uint32_t

Configuration register

CONFIGResetValue

uint32_t

Configuration register

CONFIGWriteMask

uint32_t

Configuration register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LATCHCFGColdResetValue

uint32_t

Timer latch configuration register

LATCHCFGForcedBits

uint32_t

Timer latch configuration register

LATCHCFGForcedFlippedBits

uint32_t

Timer latch configuration register

LATCHCFGReadMask

uint32_t

Timer latch configuration register

LATCHCFGResetMask

uint32_t

Timer latch configuration register

LATCHCFGResetValue

uint32_t

Timer latch configuration register

LATCHCFGWriteMask

uint32_t

Timer latch configuration register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

SCALERColdResetValue

uint32_t

Scaler value register

SCALERForcedBits

uint32_t

Scaler value register

SCALERForcedFlippedBits

uint32_t

Scaler value register

SCALERReadMask

uint32_t

Scaler value register

SCALERResetMask

uint32_t

Scaler value register

SCALERResetValue

uint32_t

Scaler value register

SCALERWriteMask

uint32_t

Scaler value register

SRELOADColdResetValue

uint32_t

Scaler reload value register

SRELOADForcedBits

uint32_t

Scaler reload value register

SRELOADForcedFlippedBits

uint32_t

Scaler reload value register

SRELOADReadMask

uint32_t

Scaler reload value register

SRELOADResetMask

uint32_t

Scaler reload value register

SRELOADResetValue

uint32_t

Scaler reload value register

SRELOADWriteMask

uint32_t

Scaler reload value register

TimeSource

*void

Time source object

config.clearIrqOnSet

uint8_t

Use behaviour in GRIP manual. Set to zero for beahviour as documented in (UT699 manual from 2012 (p77).

config.clockDivider

uint32_t

Clock divider for scaling event posting

config.irqNumber

uint8_t

Set interrupt number for first interrupt

config.littleEndian

uint8_t

Endianess of memory interface.

config.numTimers

uint8_t

config.separateInterrupts

uint8_t

Enable separate interrupts

config.traceInterrupts

uint8_t

config.traceReads

uint8_t

config.traceWrites

uint8_t

config.underflowNotificationMask

uint32_t

configReg

uint32_t

Configuration register

control

[uint32_t; 7]

Timer control register

counters

[uint32_t; 7]

Timer counter value register

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller.

latchConfigReg

uint32_t

Timer latch configuration register

latchReg

[uint32_t; 7]

Timer latch register

pnp.bar

uint32_t

pnp.config

uint32_t

reload

[uint32_t; 7]

Timer reload value register

scaler

uint32_t

Scaler value register

scalerReload

uint32_t

Scaler reload value register

stats.interruptsRaised

[uint64_t; 32]

Interfaces

Name Type Description

ApbIface

ApbIface

DeviceIface

DeviceIface

MemAccessIface

MemAccessIface

ObjectIface

ObjectIface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Registers

Register support is currently experimental!

Register Bank Regs

Register SCALER
Description

Scaler value register

Reset value

0x0000ffff

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

SCALER

0x0000ffff

0xffff

Scaler value
Register SRELOAD
Description

Scaler reload value register

Reset value

0x0000ffff

Warm reset mask

0x0000ffff

Diagram
Field Mask Reset Description

SRELOAD

0x0000ffff

0xffff

Scaler reload value
Register CONFIG
Description

Configuration register

Reset value

0x00000200

Warm reset mask

0x00003fff

Diagram
Field Mask Reset Description

EV

0x00002000

0x0

External events

ES

0x00001000

0x0

Enable set

EL

0x00000800

0x0

Enable latching

EE

0x00000400

0x0

Enable external clock source

DF

0x00000200

0x1

Disable timer freeze

SI

0x00000100

0x0

Separate interrupts

IRQ

0x000000f8

0x0

APB interrupt

TIMERS

0x00000007

0x0

Number of implemented timers
Register LATCHCFG
Description

Timer latch configuration register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LATCHSEL

0xffffffff

0x0

Latch select
Register TCNTVAL
Description

Timer counter value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TCVAL

0xffffffff

0x0

Timer counter value
Register TCNTVAL
Description

Timer counter value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TCVAL

0xffffffff

0x0

Timer counter value
Register TCNTVAL
Description

Timer counter value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TCVAL

0xffffffff

0x0

Timer counter value
Register TCNTVAL
Description

Timer counter value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TCVAL

0xffffffff

0x0

Timer counter value
Register TCNTVAL
Description

Timer counter value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TCVAL

0xffffffff

0x0

Timer counter value
Register TCNTVAL
Description

Timer counter value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TCVAL

0xffffffff

0x0

Timer counter value
Register TCNTVAL
Description

Timer counter value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TCVAL

0xffffffff

0x0

Timer counter value
Register TRLDVAL
Description

Timer reload value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TRLDVAL

0xffffffff

0x0

Timer reload value
Register TRLDVAL
Description

Timer reload value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TRLDVAL

0xffffffff

0x0

Timer reload value
Register TRLDVAL
Description

Timer reload value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TRLDVAL

0xffffffff

0x0

Timer reload value
Register TRLDVAL
Description

Timer reload value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TRLDVAL

0xffffffff

0x0

Timer reload value
Register TRLDVAL
Description

Timer reload value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TRLDVAL

0xffffffff

0x0

Timer reload value
Register TRLDVAL
Description

Timer reload value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TRLDVAL

0xffffffff

0x0

Timer reload value
Register TRLDVAL
Description

Timer reload value register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

TRLDVAL

0xffffffff

0x0

Timer reload value
Register TCTRL
Description

Timer control register

Reset value

0x00000000

Warm reset mask

0x000001ef

Diagram
Field Mask Reset Description

WS

0x00000100

0x0

Disable watchdog output

WN

0x00000080

0x0

Enable watchdog NMI

DH

0x00000040

0x0

Debug halt

CH

0x00000020

0x0

Chain with preceding timer

IP

0x00000010

-

Interrupt pending

IE

0x00000008

0x0

Interrupt enable

LD

0x00000004

0x0

Load

RS

0x00000002

0x0

Restart

EN

0x00000001

0x0

Enable
Register TCTRL
Description

Timer control register

Reset value

0x00000000

Warm reset mask

0x000001ef

Diagram
Field Mask Reset Description

WS

0x00000100

0x0

Disable watchdog output

WN

0x00000080

0x0

Enable watchdog NMI

DH

0x00000040

0x0

Debug halt

CH

0x00000020

0x0

Chain with preceding timer

IP

0x00000010

-

Interrupt pending

IE

0x00000008

0x0

Interrupt enable

LD

0x00000004

0x0

Load

RS

0x00000002

0x0

Restart

EN

0x00000001

0x0

Enable
Register TCTRL
Description

Timer control register

Reset value

0x00000000

Warm reset mask

0x000001ef

Diagram
Field Mask Reset Description

WS

0x00000100

0x0

Disable watchdog output

WN

0x00000080

0x0

Enable watchdog NMI

DH

0x00000040

0x0

Debug halt

CH

0x00000020

0x0

Chain with preceding timer

IP

0x00000010

-

Interrupt pending

IE

0x00000008

0x0

Interrupt enable

LD

0x00000004

0x0

Load

RS

0x00000002

0x0

Restart

EN

0x00000001

0x0

Enable
Register TCTRL
Description

Timer control register

Reset value

0x00000000

Warm reset mask

0x000001ef

Diagram
Field Mask Reset Description

WS

0x00000100

0x0

Disable watchdog output

WN

0x00000080

0x0

Enable watchdog NMI

DH

0x00000040

0x0

Debug halt

CH

0x00000020

0x0

Chain with preceding timer

IP

0x00000010

-

Interrupt pending

IE

0x00000008

0x0

Interrupt enable

LD

0x00000004

0x0

Load

RS

0x00000002

0x0

Restart

EN

0x00000001

0x0

Enable
Register TCTRL
Description

Timer control register

Reset value

0x00000000

Warm reset mask

0x000001ef

Diagram
Field Mask Reset Description

WS

0x00000100

0x0

Disable watchdog output

WN

0x00000080

0x0

Enable watchdog NMI

DH

0x00000040

0x0

Debug halt

CH

0x00000020

0x0

Chain with preceding timer

IP

0x00000010

-

Interrupt pending

IE

0x00000008

0x0

Interrupt enable

LD

0x00000004

0x0

Load

RS

0x00000002

0x0

Restart

EN

0x00000001

0x0

Enable
Register TCTRL
Description

Timer control register

Reset value

0x00000000

Warm reset mask

0x000001ef

Diagram
Field Mask Reset Description

WS

0x00000100

0x0

Disable watchdog output

WN

0x00000080

0x0

Enable watchdog NMI

DH

0x00000040

0x0

Debug halt

CH

0x00000020

0x0

Chain with preceding timer

IP

0x00000010

-

Interrupt pending

IE

0x00000008

0x0

Interrupt enable

LD

0x00000004

0x0

Load

RS

0x00000002

0x0

Restart

EN

0x00000001

0x0

Enable
Register TCTRL
Description

Timer control register

Reset value

0x00000000

Warm reset mask

0x000001ef

Diagram
Field Mask Reset Description

WS

0x00000100

0x0

Disable watchdog output

WN

0x00000080

0x0

Enable watchdog NMI

DH

0x00000040

0x0

Debug halt

CH

0x00000020

0x0

Chain with preceding timer

IP

0x00000010

-

Interrupt pending

IE

0x00000008

0x0

Interrupt enable

LD

0x00000004

0x0

Load

RS

0x00000002

0x0

Restart

EN

0x00000001

0x0

Enable
Register TLATCH
Description

Timer latch register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LTCV

0xffffffff

0x0

Latched timer counter value
Register TLATCH
Description

Timer latch register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LTCV

0xffffffff

0x0

Latched timer counter value
Register TLATCH
Description

Timer latch register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LTCV

0xffffffff

0x0

Latched timer counter value
Register TLATCH
Description

Timer latch register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LTCV

0xffffffff

0x0

Latched timer counter value
Register TLATCH
Description

Timer latch register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LTCV

0xffffffff

0x0

Latched timer counter value
Register TLATCH
Description

Timer latch register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LTCV

0xffffffff

0x0

Latched timer counter value
Register TLATCH
Description

Timer latch register

Reset value

0x00000000

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

LTCV

0xffffffff

0x0

Latched timer counter value

Commands

Name Description

delete

Dispose instance of GpTimer

Limitations

The following deviations from real hardware are known to exist with this model:

  • The Disable Timer Freeze bit is always 1 and cannot be configured.

  • The Debug Halt bit for each timer is always 0 and cannot be altered.

  • The last timer does not work as a watchdog.

  • The timer utilize synchronized events. The minimum time for a timer expiration on a multi-core CPU, will thus be equal to the time-quanta of the machine.