GRLIB GPTIMER Model
The GPTIMER is part of the GRLIB device library from Gaisler. The timer runs using synchronised events in order to ensure that would a timer tick be broadcasted by the interrupt controller, then the IRQ should be taken at roughly the same time.
Configuration
Interrupt Index
The interrupt number can be set by configuring the "pnp.config" property. The lower 5 bits of the property is used for this.
Number of Timers
Set the "config.numTimers" property. By default this value is 4 to be compatible with the UT699.
Clear IRQ on Set
Set the "config.clearIrqOnSet" property changes the behaviour of bit 4 in the timer control registers. ClearOnSet can be non-zero (the default), in that case writing a 1 to the bit will clear bit 4 (i.e. it will read out as 0), if clearOnSet is zero, the bit is cleared if bit 4 is 0 in the written word.
The reason for this are ambiguities in the LEON3 and UT699 manuals.
@GpTimer Reference
GpTimer Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
TimeSource |
*void |
Time source object |
config.clearIrqOnSet |
uint8_t |
Use behaviour in GRIP manual. Set to zero for beahviour as documented in (UT699 manual from 2012 (p77). |
config.clockDivider |
uint32_t |
Clock divider for scaling event posting |
config.irqNumber |
uint8_t |
Set interrupt number for first interrupt |
config.numTimers |
uint8_t |
|
config.separateInterrupts |
uint8_t |
Enable separate interrupts |
config.traceInterrupts |
uint8_t |
|
config.traceReads |
uint8_t |
|
config.traceWrites |
uint8_t |
|
config.underflowNotificationMask |
uint32_t |
|
configReg |
uint32_t |
|
control |
[uint32_t; 7] |
|
counters |
[uint32_t; 7] |
|
irqCtrl |
temu_IfaceRef/ <unknown> |
Interrupt controller. |
latchConfigReg |
uint32_t |
|
latchReg |
[uint32_t; 7] |
|
pnp.bar |
uint32_t |
|
pnp.config |
uint32_t |
|
reload |
[uint32_t; 7] |
|
scaler |
uint32_t |
|
scalerReload |
uint32_t |
|
stats.interruptsRaised |
[uint64_t; 32] |
Interfaces
| Name | Type | Description |
|---|---|---|
ApbIface |
ApbIface |
|
DeviceIface |
DeviceIface |
|
MemAccessIface |
MemAccessIface |
|
ObjectIface |
ObjectIface |
|
ResetIface |
ResetIface |
Registers
| Register support is currently experimental! |
Register Bank default
Register configReg
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register control
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register counters
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register latchConfigReg
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register latchReg
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Register reload
- Description
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
- |
- |
- |
- |
Limitations
The following deviations from real hardware are known to exist with this model:
-
The Disable Timer Freeze bit is always 1 and cannot be configured.
-
The Debug Halt bit for each timer is always 0 and cannot be altered.
-
The last timer does not work as a watchdog.
-
The timer utilize synchronized events. The minimum time for a timer expiration on a multi-core CPU, will thus be equal to the time-quanta of the machine.