P2020 eTSEC Model
This section describes the P2020 eTSEC Ethernet controller model.
The eTSECs of the device include these distinctive features:
-
TCP/IP off-load:
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IP v4 and IP v6 header recognition on receive;
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IP v4 header checksum verification and generation;
-
TCP and UDP checksum verification and generation;
-
Per-packet configurable off-load.
-
-
Support for different Ethernet physical interfaces (MII, GMII, RMII, RGMII, TBI and RTBI.).
Configuration
- config.interfaceMode
-
Interface Mode (MII 10/100 Mbps, RMII 100 Mbps, RMII 10 Mbps, GMII 1Gbps, etc).
The GenericPHY is a PHY / MII device which supports both the MDIO interface and the PHY interface for sending/receiving ethernet frames. It is connected to MDIO bus via MDIOIface and to eTSEC via PHYIface. An ethernet link must be connected to its attached PHYs via EthernetIface;
The MDIO bus distributes MDIO control messages and supports routing of them. The MDIO bus use the same interface as an MDIO device. It is connected to eTSEC via MDIOIface.
Before starting the communications all mentioned above models should be created and connected as follows:
// connect MDIO bus with MAC controller and PHY circuit.
temu_connect(miibus, "macDevice", etsec, "MACIface");
temu_connect(miibus, "phyDevices", phy, "MDIOIface");
// connect eTSEC with MDIO bus and PHY
temu_connect(etsec, "mdioBus", miibus, "MDIOIface");
temu_connect(etsec, "phy", phy, "PHYIface");
// connect MAC device to PHY
temu_connect(phy, "macDevice", etsec, "MACIface");
// connect ethernet link
temu_connect(phy, "ethernetLink", ethlink, "EthernetIface");# connect MDIO bus with MAC controller and PHY circuit.
connect a=miibus.macDevice b=etsec:MACIface
connect a=miibus.phyDevices b=phy:MDIOIface
# connect eTSEC with MDIO bus and PHY
connect a=etsec.mdioBus b=miibus:MDIOIface
connect a=etsec.phy b=phy:PHYIface
# connect MAC device to PHY
connect a=phy.macDevice b=etsec:MACIface
# connect ethernet link
connect a=phy.ethernetLink b=ethlink:EthernetIfaceAn ethernet link must be connected to its attached PHYs.
Connection is done using the connect command.
ethlink.connect device=phy:PHYIfaceThe eTSEC programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. All the eTSEC registers are 4-byte wide.
To set MAC address MACSTNADDR1 and MACSTNADDR2 registers should be filled. The value of the station address written into MACSTNADDR1 and MACSTNADDR2 is byte reversed from how it would appear in the DA field of a frame in memory. For example, for a station address of 0x12345678ABCD, MACSTNADDR1 is set to 0xCDAB7856 and MACSTNADDR2 is set to 0x34120000.
// Write MACSTNADDR1 register value to set MAC to 00:00:00:00:00:01
temu_writeValueU32(etsec, "MACSTNADDR1", 0x01000000, 0);# Write MACSTNADDR1 register value to set MAC to 00:00:00:00:00:01
etsec.MACSTNADDR1 = 0x01000000MAC address also can be set via setMAC command:
etsec.setMAC mac=\"00:00:00:00:00:01\"@eTSEC Reference
eTSEC Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
ETSEC_1588_TMR_ACC |
uint32_t |
Timer accumulator register |
ETSEC_1588_TMR_ADD |
uint32_t |
Timer rift compensation addend register |
ETSEC_1588_TMR_ALARM_H |
[uint32_t; 2] |
Timer offset high register |
ETSEC_1588_TMR_ALARM_L |
[uint32_t; 2] |
Timer offset low register |
ETSEC_1588_TMR_CNT_H |
uint32_t |
Timer counter high register |
ETSEC_1588_TMR_CNT_L |
uint32_t |
Timer counter low register |
ETSEC_1588_TMR_CTRL |
uint32_t |
Timer control register |
ETSEC_1588_TMR_ETTS_H |
[uint32_t; 2] |
Time stamp of general purpose external trigger(high) |
ETSEC_1588_TMR_ETTS_L |
[uint32_t; 2] |
Time stamp of general purpose external trigger(low) |
ETSEC_1588_TMR_FIPER |
[uint32_t; 2] |
Timer fixed period interval |
ETSEC_1588_TMR_PEMASK |
uint32_t |
Timer event mask register |
ETSEC_1588_TMR_PEVENT |
uint32_t |
Timer event mask register |
ETSEC_1588_TMR_PRSC |
uint32_t |
Timer prescale |
ETSEC_1588_TMR_STAT |
uint32_t |
Time stamp status register |
ETSEC_1588_TMR_TEMASK |
uint32_t |
Timer event mask register |
ETSEC_1588_TMR_TEVENT |
uint32_t |
Time stamp event register |
ETSEC_1588_TMR_TMROFF_H |
uint32_t |
Timer offset high register |
ETSEC_1588_TMR_TMROFF_L |
uint32_t |
Timer offset low register |
ETSEC_ATTR |
uint32_t |
ETSEC DMA Attribute register |
ETSEC_ATTRELI |
uint32_t |
ETSEC DMA Attribute extract length and extract index register |
ETSEC_CAM |
[uint32_t; 2] |
ETSEC Carry registers(0,1) mask |
ETSEC_CAR |
[uint32_t; 2] |
ETSEC Carry registers(0,1) |
ETSEC_DFVLAN |
uint32_t |
ETSEC Default VLAN control word |
ETSEC_DMACTRL |
uint32_t |
ETSEC DMA control register |
ETSEC_ECNTRL |
uint32_t |
ETSEC Ethernet control register |
ETSEC_EDIS |
uint32_t |
ETSEC Error disabled register |
ETSEC_GADDR |
[uint32_t; 16] |
ETSEC group address register n |
ETSEC_HAFDUP |
uint32_t |
ETSEC Half-duplex control register |
ETSEC_IEVENT |
uint32_t |
ETSEC Interrupt event register |
ETSEC_IFSTAT |
uint32_t |
ETSEC Interface status |
ETSEC_IGADDR |
[uint32_t; 16] |
ETSEC Individual/group address register n |
ETSEC_IMASK |
uint32_t |
ETSEC Interrupt mask register |
ETSEC_IPGIFG |
uint32_t |
ETSEC Inter-packet/inter-frame gap register |
ETSEC_MACCFG |
[uint32_t; 2] |
ETSEC MAC configuration register (0-1) |
ETSEC_MACSTNADDR |
[uint32_t; 2] |
ETSEC MAC station address registers |
ETSEC_MACnADDR1 |
[uint32_t; 16] |
ETSEC MAC exact match address n, part 1 |
ETSEC_MACnADDR2 |
[uint32_t; 16] |
ETSEC MAC exact match address n, part 2 |
ETSEC_MAXFRM |
uint32_t |
ETSEC Maximum frame length |
ETSEC_MIIMADD |
uint32_t |
ETSEC MII management address |
ETSEC_MIIMCFG |
uint32_t |
ETSEC MII management configuration |
ETSEC_MIIMCOM |
uint32_t |
ETSEC MII management command |
ETSEC_MIIMCON |
uint32_t |
ETSEC MII management control |
ETSEC_MIIMIND |
uint32_t |
ETSEC MII management indicator |
ETSEC_MIIMSTAT |
uint32_t |
ETSEC MII management status |
ETSEC_MRBLR |
uint32_t |
ETSEC Maximum receive buffer length register |
ETSEC_PVT |
uint32_t |
ETSEC Pause time value register |
ETSEC_RALN |
uint32_t |
ETSEC Receive alignment error counter |
ETSEC_RBASE |
[uint32_t; 8] |
ETSEC base address of ring n |
ETSEC_RBASEH |
uint32_t |
ETSEC RxBD base address high bits |
ETSEC_RBCA |
uint32_t |
ETSEC Receive broadcast packet counter |
ETSEC_RBDBPH |
uint32_t |
ETSEC Rx data buffer pointer high bits register |
ETSEC_RBIFX |
uint32_t |
ETSEC Receive bit field extract control register |
ETSEC_RBPTR |
[uint32_t; 8] |
ETSEC RxBD pointer for ring n |
ETSEC_RBYT |
uint32_t |
ETSEC Receive byte counter |
ETSEC_RCDE |
uint32_t |
ETSEC Receive code error counter |
ETSEC_RCSE |
uint32_t |
ETSEC Receive carrier sense error counter |
ETSEC_RCTRL |
uint32_t |
ETSEC Receive control register |
ETSEC_RDRP |
uint32_t |
ETSEC Receive drop counter |
ETSEC_RFBPTR |
[uint32_t; 8] |
ETSEC Receive Queue Parameters register n |
ETSEC_RFCS |
uint32_t |
ETSEC Receive FCS error counter |
ETSEC_RFLR |
uint32_t |
ETSEC Receive frame length error counter |
ETSEC_RFRG |
uint32_t |
ETSEC Receive fragments counter |
ETSEC_RJBR |
uint32_t |
ETSEC Receive jabber counter |
ETSEC_RMCA |
uint32_t |
ETSEC Receive multicast packet counter |
ETSEC_ROVR |
uint32_t |
ETSEC Receive oversize packet counter |
ETSEC_RPKT |
uint32_t |
ETSEC Receive packet counter |
ETSEC_RQFAR |
uint32_t |
ETSEC Receive queue filing table address register |
ETSEC_RQFCR |
uint32_t |
ETSEC Receive queue filing table control register |
ETSEC_RQFPR |
uint32_t |
ETSEC Receive queue filing table property register |
ETSEC_RQPRM |
[uint32_t; 8] |
ETSEC Receive Queue Parameters register n |
ETSEC_RQUEUE |
uint32_t |
ETSEC Receive queue control register |
ETSEC_RREJ |
uint32_t |
ETSEC Receive filer rejected packet counter |
ETSEC_RSTAT |
uint32_t |
ETSEC Receive status register |
ETSEC_RUND |
uint32_t |
ETSEC Receive undersize packet counter |
ETSEC_RXCF |
uint32_t |
ETSEC Receive control frame packet counter |
ETSEC_RXIC |
uint32_t |
ETSEC Receive interrupt coalescing register |
ETSEC_RXPF |
uint32_t |
ETSEC Receive PAUSE frame packet counter |
ETSEC_RXUO |
uint32_t |
ETSEC Receive unknown OP code counter |
ETSEC_TBASE |
[uint32_t; 8] |
ETSEC TxBD base address of ring n |
ETSEC_TBASEH |
uint32_t |
ETSEC TxBD base address high bits |
ETSEC_TBCA |
uint32_t |
ETSEC Transmit broadcast packet counter |
ETSEC_TBDBPH |
uint32_t |
ETSEC Tx data buffer pointer high bits |
ETSEC_TBIPA |
uint32_t |
ETSEC TBI PHY address register |
ETSEC_TBPTR |
[uint32_t; 8] |
ETSEC TxBD pointer for ring n |
ETSEC_TBYT |
uint32_t |
ETSEC Transmit byte counter |
ETSEC_TCTRL |
uint32_t |
ETSEC Transmit control register |
ETSEC_TDRF |
uint32_t |
ETSEC Transmit deferral packet counter |
ETSEC_TDRP |
uint32_t |
ETSEC Transmit drop frame counter |
ETSEC_TEDF |
uint32_t |
ETSEC Transmit excessive deferral packet counter |
ETSEC_TFCS |
uint32_t |
ETSEC Transmit FCS error counter |
ETSEC_TFRG |
uint32_t |
ETSEC Transmit fragments frame counter |
ETSEC_TJBR |
uint32_t |
ETSEC Transmit jabber frame counter |
ETSEC_TLCL |
uint32_t |
ETSEC Transmit late collision packet counter |
ETSEC_TMCA |
uint32_t |
ETSEC Transmit multicast packet counter |
ETSEC_TMCL |
uint32_t |
ETSEC Transmit multi collision packet counter |
ETSEC_TMR_RXTS_H |
uint32_t |
ETSEC Rx timer time stamp register high |
ETSEC_TMR_RXTS_L |
uint32_t |
ETSEC Rx timer time stamp register low |
ETSEC_TMR_TXTS_H |
[uint32_t; 2] |
ETSEC Tx Tx time stamp high |
ETSEC_TMR_TXTS_ID |
[uint32_t; 2] |
ETSEC Tx time stamp identification tag (set n) register |
ETSEC_TMR_TXTS_L |
[uint32_t; 2] |
ETSEC Tx Tx time stamp low |
ETSEC_TNCL |
uint32_t |
ETSEC Transmit total collision packet counter |
ETSEC_TOVR |
uint32_t |
ETSEC Transmit oversize frame counter |
ETSEC_TPKT |
uint32_t |
ETSEC Transmit packet counter |
ETSEC_TQUEUE |
uint32_t |
ETSEC Transmit queue control register |
ETSEC_TR03WT |
uint32_t |
ETSEC TxBD Rings 0-3 round-robin weightings |
ETSEC_TR127 |
uint32_t |
ETSEC Transmit and receive 65- to 127-byte frame counter |
ETSEC_TR1K |
uint32_t |
ETSEC Transmit and receive 512- to 1023-byte frame counter |
ETSEC_TR255 |
uint32_t |
ETSEC Transmit and receive 128- to 255-byte frame counter |
ETSEC_TR47WT |
uint32_t |
ETSEC TxBD Rings 4-7 round-robin weightings |
ETSEC_TR511 |
uint32_t |
ETSEC Transmit and receive 256- to 511-byte frame counter |
ETSEC_TR64 |
uint32_t |
ETSEC Transmit and receive 64-byte frame counter |
ETSEC_TRMAX |
uint32_t |
ETSEC Transmit and receive 1024- to 1518-byte frame counter |
ETSEC_TSCL |
uint32_t |
ETSEC Transmit single collision packet counter |
ETSEC_TSEC_ID |
[uint32_t; 2] |
ETSEC Controller ID registers (0, 1) |
ETSEC_TSTAT |
uint32_t |
ETSEC Transmit status register |
ETSEC_TUND |
uint32_t |
ETSEC Transmit undersize frame counter |
ETSEC_TXCF |
uint32_t |
ETSEC Transmit control frame counter |
ETSEC_TXCL |
uint32_t |
ETSEC Transmit excessive collision packet counter |
ETSEC_TXIC |
uint32_t |
ETSEC Transmit interrupt coalescing register |
ETSEC_TXPF |
uint32_t |
ETSEC Transmit PAUSE control frame counter |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
TimeSource |
*void |
Time source object |
config.checkCrc |
uint8_t |
Enable ethernet frame CRC checking. |
config.generateCrc |
uint8_t |
Enable ethernet frame CRC generation. |
config.interfaceMode |
uint8_t |
Set interface mode |
config.irqError |
uint8_t |
IRQ number for eTSEC error |
config.irqReceive |
uint8_t |
IRQ number for eTSEC receieve event |
config.irqTransmit |
uint8_t |
IRQ number for eTSEC transmit event |
config.logTraffic |
uint8_t |
Enable traffic logging |
irqCtrl |
temu_IfaceRef/ <unknown> |
IRQ controller |
mac |
*char |
Set MAC by string |
mdioBus |
temu_IfaceRef/ <unknown> |
MDIO bus |
memAccess |
temu_IfaceRef/ <unknown> |
Memory access (for DMA). |
memory |
temu_IfaceRef/ <unknown> |
Memory |
phy |
temu_IfaceRef/ <unknown> |
PHY device |