P2020 eTSEC Model
This section describes the P2020 eTSEC Ethernet controller model.
The eTSECs of the device include these distinctive features:
-
TCP/IP off-load:
-
IP v4 and IP v6 header recognition on receive;
-
IP v4 header checksum verification and generation;
-
TCP and UDP checksum verification and generation;
-
Per-packet configurable off-load.
-
-
Support for different Ethernet physical interfaces (MII, GMII, RMII, RGMII, TBI and RTBI.).
Configuration
- config.interfaceMode
-
Interface Mode (MII 10/100 Mbps, RMII 100 Mbps, RMII 10 Mbps, GMII 1Gbps, etc).
The GenericPHY is a PHY / MII device which supports both the MDIO interface and the PHY interface for sending/receiving ethernet frames. It is connected to MDIO bus via MDIOIface and to eTSEC via PHYIface. An ethernet link must be connected to its attached PHYs via EthernetIface;
The MDIO bus distributes MDIO control messages and supports routing of them. The MDIO bus use the same interface as an MDIO device. It is connected to eTSEC via MDIOIface.
Before starting the communications all mentioned above models should be created and connected as follows:
// connect MDIO bus with MAC controller and PHY circuit.
temu_connect(miibus, "macDevice", etsec, "MACIface");
temu_connect(miibus, "phyDevices", phy, "MDIOIface");
// connect eTSEC with MDIO bus and PHY
temu_connect(etsec, "mdioBus", miibus, "MDIOIface");
temu_connect(etsec, "phy", phy, "PHYIface");
// connect MAC device to PHY
temu_connect(phy, "macDevice", etsec, "MACIface");
// connect ethernet link
temu_connect(phy, "ethernetLink", ethlink, "EthernetIface");# connect MDIO bus with MAC controller and PHY circuit.
connect a=miibus.macDevice b=etsec:MACIface
connect a=miibus.phyDevices b=phy:MDIOIface
# connect eTSEC with MDIO bus and PHY
connect a=etsec.mdioBus b=miibus:MDIOIface
connect a=etsec.phy b=phy:PHYIface
# connect MAC device to PHY
connect a=phy.macDevice b=etsec:MACIface
# connect ethernet link
connect a=phy.ethernetLink b=ethlink:EthernetIfaceAn ethernet link must be connected to its attached PHYs.
Connection is done using the connect command.
ethlink.connect device=phy:PHYIfaceThe eTSEC programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. All the eTSEC registers are 4-byte wide.
To set MAC address MACSTNADDR1 and MACSTNADDR2 registers should be filled. The value of the station address written into MACSTNADDR1 and MACSTNADDR2 is byte reversed from how it would appear in the DA field of a frame in memory. For example, for a station address of 0x12345678ABCD, MACSTNADDR1 is set to 0xCDAB7856 and MACSTNADDR2 is set to 0x34120000.
// Write MACSTNADDR1 register value to set MAC to 00:00:00:00:00:01
temu_writeValueU32(etsec, "MACSTNADDR1", 0x01000000, 0);# Write MACSTNADDR1 register value to set MAC to 00:00:00:00:00:01
etsec.MACSTNADDR1 = 0x01000000MAC address also can be set via setMAC command:
etsec.setMAC mac=\"00:00:00:00:00:01\"@eTSEC Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
eTSEC Reference
Properties
| Name | Type | Description |
|---|---|---|
ATTR |
uint32_t |
Attribute register |
ATTRColdResetValue |
uint32_t |
Attribute register |
ATTRELI |
uint32_t |
Attribute extract length and extract index register |
ATTRELIColdResetValue |
uint32_t |
Attribute extract length and extract index register |
ATTRELIForcedBits |
uint32_t |
Attribute extract length and extract index register |
ATTRELIForcedFlippedBits |
uint32_t |
Attribute extract length and extract index register |
ATTRELIReadMask |
uint32_t |
Attribute extract length and extract index register |
ATTRELIResetMask |
uint32_t |
Attribute extract length and extract index register |
ATTRELIResetValue |
uint32_t |
Attribute extract length and extract index register |
ATTRELIWriteMask |
uint32_t |
Attribute extract length and extract index register |
ATTRForcedBits |
uint32_t |
Attribute register |
ATTRForcedFlippedBits |
uint32_t |
Attribute register |
ATTRReadMask |
uint32_t |
Attribute register |
ATTRResetMask |
uint32_t |
Attribute register |
ATTRResetValue |
uint32_t |
Attribute register |
ATTRWriteMask |
uint32_t |
Attribute register |
CAM |
[uint32_t; 2] |
Carry mask register |
CAR |
[uint32_t; 2] |
Carry register |
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
DFVLAN |
uint32_t |
Default VLAN control word |
DFVLANColdResetValue |
uint32_t |
Default VLAN control word |
DFVLANForcedBits |
uint32_t |
Default VLAN control word |
DFVLANForcedFlippedBits |
uint32_t |
Default VLAN control word |
DFVLANReadMask |
uint32_t |
Default VLAN control word |
DFVLANResetMask |
uint32_t |
Default VLAN control word |
DFVLANResetValue |
uint32_t |
Default VLAN control word |
DFVLANWriteMask |
uint32_t |
Default VLAN control word |
DMACTRL |
uint32_t |
DMA control register |
DMACTRLColdResetValue |
uint32_t |
DMA control register |
DMACTRLForcedBits |
uint32_t |
DMA control register |
DMACTRLForcedFlippedBits |
uint32_t |
DMA control register |
DMACTRLReadMask |
uint32_t |
DMA control register |
DMACTRLResetMask |
uint32_t |
DMA control register |
DMACTRLResetValue |
uint32_t |
DMA control register |
DMACTRLWriteMask |
uint32_t |
DMA control register |
ECNTRL |
uint32_t |
Ethernet control register |
ECNTRLColdResetValue |
uint32_t |
Ethernet control register |
ECNTRLForcedBits |
uint32_t |
Ethernet control register |
ECNTRLForcedFlippedBits |
uint32_t |
Ethernet control register |
ECNTRLReadMask |
uint32_t |
Ethernet control register |
ECNTRLResetMask |
uint32_t |
Ethernet control register |
ECNTRLResetValue |
uint32_t |
Ethernet control register |
ECNTRLWriteMask |
uint32_t |
Ethernet control register |
EDIS |
uint32_t |
Error disabled register |
EDISColdResetValue |
uint32_t |
Error disabled register |
EDISForcedBits |
uint32_t |
Error disabled register |
EDISForcedFlippedBits |
uint32_t |
Error disabled register |
EDISReadMask |
uint32_t |
Error disabled register |
EDISResetMask |
uint32_t |
Error disabled register |
EDISResetValue |
uint32_t |
Error disabled register |
EDISWriteMask |
uint32_t |
Error disabled register |
GADDR |
[uint32_t; 8] |
Group address register n |
HAFDUP |
uint32_t |
Half-duplex control register |
HAFDUPColdResetValue |
uint32_t |
Half-duplex control register |
HAFDUPForcedBits |
uint32_t |
Half-duplex control register |
HAFDUPForcedFlippedBits |
uint32_t |
Half-duplex control register |
HAFDUPReadMask |
uint32_t |
Half-duplex control register |
HAFDUPResetMask |
uint32_t |
Half-duplex control register |
HAFDUPResetValue |
uint32_t |
Half-duplex control register |
HAFDUPWriteMask |
uint32_t |
Half-duplex control register |
IEVENT |
uint32_t |
Interrupt event register |
IEVENTColdResetValue |
uint32_t |
Interrupt event register |
IEVENTForcedBits |
uint32_t |
Interrupt event register |
IEVENTForcedFlippedBits |
uint32_t |
Interrupt event register |
IEVENTReadMask |
uint32_t |
Interrupt event register |
IEVENTResetMask |
uint32_t |
Interrupt event register |
IEVENTResetValue |
uint32_t |
Interrupt event register |
IEVENTWriteMask |
uint32_t |
Interrupt event register |
IFSTAT |
uint32_t |
Interface status register |
IFSTATColdResetValue |
uint32_t |
Interface status register |
IFSTATForcedBits |
uint32_t |
Interface status register |
IFSTATForcedFlippedBits |
uint32_t |
Interface status register |
IFSTATReadMask |
uint32_t |
Interface status register |
IFSTATResetMask |
uint32_t |
Interface status register |
IFSTATResetValue |
uint32_t |
Interface status register |
IFSTATWriteMask |
uint32_t |
Interface status register |
IGADDR |
[uint32_t; 8] |
Individual/group address register n |
IMASK |
uint32_t |
Interrupt mask register |
IMASKColdResetValue |
uint32_t |
Interrupt mask register |
IMASKForcedBits |
uint32_t |
Interrupt mask register |
IMASKForcedFlippedBits |
uint32_t |
Interrupt mask register |
IMASKReadMask |
uint32_t |
Interrupt mask register |
IMASKResetMask |
uint32_t |
Interrupt mask register |
IMASKResetValue |
uint32_t |
Interrupt mask register |
IMASKWriteMask |
uint32_t |
Interrupt mask register |
IPGIFG |
uint32_t |
Inter-packet/inter-frame gap register |
IPGIFGColdResetValue |
uint32_t |
Inter-packet/inter-frame gap register |
IPGIFGForcedBits |
uint32_t |
Inter-packet/inter-frame gap register |
IPGIFGForcedFlippedBits |
uint32_t |
Inter-packet/inter-frame gap register |
IPGIFGReadMask |
uint32_t |
Inter-packet/inter-frame gap register |
IPGIFGResetMask |
uint32_t |
Inter-packet/inter-frame gap register |
IPGIFGResetValue |
uint32_t |
Inter-packet/inter-frame gap register |
IPGIFGWriteMask |
uint32_t |
Inter-packet/inter-frame gap register |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
MACCFG1 |
uint32_t |
MAC configuration register 1 |
MACCFG1ColdResetValue |
uint32_t |
MAC configuration register 1 |
MACCFG1ForcedBits |
uint32_t |
MAC configuration register 1 |
MACCFG1ForcedFlippedBits |
uint32_t |
MAC configuration register 1 |
MACCFG1ReadMask |
uint32_t |
MAC configuration register 1 |
MACCFG1ResetMask |
uint32_t |
MAC configuration register 1 |
MACCFG1ResetValue |
uint32_t |
MAC configuration register 1 |
MACCFG1WriteMask |
uint32_t |
MAC configuration register 1 |
MACCFG2 |
uint32_t |
MAC configuration register 2 |
MACCFG2ColdResetValue |
uint32_t |
MAC configuration register 2 |
MACCFG2ForcedBits |
uint32_t |
MAC configuration register 2 |
MACCFG2ForcedFlippedBits |
uint32_t |
MAC configuration register 2 |
MACCFG2ReadMask |
uint32_t |
MAC configuration register 2 |
MACCFG2ResetMask |
uint32_t |
MAC configuration register 2 |
MACCFG2ResetValue |
uint32_t |
MAC configuration register 2 |
MACCFG2WriteMask |
uint32_t |
MAC configuration register 2 |
MACSTNADDR1 |
uint32_t |
MAC station address register 1 |
MACSTNADDR1ColdResetValue |
uint32_t |
MAC station address register 1 |
MACSTNADDR1ForcedBits |
uint32_t |
MAC station address register 1 |
MACSTNADDR1ForcedFlippedBits |
uint32_t |
MAC station address register 1 |
MACSTNADDR1ReadMask |
uint32_t |
MAC station address register 1 |
MACSTNADDR1ResetMask |
uint32_t |
MAC station address register 1 |
MACSTNADDR1ResetValue |
uint32_t |
MAC station address register 1 |
MACSTNADDR1WriteMask |
uint32_t |
MAC station address register 1 |
MACSTNADDR2 |
uint32_t |
MAC station address register 2 |
MACSTNADDR2ColdResetValue |
uint32_t |
MAC station address register 2 |
MACSTNADDR2ForcedBits |
uint32_t |
MAC station address register 2 |
MACSTNADDR2ForcedFlippedBits |
uint32_t |
MAC station address register 2 |
MACSTNADDR2ReadMask |
uint32_t |
MAC station address register 2 |
MACSTNADDR2ResetMask |
uint32_t |
MAC station address register 2 |
MACSTNADDR2ResetValue |
uint32_t |
MAC station address register 2 |
MACSTNADDR2WriteMask |
uint32_t |
MAC station address register 2 |
MACnADDR1 |
[uint32_t; 15] |
MAC exact match address n, part 1 |
MACnADDR2 |
[uint32_t; 15] |
MAC exact match address n, part 2 |
MAXFRM |
uint32_t |
Maximum frame length register |
MAXFRMColdResetValue |
uint32_t |
Maximum frame length register |
MAXFRMForcedBits |
uint32_t |
Maximum frame length register |
MAXFRMForcedFlippedBits |
uint32_t |
Maximum frame length register |
MAXFRMReadMask |
uint32_t |
Maximum frame length register |
MAXFRMResetMask |
uint32_t |
Maximum frame length register |
MAXFRMResetValue |
uint32_t |
Maximum frame length register |
MAXFRMWriteMask |
uint32_t |
Maximum frame length register |
MIIMADD |
uint32_t |
MII management address register |
MIIMADDColdResetValue |
uint32_t |
MII management address register |
MIIMADDForcedBits |
uint32_t |
MII management address register |
MIIMADDForcedFlippedBits |
uint32_t |
MII management address register |
MIIMADDReadMask |
uint32_t |
MII management address register |
MIIMADDResetMask |
uint32_t |
MII management address register |
MIIMADDResetValue |
uint32_t |
MII management address register |
MIIMADDWriteMask |
uint32_t |
MII management address register |
MIIMCFG |
uint32_t |
MII management configuration register |
MIIMCFGColdResetValue |
uint32_t |
MII management configuration register |
MIIMCFGForcedBits |
uint32_t |
MII management configuration register |
MIIMCFGForcedFlippedBits |
uint32_t |
MII management configuration register |
MIIMCFGReadMask |
uint32_t |
MII management configuration register |
MIIMCFGResetMask |
uint32_t |
MII management configuration register |
MIIMCFGResetValue |
uint32_t |
MII management configuration register |
MIIMCFGWriteMask |
uint32_t |
MII management configuration register |
MIIMCOM |
uint32_t |
MII management command register |
MIIMCOMColdResetValue |
uint32_t |
MII management command register |
MIIMCOMForcedBits |
uint32_t |
MII management command register |
MIIMCOMForcedFlippedBits |
uint32_t |
MII management command register |
MIIMCOMReadMask |
uint32_t |
MII management command register |
MIIMCOMResetMask |
uint32_t |
MII management command register |
MIIMCOMResetValue |
uint32_t |
MII management command register |
MIIMCOMWriteMask |
uint32_t |
MII management command register |
MIIMCON |
uint32_t |
MII management control register |
MIIMCONColdResetValue |
uint32_t |
MII management control register |
MIIMCONForcedBits |
uint32_t |
MII management control register |
MIIMCONForcedFlippedBits |
uint32_t |
MII management control register |
MIIMCONReadMask |
uint32_t |
MII management control register |
MIIMCONResetMask |
uint32_t |
MII management control register |
MIIMCONResetValue |
uint32_t |
MII management control register |
MIIMCONWriteMask |
uint32_t |
MII management control register |
MIIMIND |
uint32_t |
MII management indicator register |
MIIMINDColdResetValue |
uint32_t |
MII management indicator register |
MIIMINDForcedBits |
uint32_t |
MII management indicator register |
MIIMINDForcedFlippedBits |
uint32_t |
MII management indicator register |
MIIMINDReadMask |
uint32_t |
MII management indicator register |
MIIMINDResetMask |
uint32_t |
MII management indicator register |
MIIMINDResetValue |
uint32_t |
MII management indicator register |
MIIMINDWriteMask |
uint32_t |
MII management indicator register |
MIIMSTAT |
uint32_t |
MII management status register |
MIIMSTATColdResetValue |
uint32_t |
MII management status register |
MIIMSTATForcedBits |
uint32_t |
MII management status register |
MIIMSTATForcedFlippedBits |
uint32_t |
MII management status register |
MIIMSTATReadMask |
uint32_t |
MII management status register |
MIIMSTATResetMask |
uint32_t |
MII management status register |
MIIMSTATResetValue |
uint32_t |
MII management status register |
MIIMSTATWriteMask |
uint32_t |
MII management status register |
MRBLR |
uint32_t |
Maximum receive buffer length register |
MRBLRColdResetValue |
uint32_t |
Maximum receive buffer length register |
MRBLRForcedBits |
uint32_t |
Maximum receive buffer length register |
MRBLRForcedFlippedBits |
uint32_t |
Maximum receive buffer length register |
MRBLRReadMask |
uint32_t |
Maximum receive buffer length register |
MRBLRResetMask |
uint32_t |
Maximum receive buffer length register |
MRBLRResetValue |
uint32_t |
Maximum receive buffer length register |
MRBLRWriteMask |
uint32_t |
Maximum receive buffer length register |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
PTV |
uint32_t |
Pause time value register |
PTVColdResetValue |
uint32_t |
Pause time value register |
PTVForcedBits |
uint32_t |
Pause time value register |
PTVForcedFlippedBits |
uint32_t |
Pause time value register |
PTVReadMask |
uint32_t |
Pause time value register |
PTVResetMask |
uint32_t |
Pause time value register |
PTVResetValue |
uint32_t |
Pause time value register |
PTVWriteMask |
uint32_t |
Pause time value register |
RALN |
uint32_t |
Receive alignment error counter |
RALNColdResetValue |
uint32_t |
Receive alignment error counter |
RALNForcedBits |
uint32_t |
Receive alignment error counter |
RALNForcedFlippedBits |
uint32_t |
Receive alignment error counter |
RALNReadMask |
uint32_t |
Receive alignment error counter |
RALNResetMask |
uint32_t |
Receive alignment error counter |
RALNResetValue |
uint32_t |
Receive alignment error counter |
RALNWriteMask |
uint32_t |
Receive alignment error counter |
RBASE |
[uint32_t; 8] |
RxBD base address of ring n |
RBASEH |
uint32_t |
RxBD base address high bits |
RBASEHColdResetValue |
uint32_t |
RxBD base address high bits |
RBASEHForcedBits |
uint32_t |
RxBD base address high bits |
RBASEHForcedFlippedBits |
uint32_t |
RxBD base address high bits |
RBASEHReadMask |
uint32_t |
RxBD base address high bits |
RBASEHResetMask |
uint32_t |
RxBD base address high bits |
RBASEHResetValue |
uint32_t |
RxBD base address high bits |
RBASEHWriteMask |
uint32_t |
RxBD base address high bits |
RBCA |
uint32_t |
Receive broadcast packet counter |
RBCAColdResetValue |
uint32_t |
Receive broadcast packet counter |
RBCAForcedBits |
uint32_t |
Receive broadcast packet counter |
RBCAForcedFlippedBits |
uint32_t |
Receive broadcast packet counter |
RBCAReadMask |
uint32_t |
Receive broadcast packet counter |
RBCAResetMask |
uint32_t |
Receive broadcast packet counter |
RBCAResetValue |
uint32_t |
Receive broadcast packet counter |
RBCAWriteMask |
uint32_t |
Receive broadcast packet counter |
RBDBPH |
uint32_t |
Rx data buffer pointer high bits |
RBDBPHColdResetValue |
uint32_t |
Rx data buffer pointer high bits |
RBDBPHForcedBits |
uint32_t |
Rx data buffer pointer high bits |
RBDBPHForcedFlippedBits |
uint32_t |
Rx data buffer pointer high bits |
RBDBPHReadMask |
uint32_t |
Rx data buffer pointer high bits |
RBDBPHResetMask |
uint32_t |
Rx data buffer pointer high bits |
RBDBPHResetValue |
uint32_t |
Rx data buffer pointer high bits |
RBDBPHWriteMask |
uint32_t |
Rx data buffer pointer high bits |
RBIFX |
uint32_t |
Receive bit field extract control register |
RBIFXColdResetValue |
uint32_t |
Receive bit field extract control register |
RBIFXForcedBits |
uint32_t |
Receive bit field extract control register |
RBIFXForcedFlippedBits |
uint32_t |
Receive bit field extract control register |
RBIFXReadMask |
uint32_t |
Receive bit field extract control register |
RBIFXResetMask |
uint32_t |
Receive bit field extract control register |
RBIFXResetValue |
uint32_t |
Receive bit field extract control register |
RBIFXWriteMask |
uint32_t |
Receive bit field extract control register |
RBPTR |
[uint32_t; 8] |
RxBD pointer for ring n |
RBYT |
uint32_t |
Receive byte counter |
RBYTColdResetValue |
uint32_t |
Receive byte counter |
RBYTForcedBits |
uint32_t |
Receive byte counter |
RBYTForcedFlippedBits |
uint32_t |
Receive byte counter |
RBYTReadMask |
uint32_t |
Receive byte counter |
RBYTResetMask |
uint32_t |
Receive byte counter |
RBYTResetValue |
uint32_t |
Receive byte counter |
RBYTWriteMask |
uint32_t |
Receive byte counter |
RCSE |
uint32_t |
Receive carrier sense error counter |
RCSEColdResetValue |
uint32_t |
Receive carrier sense error counter |
RCSEForcedBits |
uint32_t |
Receive carrier sense error counter |
RCSEForcedFlippedBits |
uint32_t |
Receive carrier sense error counter |
RCSEReadMask |
uint32_t |
Receive carrier sense error counter |
RCSEResetMask |
uint32_t |
Receive carrier sense error counter |
RCSEResetValue |
uint32_t |
Receive carrier sense error counter |
RCSEWriteMask |
uint32_t |
Receive carrier sense error counter |
RCTRL |
uint32_t |
Receive control register |
RCTRLColdResetValue |
uint32_t |
Receive control register |
RCTRLForcedBits |
uint32_t |
Receive control register |
RCTRLForcedFlippedBits |
uint32_t |
Receive control register |
RCTRLReadMask |
uint32_t |
Receive control register |
RCTRLResetMask |
uint32_t |
Receive control register |
RCTRLResetValue |
uint32_t |
Receive control register |
RCTRLWriteMask |
uint32_t |
Receive control register |
RDRP |
uint32_t |
Receive drop counter |
RDRPColdResetValue |
uint32_t |
Receive drop counter |
RDRPForcedBits |
uint32_t |
Receive drop counter |
RDRPForcedFlippedBits |
uint32_t |
Receive drop counter |
RDRPReadMask |
uint32_t |
Receive drop counter |
RDRPResetMask |
uint32_t |
Receive drop counter |
RDRPResetValue |
uint32_t |
Receive drop counter |
RDRPWriteMask |
uint32_t |
Receive drop counter |
RFBPTR |
[uint32_t; 8] |
Last free RxBD pointer for ring n |
RFCS |
uint32_t |
Receive FCS error counter |
RFCSColdResetValue |
uint32_t |
Receive FCS error counter |
RFCSForcedBits |
uint32_t |
Receive FCS error counter |
RFCSForcedFlippedBits |
uint32_t |
Receive FCS error counter |
RFCSReadMask |
uint32_t |
Receive FCS error counter |
RFCSResetMask |
uint32_t |
Receive FCS error counter |
RFCSResetValue |
uint32_t |
Receive FCS error counter |
RFCSWriteMask |
uint32_t |
Receive FCS error counter |
RFLR |
uint32_t |
Receive frame length error counter |
RFLRColdResetValue |
uint32_t |
Receive frame length error counter |
RFLRForcedBits |
uint32_t |
Receive frame length error counter |
RFLRForcedFlippedBits |
uint32_t |
Receive frame length error counter |
RFLRReadMask |
uint32_t |
Receive frame length error counter |
RFLRResetMask |
uint32_t |
Receive frame length error counter |
RFLRResetValue |
uint32_t |
Receive frame length error counter |
RFLRWriteMask |
uint32_t |
Receive frame length error counter |
RFRG |
uint32_t |
Receive fragments counter |
RFRGColdResetValue |
uint32_t |
Receive fragments counter |
RFRGForcedBits |
uint32_t |
Receive fragments counter |
RFRGForcedFlippedBits |
uint32_t |
Receive fragments counter |
RFRGReadMask |
uint32_t |
Receive fragments counter |
RFRGResetMask |
uint32_t |
Receive fragments counter |
RFRGResetValue |
uint32_t |
Receive fragments counter |
RFRGWriteMask |
uint32_t |
Receive fragments counter |
RJBR |
uint32_t |
Receive jabber counter |
RJBRColdResetValue |
uint32_t |
Receive jabber counter |
RJBRForcedBits |
uint32_t |
Receive jabber counter |
RJBRForcedFlippedBits |
uint32_t |
Receive jabber counter |
RJBRReadMask |
uint32_t |
Receive jabber counter |
RJBRResetMask |
uint32_t |
Receive jabber counter |
RJBRResetValue |
uint32_t |
Receive jabber counter |
RJBRWriteMask |
uint32_t |
Receive jabber counter |
RMCA |
uint32_t |
Receive multicast packet counter |
RMCAColdResetValue |
uint32_t |
Receive multicast packet counter |
RMCAForcedBits |
uint32_t |
Receive multicast packet counter |
RMCAForcedFlippedBits |
uint32_t |
Receive multicast packet counter |
RMCAReadMask |
uint32_t |
Receive multicast packet counter |
RMCAResetMask |
uint32_t |
Receive multicast packet counter |
RMCAResetValue |
uint32_t |
Receive multicast packet counter |
RMCAWriteMask |
uint32_t |
Receive multicast packet counter |
ROVR |
uint32_t |
Receive oversize packet counter |
ROVRColdResetValue |
uint32_t |
Receive oversize packet counter |
ROVRForcedBits |
uint32_t |
Receive oversize packet counter |
ROVRForcedFlippedBits |
uint32_t |
Receive oversize packet counter |
ROVRReadMask |
uint32_t |
Receive oversize packet counter |
ROVRResetMask |
uint32_t |
Receive oversize packet counter |
ROVRResetValue |
uint32_t |
Receive oversize packet counter |
ROVRWriteMask |
uint32_t |
Receive oversize packet counter |
RPKT |
uint32_t |
Receive packet counter |
RPKTColdResetValue |
uint32_t |
Receive packet counter |
RPKTForcedBits |
uint32_t |
Receive packet counter |
RPKTForcedFlippedBits |
uint32_t |
Receive packet counter |
RPKTReadMask |
uint32_t |
Receive packet counter |
RPKTResetMask |
uint32_t |
Receive packet counter |
RPKTResetValue |
uint32_t |
Receive packet counter |
RPKTWriteMask |
uint32_t |
Receive packet counter |
RQFAR |
uint32_t |
Receive queue filing table address register |
RQFARColdResetValue |
uint32_t |
Receive queue filing table address register |
RQFARForcedBits |
uint32_t |
Receive queue filing table address register |
RQFARForcedFlippedBits |
uint32_t |
Receive queue filing table address register |
RQFARReadMask |
uint32_t |
Receive queue filing table address register |
RQFARResetMask |
uint32_t |
Receive queue filing table address register |
RQFARResetValue |
uint32_t |
Receive queue filing table address register |
RQFARWriteMask |
uint32_t |
Receive queue filing table address register |
RQFCR |
uint32_t |
Receive queue filing table control register |
RQFCRColdResetValue |
uint32_t |
Receive queue filing table control register |
RQFCRForcedBits |
uint32_t |
Receive queue filing table control register |
RQFCRForcedFlippedBits |
uint32_t |
Receive queue filing table control register |
RQFCRReadMask |
uint32_t |
Receive queue filing table control register |
RQFCRResetMask |
uint32_t |
Receive queue filing table control register |
RQFCRResetValue |
uint32_t |
Receive queue filing table control register |
RQFCRWriteMask |
uint32_t |
Receive queue filing table control register |
RQFPR |
uint32_t |
Receive queue filing table property register |
RQFPRColdResetValue |
uint32_t |
Receive queue filing table property register |
RQFPRForcedBits |
uint32_t |
Receive queue filing table property register |
RQFPRForcedFlippedBits |
uint32_t |
Receive queue filing table property register |
RQFPRReadMask |
uint32_t |
Receive queue filing table property register |
RQFPRResetMask |
uint32_t |
Receive queue filing table property register |
RQFPRResetValue |
uint32_t |
Receive queue filing table property register |
RQFPRWriteMask |
uint32_t |
Receive queue filing table property register |
RQPRM |
[uint32_t; 8] |
Receive queue parameters register |
RQUEUE |
uint32_t |
Receive queue control register |
RQUEUEColdResetValue |
uint32_t |
Receive queue control register |
RQUEUEForcedBits |
uint32_t |
Receive queue control register |
RQUEUEForcedFlippedBits |
uint32_t |
Receive queue control register |
RQUEUEReadMask |
uint32_t |
Receive queue control register |
RQUEUEResetMask |
uint32_t |
Receive queue control register |
RQUEUEResetValue |
uint32_t |
Receive queue control register |
RQUEUEWriteMask |
uint32_t |
Receive queue control register |
RREJ |
uint32_t |
Receive filer rejected packet counter |
RREJColdResetValue |
uint32_t |
Receive filer rejected packet counter |
RREJForcedBits |
uint32_t |
Receive filer rejected packet counter |
RREJForcedFlippedBits |
uint32_t |
Receive filer rejected packet counter |
RREJReadMask |
uint32_t |
Receive filer rejected packet counter |
RREJResetMask |
uint32_t |
Receive filer rejected packet counter |
RREJResetValue |
uint32_t |
Receive filer rejected packet counter |
RREJWriteMask |
uint32_t |
Receive filer rejected packet counter |
RSTAT |
uint32_t |
Receive status register |
RSTATColdResetValue |
uint32_t |
Receive status register |
RSTATForcedBits |
uint32_t |
Receive status register |
RSTATForcedFlippedBits |
uint32_t |
Receive status register |
RSTATReadMask |
uint32_t |
Receive status register |
RSTATResetMask |
uint32_t |
Receive status register |
RSTATResetValue |
uint32_t |
Receive status register |
RSTATWriteMask |
uint32_t |
Receive status register |
RUND |
uint32_t |
Receive undersize packet counter |
RUNDColdResetValue |
uint32_t |
Receive undersize packet counter |
RUNDForcedBits |
uint32_t |
Receive undersize packet counter |
RUNDForcedFlippedBits |
uint32_t |
Receive undersize packet counter |
RUNDReadMask |
uint32_t |
Receive undersize packet counter |
RUNDResetMask |
uint32_t |
Receive undersize packet counter |
RUNDResetValue |
uint32_t |
Receive undersize packet counter |
RUNDWriteMask |
uint32_t |
Receive undersize packet counter |
RXCF |
uint32_t |
Receive control frame counter |
RXCFColdResetValue |
uint32_t |
Receive control frame counter |
RXCFForcedBits |
uint32_t |
Receive control frame counter |
RXCFForcedFlippedBits |
uint32_t |
Receive control frame counter |
RXCFReadMask |
uint32_t |
Receive control frame counter |
RXCFResetMask |
uint32_t |
Receive control frame counter |
RXCFResetValue |
uint32_t |
Receive control frame counter |
RXCFWriteMask |
uint32_t |
Receive control frame counter |
RXIC |
uint32_t |
Receive interrupt coalescing register |
RXICColdResetValue |
uint32_t |
Receive interrupt coalescing register |
RXICForcedBits |
uint32_t |
Receive interrupt coalescing register |
RXICForcedFlippedBits |
uint32_t |
Receive interrupt coalescing register |
RXICReadMask |
uint32_t |
Receive interrupt coalescing register |
RXICResetMask |
uint32_t |
Receive interrupt coalescing register |
RXICResetValue |
uint32_t |
Receive interrupt coalescing register |
RXICWriteMask |
uint32_t |
Receive interrupt coalescing register |
RXPF |
uint32_t |
Receive PAUSE frame counter |
RXPFColdResetValue |
uint32_t |
Receive PAUSE frame counter |
RXPFForcedBits |
uint32_t |
Receive PAUSE frame counter |
RXPFForcedFlippedBits |
uint32_t |
Receive PAUSE frame counter |
RXPFReadMask |
uint32_t |
Receive PAUSE frame counter |
RXPFResetMask |
uint32_t |
Receive PAUSE frame counter |
RXPFResetValue |
uint32_t |
Receive PAUSE frame counter |
RXPFWriteMask |
uint32_t |
Receive PAUSE frame counter |
RXUO |
uint32_t |
Receive unknown opcode counter |
RXUOColdResetValue |
uint32_t |
Receive unknown opcode counter |
RXUOForcedBits |
uint32_t |
Receive unknown opcode counter |
RXUOForcedFlippedBits |
uint32_t |
Receive unknown opcode counter |
RXUOReadMask |
uint32_t |
Receive unknown opcode counter |
RXUOResetMask |
uint32_t |
Receive unknown opcode counter |
RXUOResetValue |
uint32_t |
Receive unknown opcode counter |
RXUOWriteMask |
uint32_t |
Receive unknown opcode counter |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TBASE |
[uint32_t; 8] |
TxBD base address of ring n |
TBASEH |
uint32_t |
TxBD base address high bits |
TBASEHColdResetValue |
uint32_t |
TxBD base address high bits |
TBASEHForcedBits |
uint32_t |
TxBD base address high bits |
TBASEHForcedFlippedBits |
uint32_t |
TxBD base address high bits |
TBASEHReadMask |
uint32_t |
TxBD base address high bits |
TBASEHResetMask |
uint32_t |
TxBD base address high bits |
TBASEHResetValue |
uint32_t |
TxBD base address high bits |
TBASEHWriteMask |
uint32_t |
TxBD base address high bits |
TBCA |
uint32_t |
Transmit broadcast packet counter |
TBCAColdResetValue |
uint32_t |
Transmit broadcast packet counter |
TBCAForcedBits |
uint32_t |
Transmit broadcast packet counter |
TBCAForcedFlippedBits |
uint32_t |
Transmit broadcast packet counter |
TBCAReadMask |
uint32_t |
Transmit broadcast packet counter |
TBCAResetMask |
uint32_t |
Transmit broadcast packet counter |
TBCAResetValue |
uint32_t |
Transmit broadcast packet counter |
TBCAWriteMask |
uint32_t |
Transmit broadcast packet counter |
TBDBPH |
uint32_t |
Tx data buffer pointer high bits |
TBDBPHColdResetValue |
uint32_t |
Tx data buffer pointer high bits |
TBDBPHForcedBits |
uint32_t |
Tx data buffer pointer high bits |
TBDBPHForcedFlippedBits |
uint32_t |
Tx data buffer pointer high bits |
TBDBPHReadMask |
uint32_t |
Tx data buffer pointer high bits |
TBDBPHResetMask |
uint32_t |
Tx data buffer pointer high bits |
TBDBPHResetValue |
uint32_t |
Tx data buffer pointer high bits |
TBDBPHWriteMask |
uint32_t |
Tx data buffer pointer high bits |
TBIPA |
uint32_t |
TBI PHY address register |
TBIPAColdResetValue |
uint32_t |
TBI PHY address register |
TBIPAForcedBits |
uint32_t |
TBI PHY address register |
TBIPAForcedFlippedBits |
uint32_t |
TBI PHY address register |
TBIPAReadMask |
uint32_t |
TBI PHY address register |
TBIPAResetMask |
uint32_t |
TBI PHY address register |
TBIPAResetValue |
uint32_t |
TBI PHY address register |
TBIPAWriteMask |
uint32_t |
TBI PHY address register |
TBPTR |
[uint32_t; 8] |
TxBD pointer for ring n |
TBYT |
uint32_t |
Transmit byte counter |
TBYTColdResetValue |
uint32_t |
Transmit byte counter |
TBYTForcedBits |
uint32_t |
Transmit byte counter |
TBYTForcedFlippedBits |
uint32_t |
Transmit byte counter |
TBYTReadMask |
uint32_t |
Transmit byte counter |
TBYTResetMask |
uint32_t |
Transmit byte counter |
TBYTResetValue |
uint32_t |
Transmit byte counter |
TBYTWriteMask |
uint32_t |
Transmit byte counter |
TCTRL |
uint32_t |
Transmit control register |
TCTRLColdResetValue |
uint32_t |
Transmit control register |
TCTRLForcedBits |
uint32_t |
Transmit control register |
TCTRLForcedFlippedBits |
uint32_t |
Transmit control register |
TCTRLReadMask |
uint32_t |
Transmit control register |
TCTRLResetMask |
uint32_t |
Transmit control register |
TCTRLResetValue |
uint32_t |
Transmit control register |
TCTRLWriteMask |
uint32_t |
Transmit control register |
TDFR |
uint32_t |
Transmit deferral packet counter |
TDFRColdResetValue |
uint32_t |
Transmit deferral packet counter |
TDFRForcedBits |
uint32_t |
Transmit deferral packet counter |
TDFRForcedFlippedBits |
uint32_t |
Transmit deferral packet counter |
TDFRReadMask |
uint32_t |
Transmit deferral packet counter |
TDFRResetMask |
uint32_t |
Transmit deferral packet counter |
TDFRResetValue |
uint32_t |
Transmit deferral packet counter |
TDFRWriteMask |
uint32_t |
Transmit deferral packet counter |
TDRP |
uint32_t |
Transmit drop frame counter |
TDRPColdResetValue |
uint32_t |
Transmit drop frame counter |
TDRPForcedBits |
uint32_t |
Transmit drop frame counter |
TDRPForcedFlippedBits |
uint32_t |
Transmit drop frame counter |
TDRPReadMask |
uint32_t |
Transmit drop frame counter |
TDRPResetMask |
uint32_t |
Transmit drop frame counter |
TDRPResetValue |
uint32_t |
Transmit drop frame counter |
TDRPWriteMask |
uint32_t |
Transmit drop frame counter |
TEDF |
uint32_t |
Transmit excessive deferral packet counter |
TEDFColdResetValue |
uint32_t |
Transmit excessive deferral packet counter |
TEDFForcedBits |
uint32_t |
Transmit excessive deferral packet counter |
TEDFForcedFlippedBits |
uint32_t |
Transmit excessive deferral packet counter |
TEDFReadMask |
uint32_t |
Transmit excessive deferral packet counter |
TEDFResetMask |
uint32_t |
Transmit excessive deferral packet counter |
TEDFResetValue |
uint32_t |
Transmit excessive deferral packet counter |
TEDFWriteMask |
uint32_t |
Transmit excessive deferral packet counter |
TFCS |
uint32_t |
Transmit FCS error counter |
TFCSColdResetValue |
uint32_t |
Transmit FCS error counter |
TFCSForcedBits |
uint32_t |
Transmit FCS error counter |
TFCSForcedFlippedBits |
uint32_t |
Transmit FCS error counter |
TFCSReadMask |
uint32_t |
Transmit FCS error counter |
TFCSResetMask |
uint32_t |
Transmit FCS error counter |
TFCSResetValue |
uint32_t |
Transmit FCS error counter |
TFCSWriteMask |
uint32_t |
Transmit FCS error counter |
TFRG |
uint32_t |
Transmit fragments frame counter |
TFRGColdResetValue |
uint32_t |
Transmit fragments frame counter |
TFRGForcedBits |
uint32_t |
Transmit fragments frame counter |
TFRGForcedFlippedBits |
uint32_t |
Transmit fragments frame counter |
TFRGReadMask |
uint32_t |
Transmit fragments frame counter |
TFRGResetMask |
uint32_t |
Transmit fragments frame counter |
TFRGResetValue |
uint32_t |
Transmit fragments frame counter |
TFRGWriteMask |
uint32_t |
Transmit fragments frame counter |
TJBR |
uint32_t |
Transmit jabber frame counter |
TJBRColdResetValue |
uint32_t |
Transmit jabber frame counter |
TJBRForcedBits |
uint32_t |
Transmit jabber frame counter |
TJBRForcedFlippedBits |
uint32_t |
Transmit jabber frame counter |
TJBRReadMask |
uint32_t |
Transmit jabber frame counter |
TJBRResetMask |
uint32_t |
Transmit jabber frame counter |
TJBRResetValue |
uint32_t |
Transmit jabber frame counter |
TJBRWriteMask |
uint32_t |
Transmit jabber frame counter |
TLCL |
uint32_t |
Transmit late collision packet counter |
TLCLColdResetValue |
uint32_t |
Transmit late collision packet counter |
TLCLForcedBits |
uint32_t |
Transmit late collision packet counter |
TLCLForcedFlippedBits |
uint32_t |
Transmit late collision packet counter |
TLCLReadMask |
uint32_t |
Transmit late collision packet counter |
TLCLResetMask |
uint32_t |
Transmit late collision packet counter |
TLCLResetValue |
uint32_t |
Transmit late collision packet counter |
TLCLWriteMask |
uint32_t |
Transmit late collision packet counter |
TMCA |
uint32_t |
Transmit multicast packet counter |
TMCAColdResetValue |
uint32_t |
Transmit multicast packet counter |
TMCAForcedBits |
uint32_t |
Transmit multicast packet counter |
TMCAForcedFlippedBits |
uint32_t |
Transmit multicast packet counter |
TMCAReadMask |
uint32_t |
Transmit multicast packet counter |
TMCAResetMask |
uint32_t |
Transmit multicast packet counter |
TMCAResetValue |
uint32_t |
Transmit multicast packet counter |
TMCAWriteMask |
uint32_t |
Transmit multicast packet counter |
TMCL |
uint32_t |
Transmit multi collision packet counter |
TMCLColdResetValue |
uint32_t |
Transmit multi collision packet counter |
TMCLForcedBits |
uint32_t |
Transmit multi collision packet counter |
TMCLForcedFlippedBits |
uint32_t |
Transmit multi collision packet counter |
TMCLReadMask |
uint32_t |
Transmit multi collision packet counter |
TMCLResetMask |
uint32_t |
Transmit multi collision packet counter |
TMCLResetValue |
uint32_t |
Transmit multi collision packet counter |
TMCLWriteMask |
uint32_t |
Transmit multi collision packet counter |
TMROFF_H |
uint32_t |
Timer offset high register |
TMROFF_HColdResetValue |
uint32_t |
Timer offset high register |
TMROFF_HForcedBits |
uint32_t |
Timer offset high register |
TMROFF_HForcedFlippedBits |
uint32_t |
Timer offset high register |
TMROFF_HReadMask |
uint32_t |
Timer offset high register |
TMROFF_HResetMask |
uint32_t |
Timer offset high register |
TMROFF_HResetValue |
uint32_t |
Timer offset high register |
TMROFF_HWriteMask |
uint32_t |
Timer offset high register |
TMROFF_L |
uint32_t |
Timer offset low register |
TMROFF_LColdResetValue |
uint32_t |
Timer offset low register |
TMROFF_LForcedBits |
uint32_t |
Timer offset low register |
TMROFF_LForcedFlippedBits |
uint32_t |
Timer offset low register |
TMROFF_LReadMask |
uint32_t |
Timer offset low register |
TMROFF_LResetMask |
uint32_t |
Timer offset low register |
TMROFF_LResetValue |
uint32_t |
Timer offset low register |
TMROFF_LWriteMask |
uint32_t |
Timer offset low register |
TMR_ACC |
uint32_t |
Timer accumulator register |
TMR_ACCColdResetValue |
uint32_t |
Timer accumulator register |
TMR_ACCForcedBits |
uint32_t |
Timer accumulator register |
TMR_ACCForcedFlippedBits |
uint32_t |
Timer accumulator register |
TMR_ACCReadMask |
uint32_t |
Timer accumulator register |
TMR_ACCResetMask |
uint32_t |
Timer accumulator register |
TMR_ACCResetValue |
uint32_t |
Timer accumulator register |
TMR_ACCWriteMask |
uint32_t |
Timer accumulator register |
TMR_ADD |
uint32_t |
Timer drift compensation addend register |
TMR_ADDColdResetValue |
uint32_t |
Timer drift compensation addend register |
TMR_ADDForcedBits |
uint32_t |
Timer drift compensation addend register |
TMR_ADDForcedFlippedBits |
uint32_t |
Timer drift compensation addend register |
TMR_ADDReadMask |
uint32_t |
Timer drift compensation addend register |
TMR_ADDResetMask |
uint32_t |
Timer drift compensation addend register |
TMR_ADDResetValue |
uint32_t |
Timer drift compensation addend register |
TMR_ADDWriteMask |
uint32_t |
Timer drift compensation addend register |
TMR_ALARM_H |
[uint32_t; 2] |
Timer alarm high register |
TMR_ALARM_L |
[uint32_t; 2] |
Timer alarm low register |
TMR_CNT_H |
uint32_t |
Timer counter high register |
TMR_CNT_HColdResetValue |
uint32_t |
Timer counter high register |
TMR_CNT_HForcedBits |
uint32_t |
Timer counter high register |
TMR_CNT_HForcedFlippedBits |
uint32_t |
Timer counter high register |
TMR_CNT_HReadMask |
uint32_t |
Timer counter high register |
TMR_CNT_HResetMask |
uint32_t |
Timer counter high register |
TMR_CNT_HResetValue |
uint32_t |
Timer counter high register |
TMR_CNT_HWriteMask |
uint32_t |
Timer counter high register |
TMR_CNT_L |
uint32_t |
Timer counter low register |
TMR_CNT_LColdResetValue |
uint32_t |
Timer counter low register |
TMR_CNT_LForcedBits |
uint32_t |
Timer counter low register |
TMR_CNT_LForcedFlippedBits |
uint32_t |
Timer counter low register |
TMR_CNT_LReadMask |
uint32_t |
Timer counter low register |
TMR_CNT_LResetMask |
uint32_t |
Timer counter low register |
TMR_CNT_LResetValue |
uint32_t |
Timer counter low register |
TMR_CNT_LWriteMask |
uint32_t |
Timer counter low register |
TMR_CTRL |
uint32_t |
Timer control register |
TMR_CTRLColdResetValue |
uint32_t |
Timer control register |
TMR_CTRLForcedBits |
uint32_t |
Timer control register |
TMR_CTRLForcedFlippedBits |
uint32_t |
Timer control register |
TMR_CTRLReadMask |
uint32_t |
Timer control register |
TMR_CTRLResetMask |
uint32_t |
Timer control register |
TMR_CTRLResetValue |
uint32_t |
Timer control register |
TMR_CTRLWriteMask |
uint32_t |
Timer control register |
TMR_ETTS_H |
[uint32_t; 2] |
External trigger timestamp high register |
TMR_ETTS_L |
[uint32_t; 2] |
External trigger timestamp low register |
TMR_FIPER |
[uint32_t; 2] |
Timer fixed period interval register |
TMR_PEMASK |
uint32_t |
PTP time stamp event mask register |
TMR_PEMASKColdResetValue |
uint32_t |
PTP time stamp event mask register |
TMR_PEMASKForcedBits |
uint32_t |
PTP time stamp event mask register |
TMR_PEMASKForcedFlippedBits |
uint32_t |
PTP time stamp event mask register |
TMR_PEMASKReadMask |
uint32_t |
PTP time stamp event mask register |
TMR_PEMASKResetMask |
uint32_t |
PTP time stamp event mask register |
TMR_PEMASKResetValue |
uint32_t |
PTP time stamp event mask register |
TMR_PEMASKWriteMask |
uint32_t |
PTP time stamp event mask register |
TMR_PEVENT |
uint32_t |
PTP time stamp event register |
TMR_PEVENTColdResetValue |
uint32_t |
PTP time stamp event register |
TMR_PEVENTForcedBits |
uint32_t |
PTP time stamp event register |
TMR_PEVENTForcedFlippedBits |
uint32_t |
PTP time stamp event register |
TMR_PEVENTReadMask |
uint32_t |
PTP time stamp event register |
TMR_PEVENTResetMask |
uint32_t |
PTP time stamp event register |
TMR_PEVENTResetValue |
uint32_t |
PTP time stamp event register |
TMR_PEVENTWriteMask |
uint32_t |
PTP time stamp event register |
TMR_PRSC |
uint32_t |
Timer prescale register |
TMR_PRSCColdResetValue |
uint32_t |
Timer prescale register |
TMR_PRSCForcedBits |
uint32_t |
Timer prescale register |
TMR_PRSCForcedFlippedBits |
uint32_t |
Timer prescale register |
TMR_PRSCReadMask |
uint32_t |
Timer prescale register |
TMR_PRSCResetMask |
uint32_t |
Timer prescale register |
TMR_PRSCResetValue |
uint32_t |
Timer prescale register |
TMR_PRSCWriteMask |
uint32_t |
Timer prescale register |
TMR_RXTS_H |
uint32_t |
Rx timer time stamp high |
TMR_RXTS_HColdResetValue |
uint32_t |
Rx timer time stamp high |
TMR_RXTS_HForcedBits |
uint32_t |
Rx timer time stamp high |
TMR_RXTS_HForcedFlippedBits |
uint32_t |
Rx timer time stamp high |
TMR_RXTS_HReadMask |
uint32_t |
Rx timer time stamp high |
TMR_RXTS_HResetMask |
uint32_t |
Rx timer time stamp high |
TMR_RXTS_HResetValue |
uint32_t |
Rx timer time stamp high |
TMR_RXTS_HWriteMask |
uint32_t |
Rx timer time stamp high |
TMR_RXTS_L |
uint32_t |
Rx timer time stamp low |
TMR_RXTS_LColdResetValue |
uint32_t |
Rx timer time stamp low |
TMR_RXTS_LForcedBits |
uint32_t |
Rx timer time stamp low |
TMR_RXTS_LForcedFlippedBits |
uint32_t |
Rx timer time stamp low |
TMR_RXTS_LReadMask |
uint32_t |
Rx timer time stamp low |
TMR_RXTS_LResetMask |
uint32_t |
Rx timer time stamp low |
TMR_RXTS_LResetValue |
uint32_t |
Rx timer time stamp low |
TMR_RXTS_LWriteMask |
uint32_t |
Rx timer time stamp low |
TMR_STAT |
uint32_t |
Time stamp status register |
TMR_STATColdResetValue |
uint32_t |
Time stamp status register |
TMR_STATForcedBits |
uint32_t |
Time stamp status register |
TMR_STATForcedFlippedBits |
uint32_t |
Time stamp status register |
TMR_STATReadMask |
uint32_t |
Time stamp status register |
TMR_STATResetMask |
uint32_t |
Time stamp status register |
TMR_STATResetValue |
uint32_t |
Time stamp status register |
TMR_STATWriteMask |
uint32_t |
Time stamp status register |
TMR_TEMASK |
uint32_t |
Timer event mask register |
TMR_TEMASKColdResetValue |
uint32_t |
Timer event mask register |
TMR_TEMASKForcedBits |
uint32_t |
Timer event mask register |
TMR_TEMASKForcedFlippedBits |
uint32_t |
Timer event mask register |
TMR_TEMASKReadMask |
uint32_t |
Timer event mask register |
TMR_TEMASKResetMask |
uint32_t |
Timer event mask register |
TMR_TEMASKResetValue |
uint32_t |
Timer event mask register |
TMR_TEMASKWriteMask |
uint32_t |
Timer event mask register |
TMR_TEVENT |
uint32_t |
Time stamp event register |
TMR_TEVENTColdResetValue |
uint32_t |
Time stamp event register |
TMR_TEVENTForcedBits |
uint32_t |
Time stamp event register |
TMR_TEVENTForcedFlippedBits |
uint32_t |
Time stamp event register |
TMR_TEVENTReadMask |
uint32_t |
Time stamp event register |
TMR_TEVENTResetMask |
uint32_t |
Time stamp event register |
TMR_TEVENTResetValue |
uint32_t |
Time stamp event register |
TMR_TEVENTWriteMask |
uint32_t |
Time stamp event register |
TMR_TXTS_H |
[uint32_t; 2] |
Tx time stamp high |
TMR_TXTS_ID |
[uint32_t; 2] |
Tx time stamp identification tag register |
TMR_TXTS_L |
[uint32_t; 2] |
Tx time stamp low |
TNCL |
uint32_t |
Transmit total collision packet counter |
TNCLColdResetValue |
uint32_t |
Transmit total collision packet counter |
TNCLForcedBits |
uint32_t |
Transmit total collision packet counter |
TNCLForcedFlippedBits |
uint32_t |
Transmit total collision packet counter |
TNCLReadMask |
uint32_t |
Transmit total collision packet counter |
TNCLResetMask |
uint32_t |
Transmit total collision packet counter |
TNCLResetValue |
uint32_t |
Transmit total collision packet counter |
TNCLWriteMask |
uint32_t |
Transmit total collision packet counter |
TOVR |
uint32_t |
Transmit oversize frame counter |
TOVRColdResetValue |
uint32_t |
Transmit oversize frame counter |
TOVRForcedBits |
uint32_t |
Transmit oversize frame counter |
TOVRForcedFlippedBits |
uint32_t |
Transmit oversize frame counter |
TOVRReadMask |
uint32_t |
Transmit oversize frame counter |
TOVRResetMask |
uint32_t |
Transmit oversize frame counter |
TOVRResetValue |
uint32_t |
Transmit oversize frame counter |
TOVRWriteMask |
uint32_t |
Transmit oversize frame counter |
TPKT |
uint32_t |
Transmit packet counter |
TPKTColdResetValue |
uint32_t |
Transmit packet counter |
TPKTForcedBits |
uint32_t |
Transmit packet counter |
TPKTForcedFlippedBits |
uint32_t |
Transmit packet counter |
TPKTReadMask |
uint32_t |
Transmit packet counter |
TPKTResetMask |
uint32_t |
Transmit packet counter |
TPKTResetValue |
uint32_t |
Transmit packet counter |
TPKTWriteMask |
uint32_t |
Transmit packet counter |
TQUEUE |
uint32_t |
Transmit queue control register |
TQUEUEColdResetValue |
uint32_t |
Transmit queue control register |
TQUEUEForcedBits |
uint32_t |
Transmit queue control register |
TQUEUEForcedFlippedBits |
uint32_t |
Transmit queue control register |
TQUEUEReadMask |
uint32_t |
Transmit queue control register |
TQUEUEResetMask |
uint32_t |
Transmit queue control register |
TQUEUEResetValue |
uint32_t |
Transmit queue control register |
TQUEUEWriteMask |
uint32_t |
Transmit queue control register |
TR03WT |
uint32_t |
TxBD rings 0-3 round-robin weightings |
TR03WTColdResetValue |
uint32_t |
TxBD rings 0-3 round-robin weightings |
TR03WTForcedBits |
uint32_t |
TxBD rings 0-3 round-robin weightings |
TR03WTForcedFlippedBits |
uint32_t |
TxBD rings 0-3 round-robin weightings |
TR03WTReadMask |
uint32_t |
TxBD rings 0-3 round-robin weightings |
TR03WTResetMask |
uint32_t |
TxBD rings 0-3 round-robin weightings |
TR03WTResetValue |
uint32_t |
TxBD rings 0-3 round-robin weightings |
TR03WTWriteMask |
uint32_t |
TxBD rings 0-3 round-robin weightings |
TR127 |
uint32_t |
Transmit and receive 65- to 127-byte frame counter |
TR127ColdResetValue |
uint32_t |
Transmit and receive 65- to 127-byte frame counter |
TR127ForcedBits |
uint32_t |
Transmit and receive 65- to 127-byte frame counter |
TR127ForcedFlippedBits |
uint32_t |
Transmit and receive 65- to 127-byte frame counter |
TR127ReadMask |
uint32_t |
Transmit and receive 65- to 127-byte frame counter |
TR127ResetMask |
uint32_t |
Transmit and receive 65- to 127-byte frame counter |
TR127ResetValue |
uint32_t |
Transmit and receive 65- to 127-byte frame counter |
TR127WriteMask |
uint32_t |
Transmit and receive 65- to 127-byte frame counter |
TR1K |
uint32_t |
Transmit and receive 512- to 1023-byte frame counter |
TR1KColdResetValue |
uint32_t |
Transmit and receive 512- to 1023-byte frame counter |
TR1KForcedBits |
uint32_t |
Transmit and receive 512- to 1023-byte frame counter |
TR1KForcedFlippedBits |
uint32_t |
Transmit and receive 512- to 1023-byte frame counter |
TR1KReadMask |
uint32_t |
Transmit and receive 512- to 1023-byte frame counter |
TR1KResetMask |
uint32_t |
Transmit and receive 512- to 1023-byte frame counter |
TR1KResetValue |
uint32_t |
Transmit and receive 512- to 1023-byte frame counter |
TR1KWriteMask |
uint32_t |
Transmit and receive 512- to 1023-byte frame counter |
TR255 |
uint32_t |
Transmit and receive 128- to 255-byte frame counter |
TR255ColdResetValue |
uint32_t |
Transmit and receive 128- to 255-byte frame counter |
TR255ForcedBits |
uint32_t |
Transmit and receive 128- to 255-byte frame counter |
TR255ForcedFlippedBits |
uint32_t |
Transmit and receive 128- to 255-byte frame counter |
TR255ReadMask |
uint32_t |
Transmit and receive 128- to 255-byte frame counter |
TR255ResetMask |
uint32_t |
Transmit and receive 128- to 255-byte frame counter |
TR255ResetValue |
uint32_t |
Transmit and receive 128- to 255-byte frame counter |
TR255WriteMask |
uint32_t |
Transmit and receive 128- to 255-byte frame counter |
TR47WT |
uint32_t |
TxBD rings 4-7 round-robin weightings |
TR47WTColdResetValue |
uint32_t |
TxBD rings 4-7 round-robin weightings |
TR47WTForcedBits |
uint32_t |
TxBD rings 4-7 round-robin weightings |
TR47WTForcedFlippedBits |
uint32_t |
TxBD rings 4-7 round-robin weightings |
TR47WTReadMask |
uint32_t |
TxBD rings 4-7 round-robin weightings |
TR47WTResetMask |
uint32_t |
TxBD rings 4-7 round-robin weightings |
TR47WTResetValue |
uint32_t |
TxBD rings 4-7 round-robin weightings |
TR47WTWriteMask |
uint32_t |
TxBD rings 4-7 round-robin weightings |
TR511 |
uint32_t |
Transmit and receive 256- to 511-byte frame counter |
TR511ColdResetValue |
uint32_t |
Transmit and receive 256- to 511-byte frame counter |
TR511ForcedBits |
uint32_t |
Transmit and receive 256- to 511-byte frame counter |
TR511ForcedFlippedBits |
uint32_t |
Transmit and receive 256- to 511-byte frame counter |
TR511ReadMask |
uint32_t |
Transmit and receive 256- to 511-byte frame counter |
TR511ResetMask |
uint32_t |
Transmit and receive 256- to 511-byte frame counter |
TR511ResetValue |
uint32_t |
Transmit and receive 256- to 511-byte frame counter |
TR511WriteMask |
uint32_t |
Transmit and receive 256- to 511-byte frame counter |
TR64 |
uint32_t |
Transmit and receive 64-byte frame counter |
TR64ColdResetValue |
uint32_t |
Transmit and receive 64-byte frame counter |
TR64ForcedBits |
uint32_t |
Transmit and receive 64-byte frame counter |
TR64ForcedFlippedBits |
uint32_t |
Transmit and receive 64-byte frame counter |
TR64ReadMask |
uint32_t |
Transmit and receive 64-byte frame counter |
TR64ResetMask |
uint32_t |
Transmit and receive 64-byte frame counter |
TR64ResetValue |
uint32_t |
Transmit and receive 64-byte frame counter |
TR64WriteMask |
uint32_t |
Transmit and receive 64-byte frame counter |
TRMAX |
uint32_t |
Transmit and receive 1024- to 1518-byte frame counter |
TRMAXColdResetValue |
uint32_t |
Transmit and receive 1024- to 1518-byte frame counter |
TRMAXForcedBits |
uint32_t |
Transmit and receive 1024- to 1518-byte frame counter |
TRMAXForcedFlippedBits |
uint32_t |
Transmit and receive 1024- to 1518-byte frame counter |
TRMAXReadMask |
uint32_t |
Transmit and receive 1024- to 1518-byte frame counter |
TRMAXResetMask |
uint32_t |
Transmit and receive 1024- to 1518-byte frame counter |
TRMAXResetValue |
uint32_t |
Transmit and receive 1024- to 1518-byte frame counter |
TRMAXWriteMask |
uint32_t |
Transmit and receive 1024- to 1518-byte frame counter |
TRMGV |
uint32_t |
Transmit and receive good VLAN frame counter |
TRMGVColdResetValue |
uint32_t |
Transmit and receive good VLAN frame counter |
TRMGVForcedBits |
uint32_t |
Transmit and receive good VLAN frame counter |
TRMGVForcedFlippedBits |
uint32_t |
Transmit and receive good VLAN frame counter |
TRMGVReadMask |
uint32_t |
Transmit and receive good VLAN frame counter |
TRMGVResetMask |
uint32_t |
Transmit and receive good VLAN frame counter |
TRMGVResetValue |
uint32_t |
Transmit and receive good VLAN frame counter |
TRMGVWriteMask |
uint32_t |
Transmit and receive good VLAN frame counter |
TSCL |
uint32_t |
Transmit single collision packet counter |
TSCLColdResetValue |
uint32_t |
Transmit single collision packet counter |
TSCLForcedBits |
uint32_t |
Transmit single collision packet counter |
TSCLForcedFlippedBits |
uint32_t |
Transmit single collision packet counter |
TSCLReadMask |
uint32_t |
Transmit single collision packet counter |
TSCLResetMask |
uint32_t |
Transmit single collision packet counter |
TSCLResetValue |
uint32_t |
Transmit single collision packet counter |
TSCLWriteMask |
uint32_t |
Transmit single collision packet counter |
TSEC_ID |
uint32_t |
Controller ID register |
TSEC_ID2 |
uint32_t |
Controller ID register 2 |
TSEC_ID2ColdResetValue |
uint32_t |
Controller ID register 2 |
TSEC_ID2ForcedBits |
uint32_t |
Controller ID register 2 |
TSEC_ID2ForcedFlippedBits |
uint32_t |
Controller ID register 2 |
TSEC_ID2ReadMask |
uint32_t |
Controller ID register 2 |
TSEC_ID2ResetMask |
uint32_t |
Controller ID register 2 |
TSEC_ID2ResetValue |
uint32_t |
Controller ID register 2 |
TSEC_ID2WriteMask |
uint32_t |
Controller ID register 2 |
TSEC_IDColdResetValue |
uint32_t |
Controller ID register |
TSEC_IDForcedBits |
uint32_t |
Controller ID register |
TSEC_IDForcedFlippedBits |
uint32_t |
Controller ID register |
TSEC_IDReadMask |
uint32_t |
Controller ID register |
TSEC_IDResetMask |
uint32_t |
Controller ID register |
TSEC_IDResetValue |
uint32_t |
Controller ID register |
TSEC_IDWriteMask |
uint32_t |
Controller ID register |
TSTAT |
uint32_t |
Transmit status register |
TSTATColdResetValue |
uint32_t |
Transmit status register |
TSTATForcedBits |
uint32_t |
Transmit status register |
TSTATForcedFlippedBits |
uint32_t |
Transmit status register |
TSTATReadMask |
uint32_t |
Transmit status register |
TSTATResetMask |
uint32_t |
Transmit status register |
TSTATResetValue |
uint32_t |
Transmit status register |
TSTATWriteMask |
uint32_t |
Transmit status register |
TUND |
uint32_t |
Transmit undersize frame counter |
TUNDColdResetValue |
uint32_t |
Transmit undersize frame counter |
TUNDForcedBits |
uint32_t |
Transmit undersize frame counter |
TUNDForcedFlippedBits |
uint32_t |
Transmit undersize frame counter |
TUNDReadMask |
uint32_t |
Transmit undersize frame counter |
TUNDResetMask |
uint32_t |
Transmit undersize frame counter |
TUNDResetValue |
uint32_t |
Transmit undersize frame counter |
TUNDWriteMask |
uint32_t |
Transmit undersize frame counter |
TXCF |
uint32_t |
Transmit control frame counter |
TXCFColdResetValue |
uint32_t |
Transmit control frame counter |
TXCFForcedBits |
uint32_t |
Transmit control frame counter |
TXCFForcedFlippedBits |
uint32_t |
Transmit control frame counter |
TXCFReadMask |
uint32_t |
Transmit control frame counter |
TXCFResetMask |
uint32_t |
Transmit control frame counter |
TXCFResetValue |
uint32_t |
Transmit control frame counter |
TXCFWriteMask |
uint32_t |
Transmit control frame counter |
TXCL |
uint32_t |
Transmit excessive collision packet counter |
TXCLColdResetValue |
uint32_t |
Transmit excessive collision packet counter |
TXCLForcedBits |
uint32_t |
Transmit excessive collision packet counter |
TXCLForcedFlippedBits |
uint32_t |
Transmit excessive collision packet counter |
TXCLReadMask |
uint32_t |
Transmit excessive collision packet counter |
TXCLResetMask |
uint32_t |
Transmit excessive collision packet counter |
TXCLResetValue |
uint32_t |
Transmit excessive collision packet counter |
TXCLWriteMask |
uint32_t |
Transmit excessive collision packet counter |
TXIC |
uint32_t |
Transmit interrupt coalescing register |
TXICColdResetValue |
uint32_t |
Transmit interrupt coalescing register |
TXICForcedBits |
uint32_t |
Transmit interrupt coalescing register |
TXICForcedFlippedBits |
uint32_t |
Transmit interrupt coalescing register |
TXICReadMask |
uint32_t |
Transmit interrupt coalescing register |
TXICResetMask |
uint32_t |
Transmit interrupt coalescing register |
TXICResetValue |
uint32_t |
Transmit interrupt coalescing register |
TXICWriteMask |
uint32_t |
Transmit interrupt coalescing register |
TXPF |
uint32_t |
Transmit PAUSE control frame counter |
TXPFColdResetValue |
uint32_t |
Transmit PAUSE control frame counter |
TXPFForcedBits |
uint32_t |
Transmit PAUSE control frame counter |
TXPFForcedFlippedBits |
uint32_t |
Transmit PAUSE control frame counter |
TXPFReadMask |
uint32_t |
Transmit PAUSE control frame counter |
TXPFResetMask |
uint32_t |
Transmit PAUSE control frame counter |
TXPFResetValue |
uint32_t |
Transmit PAUSE control frame counter |
TXPFWriteMask |
uint32_t |
Transmit PAUSE control frame counter |
TimeSource |
*void |
Time source object |
config.checkCrc |
uint8_t |
Enable ethernet frame CRC checking. |
config.generateCrc |
uint8_t |
Enable ethernet frame CRC generation. |
config.interfaceMode |
uint8_t |
Set interface mode |
config.irqError |
uint8_t |
IRQ number for eTSEC error |
config.irqReceive |
uint8_t |
IRQ number for eTSEC receieve event |
config.irqTransmit |
uint8_t |
IRQ number for eTSEC transmit event |
config.logRegisterAccess |
uint8_t |
Enable logging of register accesses |
config.logTraffic |
uint8_t |
Enable traffic logging |
irqCtrl |
temu_IfaceRef/ <unknown> |
IRQ controller |
mac |
*char |
Set MAC by string |
mdioBus |
temu_IfaceRef/ <unknown> |
MDIO bus |
memAccess |
temu_IfaceRef/ <unknown> |
Memory access (for DMA). |
phy |
temu_IfaceRef/ <unknown> |
PHY device |
Interfaces
| Name | Type | Description |
|---|---|---|
DeviceIface |
DeviceIface |
Device Interface |
MACIface |
temu::MACIface |
MAC interface |
MemAccessIface |
MemAccessIface |
Mem access interface |
RegisterIface |
temu::RegisterIface |
Auto-generated Register Interface Impl. |
ResetIface |
ResetIface |
Reset Interface |
Registers
| Register support is currently experimental! |
Register Bank Regs
Register TSEC_ID
- Description
-
Controller ID register
- Reset value
-
0x01240000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSEC_ID |
|
|
eTSEC identifier |
TSEC_REV_MJ |
|
|
eTSEC major revision |
TSEC_REV_MN |
|
|
eTSEC minor revision |
Register TSEC_ID2
- Description
-
Controller ID register 2
- Reset value
-
0x003000f0
- Warm reset mask
-
0x003f00ff
| Field | Mask | Reset | Description |
|---|---|---|---|
TSEC_INT |
|
|
Interface mode support |
TSEC_CFG |
|
|
eTSEC configuration options |
Register IEVENT
- Description
-
Interrupt event register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
BABR |
|
|
Babbling receive error |
RXC |
|
|
Receive control interrupt |
BSY |
|
|
Busy condition interrupt |
EBERR |
|
|
Internal bus error |
MSRO |
|
|
MIB counter overflow |
GTSC |
|
|
Graceful transmit stop complete |
BABT |
|
|
Babbling transmit error |
TXC |
|
|
Transmit control interrupt |
TXE |
|
|
Transmit error |
TXB |
|
|
Transmit buffer interrupt |
TXF |
|
|
Transmit frame interrupt |
LC |
|
|
Late collision |
CRL |
|
|
Collision retry limit |
XFUN |
|
|
Transmit FIFO underrun |
RXB |
|
|
Receive buffer interrupt |
MAG |
|
|
Magic Packet detected |
MMRD |
|
|
MII management read completion |
MMWR |
|
|
MII management write completion |
GRSC |
|
|
Graceful receive stop complete |
RXF |
|
|
Receive frame interrupt |
FGPI |
|
|
Filer generated general purpose interrupt |
FIR |
|
|
Receive queue filer result invalid |
FIQ |
|
|
Frame filed to invalid receive queue |
DPE |
|
|
Internal data parity error |
PERR |
|
|
Receive frame parse error |
Register IMASK
- Description
-
Interrupt mask register
- Reset value
-
0x00000000
- Warm reset mask
-
0xf7f78f9f
| Field | Mask | Reset | Description |
|---|---|---|---|
BREN |
|
|
Babbling receiver interrupt enable |
RXCEN |
|
|
Receive control interrupt enable |
BSYEN |
|
|
Busy interrupt enable |
EBERREN |
|
|
Internal bus error interrupt enable |
MSROEN |
|
|
MIB counter overflow interrupt enable |
GTSCEN |
|
|
Graceful transmit stop complete interrupt enable |
BTEN |
|
|
Babbling transmit interrupt enable |
TXCEN |
|
|
Transmit control interrupt enable |
TXEEN |
|
|
Transmit error interrupt enable |
TXBEN |
|
|
Transmit buffer interrupt enable |
TXFEN |
|
|
Transmit frame interrupt enable |
LCEN |
|
|
Late collision interrupt enable |
CRLEN |
|
|
Collision retry limit interrupt enable |
XFUNEN |
|
|
Transmit FIFO underrun interrupt enable |
RXBEN |
|
|
Receive buffer interrupt enable |
MAGEN |
|
|
Magic Packet interrupt enable |
MMRDEN |
|
|
MII management read completion interrupt enable |
MMWREN |
|
|
MII management write completion interrupt enable |
GRSCEN |
|
|
Graceful receive stop complete interrupt enable |
RXFEN |
|
|
Receive frame interrupt enable |
FGPIEN |
|
|
Filer generated interrupt enable |
FIREN |
|
|
Filer result invalid interrupt enable |
FIQEN |
|
|
Invalid receive queue interrupt enable |
DPEEN |
|
|
Data parity error interrupt enable |
PERREN |
|
|
Parse error interrupt enable |
Register EDIS
- Description
-
Error disabled register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register ECNTRL
- Description
-
Ethernet control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000707e
| Field | Mask | Reset | Description |
|---|---|---|---|
CLRCNT |
|
|
Clear all statistics counters and carry registers |
AUTOZ |
|
|
Automatically zero MIB counters and carry registers |
STEN |
|
|
MIB counter statistics enable |
GMIIM |
|
|
GMII interface mode |
TBIM |
|
|
Ten-bit interface mode |
RPM |
|
|
Reduced-pin mode for gigabit interfaces |
R100M |
|
|
RGMII/RMII 100 mode |
RMM |
|
|
Reduced-pin mode for 10/100 interfaces |
SGMIIM |
|
|
Serial GMII mode |
Register PTV
- Description
-
Pause time value register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
PTE |
|
|
Extended pause control |
PT |
|
|
Pause time value |
Register DMACTRL
- Description
-
DMA control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000080df
| Field | Mask | Reset | Description |
|---|---|---|---|
LE |
|
|
Little-endian descriptor mode enable |
TDSEN |
|
|
Tx data snoop enable |
TBDSEN |
|
|
TxBD snoop enable |
GRS |
|
|
Graceful receive stop |
GTS |
|
|
Graceful transmit stop |
TOD |
|
|
Transmit on demand for TxBD ring 0 |
WWR |
|
|
Write with response |
WOP |
|
|
Wait or poll for TxBD ring 0 |
Register TBIPA
- Description
-
TBI PHY address register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000001f
| Field | Mask | Reset | Description |
|---|---|---|---|
TBIPA |
|
|
TBI PHY address |
Register TCTRL
- Description
-
Transmit control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000781e
| Field | Mask | Reset | Description |
|---|---|---|---|
IPCSEN |
|
|
IP header checksum generation enable |
TUCSEN |
|
|
TCP/UDP checksum generation enable |
VLINS |
|
|
VLAN tag insertion enable |
THDF |
|
|
Transmit half-duplex flow control |
RFC_PAUSE |
|
|
Receive flow control pause frame |
TFC_PAUSE |
|
|
Transmit flow control pause frame |
TXSCHED |
|
|
Transmit ring scheduling algorithm |
Register TSTAT
- Description
-
Transmit status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
THLT0 |
|
|
Transmit halt of ring 0 |
THLT1 |
|
|
Transmit halt of ring 1 |
THLT2 |
|
|
Transmit halt of ring 2 |
THLT3 |
|
|
Transmit halt of ring 3 |
THLT4 |
|
|
Transmit halt of ring 4 |
THLT5 |
|
|
Transmit halt of ring 5 |
THLT6 |
|
|
Transmit halt of ring 6 |
THLT7 |
|
|
Transmit halt of ring 7 |
TXF0 |
|
|
Transmit frame event on ring 0 |
TXF1 |
|
|
Transmit frame event on ring 1 |
TXF2 |
|
|
Transmit frame event on ring 2 |
TXF3 |
|
|
Transmit frame event on ring 3 |
TXF4 |
|
|
Transmit frame event on ring 4 |
TXF5 |
|
|
Transmit frame event on ring 5 |
TXF6 |
|
|
Transmit frame event on ring 6 |
TXF7 |
|
|
Transmit frame event on ring 7 |
Register DFVLAN
- Description
-
Default VLAN control word
- Reset value
-
0x81000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TAG |
|
|
Default VLAN Ethertype |
PRI |
|
|
Default VLAN priority |
CFI |
|
|
Default VLAN canonical format indicator |
VID |
|
|
Default VLAN identifier |
Register TXIC
- Description
-
Transmit interrupt coalescing register
- Reset value
-
0x00000000
- Warm reset mask
-
0xdfe0ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
ICEN |
|
|
Interrupt coalescing enable |
ICCS |
|
|
Interrupt coalescing timer clock source |
ICFT |
|
|
Interrupt coalescing frame count threshold |
ICTT |
|
|
Interrupt coalescing timer threshold |
Register TQUEUE
- Description
-
Transmit queue control register
- Reset value
-
0x00008000
- Warm reset mask
-
0x0000ff00
| Field | Mask | Reset | Description |
|---|---|---|---|
EN0 |
|
|
Queue 0 enable |
EN1 |
|
|
Queue 1 enable |
EN2 |
|
|
Queue 2 enable |
EN3 |
|
|
Queue 3 enable |
EN4 |
|
|
Queue 4 enable |
EN5 |
|
|
Queue 5 enable |
EN6 |
|
|
Queue 6 enable |
EN7 |
|
|
Queue 7 enable |
Register TR03WT
- Description
-
TxBD rings 0-3 round-robin weightings
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
WT0 |
|
|
Ring 0 weighting |
WT1 |
|
|
Ring 1 weighting |
WT2 |
|
|
Ring 2 weighting |
WT3 |
|
|
Ring 3 weighting |
Register TR47WT
- Description
-
TxBD rings 4-7 round-robin weightings
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
WT4 |
|
|
Ring 4 weighting |
WT5 |
|
|
Ring 5 weighting |
WT6 |
|
|
Ring 6 weighting |
WT7 |
|
|
Ring 7 weighting |
Register TBDBPH
- Description
-
Tx data buffer pointer high bits
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
ADDRH |
|
|
High address bits |
Register TBASEH
- Description
-
TxBD base address high bits
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
ADDRH |
|
|
High address bits |
Register RCTRL
- Description
-
Receive control register
- Reset value
-
0x00000000
- Warm reset mask
-
0xff1f7fde
| Field | Mask | Reset | Description |
|---|---|---|---|
L2OFF |
|
|
Layer 2 offset |
TS |
|
|
Timestamp incoming packets as padding bytes |
PAL |
|
|
Packet alignment padding length |
LFC |
|
|
Lossless flow control |
VLEX |
|
|
VLAN tag extraction enable |
FILREN |
|
|
Receive frame filer enable |
FSQEN |
|
|
Single-queue filer mode enable |
GHTX |
|
|
Group address hash table extend |
IPCSEN |
|
|
IP checksum verification enable |
TUCSEN |
|
|
TCP/UDP checksum verification enable |
PRSDEP |
|
|
Parser control |
BC_REJ |
|
|
Broadcast frame reject |
PROM |
|
|
Promiscuous mode |
RSF |
|
|
Receive short frame mode |
EMEN |
|
|
Exact match MAC address enable |
Register RSTAT
- Description
-
Receive status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
QHLT0 |
|
|
Receive queue 0 halted |
QHLT1 |
|
|
Receive queue 1 halted |
QHLT2 |
|
|
Receive queue 2 halted |
QHLT3 |
|
|
Receive queue 3 halted |
QHLT4 |
|
|
Receive queue 4 halted |
QHLT5 |
|
|
Receive queue 5 halted |
QHLT6 |
|
|
Receive queue 6 halted |
QHLT7 |
|
|
Receive queue 7 halted |
RXF0 |
|
|
Receive frame event on ring 0 |
RXF1 |
|
|
Receive frame event on ring 1 |
RXF2 |
|
|
Receive frame event on ring 2 |
RXF3 |
|
|
Receive frame event on ring 3 |
RXF4 |
|
|
Receive frame event on ring 4 |
RXF5 |
|
|
Receive frame event on ring 5 |
RXF6 |
|
|
Receive frame event on ring 6 |
RXF7 |
|
|
Receive frame event on ring 7 |
Register RXIC
- Description
-
Receive interrupt coalescing register
- Reset value
-
0x00000000
- Warm reset mask
-
0xdfe0ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
ICEN |
|
|
Interrupt coalescing enable |
ICCS |
|
|
Interrupt coalescing timer clock source |
ICFT |
|
|
Interrupt coalescing frame count threshold |
ICTT |
|
|
Interrupt coalescing timer threshold |
Register RQUEUE
- Description
-
Receive queue control register
- Reset value
-
0x00800080
- Warm reset mask
-
0x00ff00ff
| Field | Mask | Reset | Description |
|---|---|---|---|
EX0 |
|
|
Receive queue 0 extract enable |
EX1 |
|
|
Receive queue 1 extract enable |
EX2 |
|
|
Receive queue 2 extract enable |
EX3 |
|
|
Receive queue 3 extract enable |
EX4 |
|
|
Receive queue 4 extract enable |
EX5 |
|
|
Receive queue 5 extract enable |
EX6 |
|
|
Receive queue 6 extract enable |
EX7 |
|
|
Receive queue 7 extract enable |
EN0 |
|
|
Receive queue 0 enable |
EN1 |
|
|
Receive queue 1 enable |
EN2 |
|
|
Receive queue 2 enable |
EN3 |
|
|
Receive queue 3 enable |
EN4 |
|
|
Receive queue 4 enable |
EN5 |
|
|
Receive queue 5 enable |
EN6 |
|
|
Receive queue 6 enable |
EN7 |
|
|
Receive queue 7 enable |
Register RBIFX
- Description
-
Receive bit field extract control register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
B0CTL |
|
|
Location of byte 0 |
B0OFFSET |
|
|
Offset of byte 0 |
B1CTL |
|
|
Location of byte 1 |
B1OFFSET |
|
|
Offset of byte 1 |
B2CTL |
|
|
Location of byte 2 |
B2OFFSET |
|
|
Offset of byte 2 |
B3CTL |
|
|
Location of byte 3 |
B3OFFSET |
|
|
Offset of byte 3 |
Register RQFAR
- Description
-
Receive queue filing table address register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
RQFAR |
|
|
Receive queue filer table index |
Register RQFCR
- Description
-
Receive queue filing table control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
GPI |
|
|
General purpose interrupt |
Q |
|
|
Receive queue index |
CLE |
|
|
Cluster entry/exit |
REJ |
|
|
Reject frame |
AND |
|
|
AND rule |
CMP |
|
|
Comparison operation |
PID |
|
|
Property identifier |
Register RQFPR
- Description
-
Receive queue filing table property register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MRBLR
- Description
-
Maximum receive buffer length register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffc0
| Field | Mask | Reset | Description |
|---|---|---|---|
MRBL |
|
|
Maximum receive buffer length |
Register RBDBPH
- Description
-
Rx data buffer pointer high bits
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
ADDRH |
|
|
High address bits |
Register RBASEH
- Description
-
RxBD base address high bits
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
ADDRH |
|
|
High address bits |
Register TMR_RXTS_H
- Description
-
Rx timer time stamp high
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_RXTS_L
- Description
-
Rx timer time stamp low
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACCFG1
- Description
-
MAC configuration register 1
- Reset value
-
0x00000000
- Warm reset mask
-
0x800f013f
| Field | Mask | Reset | Description |
|---|---|---|---|
Soft_Reset |
|
|
Soft reset |
Reset_Rx_MC |
|
|
Reset receive MAC control block |
Reset_Tx_MC |
|
|
Reset transmit MAC control block |
Reset_Rx_Fun |
|
|
Reset receive function block |
Reset_Tx_Fun |
|
|
Reset transmit function block |
Loop_Back |
|
|
Loop back |
Rx_Flow |
|
|
Receive flow |
Tx_Flow |
|
|
Transmit flow |
Syncd_Rx_EN |
|
|
Receive enable synchronized |
Rx_EN |
|
|
Receive enable |
Syncd_Tx_EN |
|
|
Transmit enable synchronized |
Tx_EN |
|
|
Transmit enable |
Register MACCFG2
- Description
-
MAC configuration register 2
- Reset value
-
0x00007000
- Warm reset mask
-
0x0000f3ff
| Field | Mask | Reset | Description |
|---|---|---|---|
Preamble_Length |
|
|
Preamble length |
I_F_Mode |
|
|
MAC interface mode |
PreAM_RxEN |
|
|
User defined preamble receive enable |
PreAM_TxEN |
|
|
User defined preamble transmit enable |
Huge_Frame |
|
|
Huge frame enable |
Length_check |
|
|
Length check |
MPEN |
|
|
Magic packet enable |
PAD_CRC |
|
|
Pad and append CRC |
CRC_EN |
|
|
CRC enable |
Full_Duplex |
|
|
Full duplex configure |
Register IPGIFG
- Description
-
Inter-packet/inter-frame gap register
- Reset value
-
0x40605060
- Warm reset mask
-
0x7f7fff7f
| Field | Mask | Reset | Description |
|---|---|---|---|
IPGR1 |
|
|
Non-back-to-back inter-packet-gap part 1 |
IPGR2 |
|
|
Non-back-to-back inter-packet-gap part 2 |
Minimum_IFG_Enforcement |
|
|
Minimum IFG enforcement |
IPGR3 |
|
|
Back-to-back inter-packet-gap |
Register HAFDUP
- Description
-
Half-duplex control register
- Reset value
-
0x00a1f037
- Warm reset mask
-
0x00fff03f
| Field | Mask | Reset | Description |
|---|---|---|---|
Alternate_BEB_Truncation |
|
|
Alternate binary exponential backoff truncation |
Alt_BEB |
|
|
Alternate binary exponential backoff |
BP_No_BackOff |
|
|
Back pressure no backoff |
No_BackOff |
|
|
No backoff |
Excess_Defer |
|
|
Excessively deferred |
Retransmission_Maximum |
|
|
Retransmission maximum |
Collision_Window |
|
|
Collision window |
Register MAXFRM
- Description
-
Maximum frame length register
- Reset value
-
0x00000600
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
Maximum_Frame |
|
|
Maximum frame length |
Register MIIMCFG
- Description
-
MII management configuration register
- Reset value
-
0x00000007
- Warm reset mask
-
0x80000017
| Field | Mask | Reset | Description |
|---|---|---|---|
Reset_Mgmt |
|
|
Reset MII management |
No_Pre |
|
|
Preamble suppress |
MgmtClk |
|
|
MII management clock |
Register MIIMCOM
- Description
-
MII management command register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
Scan_Cycle |
|
|
MII management scan cycle |
Read_Cycle |
|
|
MII management read cycle |
Register MIIMADD
- Description
-
MII management address register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00001f1f
| Field | Mask | Reset | Description |
|---|---|---|---|
PHY_Address |
|
|
MII management PHY address |
Register_Address |
|
|
MII management register address |
Register MIIMCON
- Description
-
MII management control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
PHY_Control |
|
|
MII management PHY control data |
Register MIIMSTAT
- Description
-
MII management status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
PHY_Status |
|
|
MII management PHY status data |
Register MIIMIND
- Description
-
MII management indicator register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000007
| Field | Mask | Reset | Description |
|---|---|---|---|
Not_Valid |
|
|
MII management read data not valid |
Scan |
|
|
MII management scan in progress |
Busy |
|
|
MII management busy |
Register IFSTAT
- Description
-
Interface status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000400
| Field | Mask | Reset | Description |
|---|---|---|---|
Excess_Defer |
|
|
Excessive defer status |
Register MACSTNADDR1
- Description
-
MAC station address register 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACSTNADDR2
- Description
-
MAC station address register 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TR64
- Description
-
Transmit and receive 64-byte frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TR127
- Description
-
Transmit and receive 65- to 127-byte frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TR255
- Description
-
Transmit and receive 128- to 255-byte frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TR511
- Description
-
Transmit and receive 256- to 511-byte frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TR1K
- Description
-
Transmit and receive 512- to 1023-byte frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TRMAX
- Description
-
Transmit and receive 1024- to 1518-byte frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TRMGV
- Description
-
Transmit and receive good VLAN frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RBYT
- Description
-
Receive byte counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RPKT
- Description
-
Receive packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RFCS
- Description
-
Receive FCS error counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RMCA
- Description
-
Receive multicast packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RBCA
- Description
-
Receive broadcast packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RXCF
- Description
-
Receive control frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RXPF
- Description
-
Receive PAUSE frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RXUO
- Description
-
Receive unknown opcode counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RALN
- Description
-
Receive alignment error counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RFLR
- Description
-
Receive frame length error counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RCSE
- Description
-
Receive carrier sense error counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RUND
- Description
-
Receive undersize packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register ROVR
- Description
-
Receive oversize packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RFRG
- Description
-
Receive fragments counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RJBR
- Description
-
Receive jabber counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RDRP
- Description
-
Receive drop counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TBYT
- Description
-
Transmit byte counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TPKT
- Description
-
Transmit packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMCA
- Description
-
Transmit multicast packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TBCA
- Description
-
Transmit broadcast packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TXPF
- Description
-
Transmit PAUSE control frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TDFR
- Description
-
Transmit deferral packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TEDF
- Description
-
Transmit excessive deferral packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TSCL
- Description
-
Transmit single collision packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMCL
- Description
-
Transmit multi collision packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TLCL
- Description
-
Transmit late collision packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TXCL
- Description
-
Transmit excessive collision packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TNCL
- Description
-
Transmit total collision packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TDRP
- Description
-
Transmit drop frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TJBR
- Description
-
Transmit jabber frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TFCS
- Description
-
Transmit FCS error counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TXCF
- Description
-
Transmit control frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TOVR
- Description
-
Transmit oversize frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TUND
- Description
-
Transmit undersize frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TFRG
- Description
-
Transmit fragments frame counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RREJ
- Description
-
Receive filer rejected packet counter
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register ATTR
- Description
-
Attribute register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00006cc0
| Field | Mask | Reset | Description |
|---|---|---|---|
ELCWT |
|
|
Extracted L2 cache write type |
BDLWT |
|
|
Buffer descriptor L2 cache write type |
RDSEN |
|
|
Rx data snoop enable |
RBDSEN |
|
|
RxBD snoop enable |
Register ATTRELI
- Description
-
Attribute extract length and extract index register
- Reset value
-
0x00000000
- Warm reset mask
-
0x3ff83fc0
| Field | Mask | Reset | Description |
|---|---|---|---|
EL |
|
|
Extracted length |
EI |
|
|
Extracted index |
Register TMR_CTRL
- Description
-
Timer control register
- Reset value
-
0x00010000
- Warm reset mask
-
0xdfffc3ef
| Field | Mask | Reset | Description |
|---|---|---|---|
ALM1P |
|
|
Alarm 1 output polarity |
ALM2P |
|
|
Alarm 2 output polarity |
FS |
|
|
FIPER start indication |
PP1L |
|
|
FIPER1 pulse loopback mode enable |
PP2L |
|
|
FIPER2 pulse loopback mode enable |
TCLK_PERIOD |
|
|
1588 timer reference clock period |
RTPE |
|
|
Record Tx timestamp to PAL enable |
FRD |
|
|
FIPER realignment disable |
ETEP2 |
|
|
External trigger 2 edge polarity |
ETEP1 |
|
|
External trigger 1 edge polarity |
COPH |
|
|
Generated clock output phase |
CIPH |
|
|
Oscillator input clock phase |
TMSR |
|
|
Timer soft reset |
BYP |
|
|
Bypass drift compensated clock |
TE |
|
|
1588 timer enable |
CKSEL |
|
|
1588 timer reference clock source select |
Register TMR_TEVENT
- Description
-
Time stamp event register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
ETS2 |
|
|
External trigger 2 timestamp sampled |
ETS1 |
|
|
External trigger 1 timestamp sampled |
ALM2 |
|
|
Alarm 2 time reached |
ALM1 |
|
|
Alarm 1 time reached |
PP1 |
|
|
Periodic pulse 1 generated |
PP2 |
|
|
Periodic pulse 2 generated |
Register TMR_TEMASK
- Description
-
Timer event mask register
- Reset value
-
0x00000000
- Warm reset mask
-
0x030300c0
| Field | Mask | Reset | Description |
|---|---|---|---|
ETS2EN |
|
|
External trigger 2 event enable |
ETS1EN |
|
|
External trigger 1 event enable |
ALM2EN |
|
|
Alarm 2 event enable |
ALM1EN |
|
|
Alarm 1 event enable |
PP1EN |
|
|
Periodic pulse 1 event enable |
PP2EN |
|
|
Periodic pulse 2 event enable |
Register TMR_PEVENT
- Description
-
PTP time stamp event register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000301
| Field | Mask | Reset | Description |
|---|---|---|---|
TXP2 |
|
|
PTP frame transmitted, timestamp set 2 |
TXP1 |
|
|
PTP frame transmitted, timestamp set 1 |
RXP |
|
|
PTP frame received |
Register TMR_PEMASK
- Description
-
PTP time stamp event mask register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000301
| Field | Mask | Reset | Description |
|---|---|---|---|
TXP2EN |
|
|
Transmit PTP packet event 2 enable |
TXP1EN |
|
|
Transmit PTP packet event 1 enable |
RXPEN |
|
|
Receive PTP packet event enable |
Register TMR_STAT
- Description
-
Time stamp status register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_CNT_H
- Description
-
Timer counter high register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_CNT_L
- Description
-
Timer counter low register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_ADD
- Description
-
Timer drift compensation addend register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_ACC
- Description
-
Timer accumulator register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_PRSC
- Description
-
Timer prescale register
- Reset value
-
0x00000002
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
PRSC_OCK |
|
|
Output clock division/prescale factor |
Register TMROFF_H
- Description
-
Timer offset high register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMROFF_L
- Description
-
Timer offset low register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TBPTR
- Description
-
TxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TBPTR
- Description
-
TxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TBPTR
- Description
-
TxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TBPTR
- Description
-
TxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TBPTR
- Description
-
TxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TBPTR
- Description
-
TxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TBPTR
- Description
-
TxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TBPTR
- Description
-
TxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TBASE
- Description
-
TxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register TBASE
- Description
-
TxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register TBASE
- Description
-
TxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register TBASE
- Description
-
TxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register TBASE
- Description
-
TxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register TBASE
- Description
-
TxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register TBASE
- Description
-
TxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register TBASE
- Description
-
TxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register TMR_TXTS_ID
- Description
-
Tx time stamp identification tag register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TXTS_ID |
|
|
Tx time stamp identification field |
Register TMR_TXTS_ID
- Description
-
Tx time stamp identification tag register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TXTS_ID |
|
|
Tx time stamp identification field |
Register TMR_TXTS_H
- Description
-
Tx time stamp high
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_TXTS_H
- Description
-
Tx time stamp high
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_TXTS_L
- Description
-
Tx time stamp low
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_TXTS_L
- Description
-
Tx time stamp low
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RBPTR
- Description
-
RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RBPTR
- Description
-
RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RBPTR
- Description
-
RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RBPTR
- Description
-
RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RBPTR
- Description
-
RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RBPTR
- Description
-
RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RBPTR
- Description
-
RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RBPTR
- Description
-
RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RBASE
- Description
-
RxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register RBASE
- Description
-
RxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register RBASE
- Description
-
RxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register RBASE
- Description
-
RxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register RBASE
- Description
-
RxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register RBASE
- Description
-
RxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register RBASE
- Description
-
RxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register RBASE
- Description
-
RxBD base address of ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
BASE |
|
|
8-byte aligned base address |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR1
- Description
-
MAC exact match address n, part 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register MACnADDR2
- Description
-
MAC exact match address n, part 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register CAR
- Description
-
Carry register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Write-one-to-clear value |
Register CAR
- Description
-
Carry register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Write-one-to-clear value |
Register CAM
- Description
-
Carry mask register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register CAM
- Description
-
Carry mask register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register IGADDR
- Description
-
Individual/group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register IGADDR
- Description
-
Individual/group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register IGADDR
- Description
-
Individual/group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register IGADDR
- Description
-
Individual/group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register IGADDR
- Description
-
Individual/group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register IGADDR
- Description
-
Individual/group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register IGADDR
- Description
-
Individual/group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register IGADDR
- Description
-
Individual/group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register GADDR
- Description
-
Group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register GADDR
- Description
-
Group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register GADDR
- Description
-
Group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register GADDR
- Description
-
Group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register GADDR
- Description
-
Group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register GADDR
- Description
-
Group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register GADDR
- Description
-
Group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register GADDR
- Description
-
Group address register n
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register RQPRM
- Description
-
Receive queue parameters register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FBTHR |
|
|
Free BD threshold |
LEN |
|
|
Ring length |
Register RQPRM
- Description
-
Receive queue parameters register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FBTHR |
|
|
Free BD threshold |
LEN |
|
|
Ring length |
Register RQPRM
- Description
-
Receive queue parameters register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FBTHR |
|
|
Free BD threshold |
LEN |
|
|
Ring length |
Register RQPRM
- Description
-
Receive queue parameters register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FBTHR |
|
|
Free BD threshold |
LEN |
|
|
Ring length |
Register RQPRM
- Description
-
Receive queue parameters register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FBTHR |
|
|
Free BD threshold |
LEN |
|
|
Ring length |
Register RQPRM
- Description
-
Receive queue parameters register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FBTHR |
|
|
Free BD threshold |
LEN |
|
|
Ring length |
Register RQPRM
- Description
-
Receive queue parameters register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FBTHR |
|
|
Free BD threshold |
LEN |
|
|
Ring length |
Register RQPRM
- Description
-
Receive queue parameters register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FBTHR |
|
|
Free BD threshold |
LEN |
|
|
Ring length |
Register RFBPTR
- Description
-
Last free RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RFBPTR
- Description
-
Last free RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RFBPTR
- Description
-
Last free RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RFBPTR
- Description
-
Last free RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RFBPTR
- Description
-
Last free RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RFBPTR
- Description
-
Last free RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RFBPTR
- Description
-
Last free RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register RFBPTR
- Description
-
Last free RxBD pointer for ring n
- Reset value
-
0x00000000
- Warm reset mask
-
0xfffffff8
| Field | Mask | Reset | Description |
|---|---|---|---|
PTR |
|
|
8-byte aligned pointer |
Register TMR_ALARM_H
- Description
-
Timer alarm high register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
ALARM_H |
|
|
Alarm time comparator upper half |
Register TMR_ALARM_H
- Description
-
Timer alarm high register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
ALARM_H |
|
|
Alarm time comparator upper half |
Register TMR_ALARM_L
- Description
-
Timer alarm low register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
ALARM_L |
|
|
Alarm time comparator lower half |
Register TMR_ALARM_L
- Description
-
Timer alarm low register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
ALARM_L |
|
|
Alarm time comparator lower half |
Register TMR_FIPER
- Description
-
Timer fixed period interval register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FIPER |
|
|
Fixed interval pulse period |
Register TMR_FIPER
- Description
-
Timer fixed period interval register
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FIPER |
|
|
Fixed interval pulse period |
Register TMR_ETTS_H
- Description
-
External trigger timestamp high register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |
Register TMR_ETTS_H
- Description
-
External trigger timestamp high register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VALUE |
|
|
Register value |