P2020 GUTS Model
This section describes the P2020 Global Utilities (GUTS) model.
@GUTS Reference
GUTS Reference
Properties
Name | Type | Description |
---|---|---|
AUTOSRTSR |
uint32_t |
Automatic reset status reg |
CLKOCR |
uint32_t |
Clock out control reg |
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
DDRCLKDR |
uint32_t |
DDR clock disable reg |
DEVDISR |
uint32_t |
Device disable control reg |
ECMCR |
uint32_t |
ECM control reg |
ECTRSTCR |
uint32_t |
Exception reset control reg |
IOVSELSR |
uint32_t |
IO voltage select status reg |
LoggingFlags |
uint64_t |
Flags for logging info |
MCPSUMR |
uint32_t |
Machine check summary reg |
Name |
*char |
Object name |
PMCDR |
uint32_t |
Power management disable reg |
PMUXCR |
uint32_t |
Alternate function signal multiplex control |
PORBMSR |
uint32_t |
POR boot mode status reg |
PORDBGMSR |
uint32_t |
POR debug mode status reg |
PORDEVSR |
uint32_t |
POR device status reg |
PORDEVSR2 |
uint32_t |
POR device status reg 2 |
PORGPPORCR |
uint32_t |
General-purpose POR configuration reg |
PORPLLSR |
uint32_t |
POR PLL ratio status reg |
POWMGTCSR |
uint32_t |
Power management control and status reg |
PVR |
uint32_t |
Processor version reg |
RSTCR |
uint32_t |
Reset control reg |
RSTRSCR |
uint32_t |
Reset request status and control reg |
SDHCDCR |
uint32_t |
SDHC debug control reg |
SRDSCR |
[uint32_t; 7] |
SRDS control reg |
SVR |
uint32_t |
System version reg |
TimeSource |
*void |
Time source object |
Registers
Register support is currently experimental! |
Register Bank default
Register AUTOSRTSR
- Description
-
Automatic reset status reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register CLKOCR
- Description
-
Clock out control reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register DDRCLKDR
- Description
-
DDR clock disable reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register DEVDISR
- Description
-
Device disable control reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register ECMCR
- Description
-
ECM control reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register ECTRSTCR
- Description
-
Exception reset control reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register IOVSELSR
- Description
-
IO voltage select status reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register MCPSUMR
- Description
-
Machine check summary reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PMCDR
- Description
-
Power management disable reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PMUXCR
- Description
-
Alternate function signal multiplex control
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PORBMSR
- Description
-
POR boot mode status reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PORDBGMSR
- Description
-
POR debug mode status reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PORDEVSR
- Description
-
POR device status reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PORDEVSR2
- Description
-
POR device status reg 2
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PORGPPORCR
- Description
-
General-purpose POR configuration reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PORPLLSR
- Description
-
POR PLL ratio status reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register POWMGTCSR
- Description
-
Power management control and status reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register PVR
- Description
-
Processor version reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register RSTCR
- Description
-
Reset control reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register RSTRSCR
- Description
-
Reset request status and control reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register SDHCDCR
- Description
-
SDHC debug control reg
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |