P2020 GUTS Model

This section describes the P2020 Global Utilities (GUTS) model.

Loading the Plugin

import P2020

Configuration

@GUTS Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @GUTS

new

Create new instance of GUTS

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

GUTS Reference

Properties

Name Type Description

AUTORSTSRColdResetValue

uint32_t

Automatic reset status register

AUTORSTSRForcedBits

uint32_t

Automatic reset status register

AUTORSTSRForcedFlippedBits

uint32_t

Automatic reset status register

AUTORSTSRReadMask

uint32_t

Automatic reset status register

AUTORSTSRResetMask

uint32_t

Automatic reset status register

AUTORSTSRResetValue

uint32_t

Automatic reset status register

AUTORSTSRWriteMask

uint32_t

Automatic reset status register

AUTOSRTSR

uint32_t

Automatic reset status register

CLKOCR

uint32_t

Clock out control register

CLKOCRColdResetValue

uint32_t

Clock out control register

CLKOCRForcedBits

uint32_t

Clock out control register

CLKOCRForcedFlippedBits

uint32_t

Clock out control register

CLKOCRReadMask

uint32_t

Clock out control register

CLKOCRResetMask

uint32_t

Clock out control register

CLKOCRResetValue

uint32_t

Clock out control register

CLKOCRWriteMask

uint32_t

Clock out control register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

DDRCLKDR

uint32_t

DDR clock disable register

DDRCLKDRColdResetValue

uint32_t

DDR clock disable register

DDRCLKDRForcedBits

uint32_t

DDR clock disable register

DDRCLKDRForcedFlippedBits

uint32_t

DDR clock disable register

DDRCLKDRReadMask

uint32_t

DDR clock disable register

DDRCLKDRResetMask

uint32_t

DDR clock disable register

DDRCLKDRResetValue

uint32_t

DDR clock disable register

DDRCLKDRWriteMask

uint32_t

DDR clock disable register

DEVDISR

uint32_t

Device disable control register

DEVDISRColdResetValue

uint32_t

Device disable control register

DEVDISRForcedBits

uint32_t

Device disable control register

DEVDISRForcedFlippedBits

uint32_t

Device disable control register

DEVDISRReadMask

uint32_t

Device disable control register

DEVDISRResetMask

uint32_t

Device disable control register

DEVDISRResetValue

uint32_t

Device disable control register

DEVDISRWriteMask

uint32_t

Device disable control register

ECMCR

uint32_t

ECM control register

ECMCRColdResetValue

uint32_t

ECM control register

ECMCRForcedBits

uint32_t

ECM control register

ECMCRForcedFlippedBits

uint32_t

ECM control register

ECMCRReadMask

uint32_t

ECM control register

ECMCRResetMask

uint32_t

ECM control register

ECMCRResetValue

uint32_t

ECM control register

ECMCRWriteMask

uint32_t

ECM control register

ECTRSTCR

uint32_t

Exception reset control register

ECTRSTCRColdResetValue

uint32_t

Exception reset control register

ECTRSTCRForcedBits

uint32_t

Exception reset control register

ECTRSTCRForcedFlippedBits

uint32_t

Exception reset control register

ECTRSTCRReadMask

uint32_t

Exception reset control register

ECTRSTCRResetMask

uint32_t

Exception reset control register

ECTRSTCRResetValue

uint32_t

Exception reset control register

ECTRSTCRWriteMask

uint32_t

Exception reset control register

GPPORCRColdResetValue

uint32_t

General-purpose POR configuration register

GPPORCRForcedBits

uint32_t

General-purpose POR configuration register

GPPORCRForcedFlippedBits

uint32_t

General-purpose POR configuration register

GPPORCRReadMask

uint32_t

General-purpose POR configuration register

GPPORCRResetMask

uint32_t

General-purpose POR configuration register

GPPORCRResetValue

uint32_t

General-purpose POR configuration register

GPPORCRWriteMask

uint32_t

General-purpose POR configuration register

IOVSELSR

uint32_t

IO voltage select status register

IOVSELSRColdResetValue

uint32_t

IO voltage select status register

IOVSELSRForcedBits

uint32_t

IO voltage select status register

IOVSELSRForcedFlippedBits

uint32_t

IO voltage select status register

IOVSELSRReadMask

uint32_t

IO voltage select status register

IOVSELSRResetMask

uint32_t

IO voltage select status register

IOVSELSRResetValue

uint32_t

IO voltage select status register

IOVSELSRWriteMask

uint32_t

IO voltage select status register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

MCPSUMR

uint32_t

Machine check summary register

MCPSUMRColdResetValue

uint32_t

Machine check summary register

MCPSUMRForcedBits

uint32_t

Machine check summary register

MCPSUMRForcedFlippedBits

uint32_t

Machine check summary register

MCPSUMRReadMask

uint32_t

Machine check summary register

MCPSUMRResetMask

uint32_t

Machine check summary register

MCPSUMRResetValue

uint32_t

Machine check summary register

MCPSUMRWriteMask

uint32_t

Machine check summary register

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

PMCDR

uint32_t

Power management clock disable register

PMCDRColdResetValue

uint32_t

Power management clock disable register

PMCDRForcedBits

uint32_t

Power management clock disable register

PMCDRForcedFlippedBits

uint32_t

Power management clock disable register

PMCDRReadMask

uint32_t

Power management clock disable register

PMCDRResetMask

uint32_t

Power management clock disable register

PMCDRResetValue

uint32_t

Power management clock disable register

PMCDRWriteMask

uint32_t

Power management clock disable register

PMUXCR

uint32_t

Alternate function signal multiplex control register

PMUXCRColdResetValue

uint32_t

Alternate function signal multiplex control register

PMUXCRForcedBits

uint32_t

Alternate function signal multiplex control register

PMUXCRForcedFlippedBits

uint32_t

Alternate function signal multiplex control register

PMUXCRReadMask

uint32_t

Alternate function signal multiplex control register

PMUXCRResetMask

uint32_t

Alternate function signal multiplex control register

PMUXCRResetValue

uint32_t

Alternate function signal multiplex control register

PMUXCRWriteMask

uint32_t

Alternate function signal multiplex control register

PORBMSR

uint32_t

POR boot mode status register

PORBMSRColdResetValue

uint32_t

POR boot mode status register

PORBMSRForcedBits

uint32_t

POR boot mode status register

PORBMSRForcedFlippedBits

uint32_t

POR boot mode status register

PORBMSRReadMask

uint32_t

POR boot mode status register

PORBMSRResetMask

uint32_t

POR boot mode status register

PORBMSRResetValue

uint32_t

POR boot mode status register

PORBMSRWriteMask

uint32_t

POR boot mode status register

PORDBGMSR

uint32_t

POR debug mode status register

PORDBGMSRColdResetValue

uint32_t

POR debug mode status register

PORDBGMSRForcedBits

uint32_t

POR debug mode status register

PORDBGMSRForcedFlippedBits

uint32_t

POR debug mode status register

PORDBGMSRReadMask

uint32_t

POR debug mode status register

PORDBGMSRResetMask

uint32_t

POR debug mode status register

PORDBGMSRResetValue

uint32_t

POR debug mode status register

PORDBGMSRWriteMask

uint32_t

POR debug mode status register

PORDEVSR

uint32_t

POR device status register

PORDEVSR2

uint32_t

POR device status register 2

PORDEVSR2ColdResetValue

uint32_t

POR device status register 2

PORDEVSR2ForcedBits

uint32_t

POR device status register 2

PORDEVSR2ForcedFlippedBits

uint32_t

POR device status register 2

PORDEVSR2ReadMask

uint32_t

POR device status register 2

PORDEVSR2ResetMask

uint32_t

POR device status register 2

PORDEVSR2ResetValue

uint32_t

POR device status register 2

PORDEVSR2WriteMask

uint32_t

POR device status register 2

PORDEVSRColdResetValue

uint32_t

POR device status register

PORDEVSRForcedBits

uint32_t

POR device status register

PORDEVSRForcedFlippedBits

uint32_t

POR device status register

PORDEVSRReadMask

uint32_t

POR device status register

PORDEVSRResetMask

uint32_t

POR device status register

PORDEVSRResetValue

uint32_t

POR device status register

PORDEVSRWriteMask

uint32_t

POR device status register

PORGPPORCR

uint32_t

General-purpose POR configuration register

PORPLLSR

uint32_t

POR PLL ratio status register

PORPLLSRColdResetValue

uint32_t

POR PLL ratio status register

PORPLLSRForcedBits

uint32_t

POR PLL ratio status register

PORPLLSRForcedFlippedBits

uint32_t

POR PLL ratio status register

PORPLLSRReadMask

uint32_t

POR PLL ratio status register

PORPLLSRResetMask

uint32_t

POR PLL ratio status register

PORPLLSRResetValue

uint32_t

POR PLL ratio status register

PORPLLSRWriteMask

uint32_t

POR PLL ratio status register

POWMGTCSR

uint32_t

Power management control and status register

POWMGTCSRColdResetValue

uint32_t

Power management control and status register

POWMGTCSRForcedBits

uint32_t

Power management control and status register

POWMGTCSRForcedFlippedBits

uint32_t

Power management control and status register

POWMGTCSRReadMask

uint32_t

Power management control and status register

POWMGTCSRResetMask

uint32_t

Power management control and status register

POWMGTCSRResetValue

uint32_t

Power management control and status register

POWMGTCSRWriteMask

uint32_t

Power management control and status register

PVR

uint32_t

Processor version register

PVRColdResetValue

uint32_t

Processor version register

PVRForcedBits

uint32_t

Processor version register

PVRForcedFlippedBits

uint32_t

Processor version register

PVRReadMask

uint32_t

Processor version register

PVRResetMask

uint32_t

Processor version register

PVRResetValue

uint32_t

Processor version register

PVRWriteMask

uint32_t

Processor version register

RSTCR

uint32_t

Reset control register

RSTCRColdResetValue

uint32_t

Reset control register

RSTCRForcedBits

uint32_t

Reset control register

RSTCRForcedFlippedBits

uint32_t

Reset control register

RSTCRReadMask

uint32_t

Reset control register

RSTCRResetMask

uint32_t

Reset control register

RSTCRResetValue

uint32_t

Reset control register

RSTCRWriteMask

uint32_t

Reset control register

RSTRSCR

uint32_t

Reset request status and control register

RSTRSCRColdResetValue

uint32_t

Reset request status and control register

RSTRSCRForcedBits

uint32_t

Reset request status and control register

RSTRSCRForcedFlippedBits

uint32_t

Reset request status and control register

RSTRSCRReadMask

uint32_t

Reset request status and control register

RSTRSCRResetMask

uint32_t

Reset request status and control register

RSTRSCRResetValue

uint32_t

Reset request status and control register

RSTRSCRWriteMask

uint32_t

Reset request status and control register

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

SDHCDCR

uint32_t

SDHC debug control register

SDHCDCRColdResetValue

uint32_t

SDHC debug control register

SDHCDCRForcedBits

uint32_t

SDHC debug control register

SDHCDCRForcedFlippedBits

uint32_t

SDHC debug control register

SDHCDCRReadMask

uint32_t

SDHC debug control register

SDHCDCRResetMask

uint32_t

SDHC debug control register

SDHCDCRResetValue

uint32_t

SDHC debug control register

SDHCDCRWriteMask

uint32_t

SDHC debug control register

SRDSCR0

uint32_t

SRDS control register 0

SRDSCR0ColdResetValue

uint32_t

SRDS control register 0

SRDSCR0ForcedBits

uint32_t

SRDS control register 0

SRDSCR0ForcedFlippedBits

uint32_t

SRDS control register 0

SRDSCR0ReadMask

uint32_t

SRDS control register 0

SRDSCR0ResetMask

uint32_t

SRDS control register 0

SRDSCR0ResetValue

uint32_t

SRDS control register 0

SRDSCR0WriteMask

uint32_t

SRDS control register 0

SRDSCR1

uint32_t

SRDS control register 1

SRDSCR1ColdResetValue

uint32_t

SRDS control register 1

SRDSCR1ForcedBits

uint32_t

SRDS control register 1

SRDSCR1ForcedFlippedBits

uint32_t

SRDS control register 1

SRDSCR1ReadMask

uint32_t

SRDS control register 1

SRDSCR1ResetMask

uint32_t

SRDS control register 1

SRDSCR1ResetValue

uint32_t

SRDS control register 1

SRDSCR1WriteMask

uint32_t

SRDS control register 1

SRDSCR2

uint32_t

SRDS control register 2

SRDSCR2ColdResetValue

uint32_t

SRDS control register 2

SRDSCR2ForcedBits

uint32_t

SRDS control register 2

SRDSCR2ForcedFlippedBits

uint32_t

SRDS control register 2

SRDSCR2ReadMask

uint32_t

SRDS control register 2

SRDSCR2ResetMask

uint32_t

SRDS control register 2

SRDSCR2ResetValue

uint32_t

SRDS control register 2

SRDSCR2WriteMask

uint32_t

SRDS control register 2

SRDSCR4

uint32_t

SRDS control register 4

SRDSCR4ColdResetValue

uint32_t

SRDS control register 4

SRDSCR4ForcedBits

uint32_t

SRDS control register 4

SRDSCR4ForcedFlippedBits

uint32_t

SRDS control register 4

SRDSCR4ReadMask

uint32_t

SRDS control register 4

SRDSCR4ResetMask

uint32_t

SRDS control register 4

SRDSCR4ResetValue

uint32_t

SRDS control register 4

SRDSCR4WriteMask

uint32_t

SRDS control register 4

SRDSCR5

uint32_t

SRDS control register 5

SRDSCR5ColdResetValue

uint32_t

SRDS control register 5

SRDSCR5ForcedBits

uint32_t

SRDS control register 5

SRDSCR5ForcedFlippedBits

uint32_t

SRDS control register 5

SRDSCR5ReadMask

uint32_t

SRDS control register 5

SRDSCR5ResetMask

uint32_t

SRDS control register 5

SRDSCR5ResetValue

uint32_t

SRDS control register 5

SRDSCR5WriteMask

uint32_t

SRDS control register 5

SRDSCR6

uint32_t

SRDS control register 6

SRDSCR6ColdResetValue

uint32_t

SRDS control register 6

SRDSCR6ForcedBits

uint32_t

SRDS control register 6

SRDSCR6ForcedFlippedBits

uint32_t

SRDS control register 6

SRDSCR6ReadMask

uint32_t

SRDS control register 6

SRDSCR6ResetMask

uint32_t

SRDS control register 6

SRDSCR6ResetValue

uint32_t

SRDS control register 6

SRDSCR6WriteMask

uint32_t

SRDS control register 6

SVR

uint32_t

System version register

SVRColdResetValue

uint32_t

System version register

SVRForcedBits

uint32_t

System version register

SVRForcedFlippedBits

uint32_t

System version register

SVRReadMask

uint32_t

System version register

SVRResetMask

uint32_t

System version register

SVRResetValue

uint32_t

System version register

SVRWriteMask

uint32_t

System version register

TimeSource

*void

Time source object

resetTarget

temu_IfaceRef/ <unknown>

Reset target

Interfaces

Name Type Description

DeviceIface

DeviceIface

Device Interface

MemAccessIface

MemAccessIface

Memory access interface

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Reset Interface

Registers

Register support is currently experimental!

Register Bank Regs

Register PORPLLSR
Description

POR PLL ratio status register

Reset value

0x02010e02

Warm reset mask

0x3f3f3e3e

Diagram
Field Mask Reset Description

e500_1_Ratio

0x3f000000

0x2

Clock ratio between e500 core 1 and CCB

e500_0_Ratio

0x003f0000

0x1

Clock ratio between e500 core 0 and CCB

DDR_Ratio

0x00003e00

0x7

Clock ratio between DDR complex clock and DDRCLK

Plat_Ratio

0x0000003e

0x1

Clock ratio between CCB and SYSCLK
Register PORBMSR
Description

POR boot mode status register

Reset value

0x8f370000

Warm reset mask

0xcf370000

Diagram
Field Mask Reset Description

BCFG

0xc0000000

0x2

CPU boot configuration

ROM_LOC

0x0f000000

0xf

Location of boot ROM

BSCFG

0x00300000

0x3

Boot sequencer configuration

HA

0x00070000

0x7

Host/agent mode configuration
Register PORDEVSR
Description

POR device status register

Reset value

0x9b183c00

Warm reset mask

0x9b793c4f

Diagram
Field Mask Reset Description

ECW

0x80000000

0x1

eTSEC1 and eTSEC2 controller width

SGMII2_DIS

0x10000000

0x1

eTSEC2 in SGMII mode disabled

SGMII3_DIS

0x08000000

0x1

eTSEC3 SGMII mode disabled

ECP1

0x03000000

0x3

eTSEC1 controller protocol

IO_SEL

0x00780000

0x3

I/O port selection mode

LECC

0x00010000

0x0

eLBC ECC enable

ECP2

0x00003000

0x3

eTSEC2 controller protocol

ECP3

0x00000c00

0x3

eTSEC3 controller protocol

RTYPE

0x00000040

0x0

DRAM type for DDR controller

RIO_CTLS

0x00000008

0x0

RapidIO system size

DEV_ID

0x00000007

0x0

Serial RapidIO device ID
Register PORDBGMSR
Description

POR debug mode status register

Reset value

0x00000000

Warm reset mask

0x05000000

Diagram
Field Mask Reset Description

MEM_SEL

0x04000000

0x0

Memory select

DDR_DBG

0x01000000

0x0

DDR controller debug configuration
Register PORDEVSR2
Description

POR device status register 2

Reset value

0x00000000

Warm reset mask

0x01ff25e0

Diagram
Field Mask Reset Description

ENG_USE7

0x01000000

0x0

Future engineering use 7

ENG_USE6

0x00800000

0x0

Future engineering use 6

ENG_USE5

0x00400000

0x0

Future engineering use 5

SRDS_PLL_TOE

0x00200000

0x0

SerDes PLL lock time-out counter

ENG_USE3

0x00100000

0x0

Future engineering use 3

CORE0_SPEED

0x00080000

0x0

Core 0 speed

CORE1_SPEED

0x00040000

0x0

Core 1 speed

PLAT_SPEED

0x00020000

0x0

Platform speed

DDR_SPEED

0x00010000

0x0

DDR speed

SRDS_REFCLK

0x00002000

0x0

SerDes reference clock

SYS_SPEED

0x00000400

0x0

System speed

SDHC_CD_POL_SEL

0x00000100

0x0

eSDHC card-detect polarity select

ENG_USE2

0x00000080

0x0

Future engineering use 2

ENG_USE1

0x00000040

0x0

Future engineering use 1

ENG_USE0

0x00000020

0x0

Future engineering use 0
Register GPPORCR
Description

General-purpose POR configuration register

Reset value

0x00000000

Warm reset mask

0xffff0000

Diagram
Field Mask Reset Description

POR_CFG_VEC

0xffff0000

0x0

General-purpose POR configuration vector
Register PMUXCR
Description

Alternate function signal multiplex control register

Reset value

0x00000000

Warm reset mask

0xe6070000

Diagram
Field Mask Reset Description

SD_DATA

0x80000000

0x0

Expose SDHC_DAT[4:7] signals

SDHC_CD

0x40000000

0x0

Expose SDHC_CD_B signal

SDHC_WP

0x20000000

0x0

Expose SDHC_WP signal

TSEC3_TS_USB

0x06000000

0x0

Expose USB_PCTL0 and USB_PCTL1 signals

TSEC1_CLK125

0x00040000

0x0

TSEC1 125 MHz reference clock source

TSEC2_CLK125

0x00020000

0x0

TSEC2 125 MHz reference clock source

DMA2_1

0x00010000

0x0

Expose DMA2 channel 1 signals
Register DEVDISR
Description

Device disable control register

Reset value

0x00000000

Warm reset mask

0x2fa9f6ee

Diagram
Field Mask Reset Description

PCIE1

0x20000000

0x0

PCI Express 1 controller disable

eLBC

0x08000000

0x0

Local bus controller disable

PCIE2

0x04000000

0x0

PCI Express 2 controller disable

PCIE3

0x02000000

0x0

PCI Express 3 controller disable

SEC

0x01000000

0x0

Security block disable

USB

0x00800000

0x0

USB disable

eSDHC

0x00200000

0x0

eSDHC disable

SRIO12

0x00080000

0x0

Serial RapidIO 1 and 2 controller disable

DDR

0x00010000

0x0

DDR controller disable

E500_CORE0

0x00008000

0x0

e500 core 0 disable

TB0

0x00004000

0x0

e500 core 0 time base disable

E500_CORE1

0x00002000

0x0

e500 core 1 disable

TB1

0x00001000

0x0

e500 core 1 time base disable

DMA1

0x00000400

0x0

DMA 1 controller disable

DMA2

0x00000200

0x0

DMA 2 controller disable

TSEC1

0x00000080

0x0

Three-speed Ethernet controller 1 disable

TSEC2

0x00000040

0x0

Three-speed Ethernet controller 2 disable

TSEC3

0x00000020

0x0

Three-speed Ethernet controller 3 disable

SPI

0x00000008

0x0

SPI controller disable

I2C

0x00000004

0x0

I2C controllers disable

DUART

0x00000002

0x0

Dual UART controller disable
Register POWMGTCSR
Description

Power management control and status register

Reset value

0x00000000

Warm reset mask

0xf00e003e

Diagram
Field Mask Reset Description

CORE0_IRQ_MSK

0x80000000

0x0

Core 0 interrupt input mask

CORE0_CI_MSK

0x40000000

0x0

Core 0 critical interrupt input mask

CORE1_IRQ_MSK

0x20000000

0x0

Core 1 interrupt input mask

CORE1_CI_MSK

0x10000000

0x0

Core 1 critical interrupt input mask

CORE0_DOZ

0x00080000

0x0

Core 0 doze mode

CORE1_DOZ

0x00040000

0x0

Core 1 doze mode

SLP

0x00020000

0x0

Sleep mode

CORE1_DOZING

0x00000020

0x0

Core 1 doze status

CORE1_NAPPING

0x00000010

0x0

Core 1 nap status

CORE0_DOZING

0x00000008

0x0

Core 0 doze status

CORE0_NAPPING

0x00000004

0x0

Core 0 nap status

SLPING

0x00000002

0x0

Sleep status
Register PMCDR
Description

Power management clock disable register

Reset value

0x000000e0

Warm reset mask

0x000000e0

Diagram
Field Mask Reset Description

TSEC1

0x00000080

0x1

TSEC1 disable clock in sleep mode

TSEC2

0x00000040

0x1

TSEC2 disable clock in sleep mode

TSEC3

0x00000020

0x1

TSEC3 disable clock in sleep mode
Register MCPSUMR
Description

Machine check summary register

Reset value

0x00000000

Warm reset mask

0x00000000

Diagram
Field Mask Reset Description

MCP1_CKSTP_P0

0x00000080

-

Machine check to core 1 from core 0 checkstop

MCP0_CKSTP_P1

0x00000040

-

Machine check to core 0 from core 1 checkstop

WRS1

0x00000020

-

Core 1 watchdog timer machine check

MCP1_IN

0x00000010

-

MCP1_B signal asserted

WRS0

0x00000004

-

Core 0 watchdog timer machine check

SRESET

0x00000002

-

Soft reset machine check

MCP0_IN

0x00000001

-

MCP0_B signal asserted
Register RSTRSCR
Description

Reset request status and control register

Reset value

0x00000000

Warm reset mask

0x81fc0000

Diagram
Field Mask Reset Description

SRIO_MSK

0x80000000

0x0

Serial RapidIO reset request mask

SRIO1_RR

0x01000000

0x0

Serial RapidIO 1 reset request

SRIO2_RR

0x00800000

0x0

Serial RapidIO 2 reset request

NFLSH_RR

0x00400000

0x0

NAND Flash ECC boot reset request

BS_RR

0x00200000

0x0

Boot sequence reset request

WDT0_RR

0x00100000

0x0

Core 0 watchdog timer reset request

SW_RR

0x00080000

0x0

Software reset request

WDT1_RR

0x00040000

0x0

Core 1 watchdog timer reset request
Register ECTRSTCR
Description

Exception reset control register

Reset value

0x00000000

Warm reset mask

0xccc00000

Diagram
Field Mask Reset Description

RST_CKSTP_P0_EN

0x80000000

0x0

Enable automatic reset of core 0 on checkstop

RST_CKSTP_P1_EN

0x40000000

0x0

Enable automatic reset of core 1 on checkstop

CKSTP_OUT0_DIS

0x08000000

0x0

Disable assertion of CKSTP_OUT0_B

CKSTP_OUT1_DIS

0x04000000

0x0

Disable assertion of CKSTP_OUT1_B

MCP0_CKSTP_P1_EN

0x00800000

0x0

Enable machine check to core 0 from core 1 checkstop

MCP1_CKSTP_P0_EN

0x00400000

0x0

Enable machine check to core 1 from core 0 checkstop
Register AUTORSTSR
Description

Automatic reset status register

Reset value

0x00000000

Warm reset mask

0x0000c000

Diagram
Field Mask Reset Description

RST_CKSTP_P0

0x80000000

-

Core 0 was reset in response to checkstop

RST_CKSTP_P1

0x40000000

-

Core 1 was reset in response to checkstop

RST_MPIC_P0

0x00800000

-

Core 0 was reset in response to MPIC reset request

RST_MPIC_P1

0x00400000

-

Core 1 was reset in response to MPIC reset request

RST_CORE_P0

0x00080000

-

Core 0 was reset in response to internal core request

RST_CORE_P1

0x00040000

-

Core 1 was reset in response to internal core request

READY_P0

0x00008000

0x0

Core 0 ready pin

READY_P1

0x00004000

0x0

Core 1 ready pin
Register PVR
Description

Processor version register

Reset value

0x80211051

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

Version

0xffff0000

0x8021

Processor version

Revision

0x0000ffff

0x1051

Processor revision
Register SVR
Description

System version register

Reset value

0x80e20021

Warm reset mask

0xffffffff

Diagram
Field Mask Reset Description

SV

0xffffffff

0x80e20021

System version number
Register RSTCR
Description

Reset control register

Reset value

0x00000000

Warm reset mask

0x00000002

Diagram
Field Mask Reset Description

HRESET_REQ

0x00000002

0x0

Hardware reset request
Register IOVSELSR
Description

IO voltage select status register

Reset value

0x00000000

Warm reset mask

0x00000333

Diagram
Field Mask Reset Description

CVDDV

0x00000300

0x0

CVDD I/O voltage selection

BVDDV

0x00000030

0x0

BVDD I/O voltage selection

LVDDV

0x00000003

0x0

LVDD I/O voltage selection
Register DDRCLKDR
Description

DDR clock disable register

Reset value

0x00000000

Warm reset mask

0x0000003f

Diagram
Field Mask Reset Description

DDR_MCK0_DIS

0x00000020

0x0

DDR controller clock 0 disable

DDR_MCK1_DIS

0x00000010

0x0

DDR controller clock 1 disable

DDR_MCK2_DIS

0x00000008

0x0

DDR controller clock 2 disable

DDR_MCK3_DIS

0x00000004

0x0

DDR controller clock 3 disable

DDR_MCK4_DIS

0x00000002

0x0

DDR controller clock 4 disable

DDR_MCK5_DIS

0x00000001

0x0

DDR controller clock 5 disable
Register CLKOCR
Description

Clock out control register

Reset value

0x00000000

Warm reset mask

0x8000003f

Diagram
Field Mask Reset Description

ENB

0x80000000

0x0

Clock out enable

CLK_SEL

0x0000003f

0x0

Clock out select
Register ECMCR
Description

ECM control register

Reset value

0x00000000

Warm reset mask

0xff000000

Diagram
Field Mask Reset Description

USB_UPRADR

0xf0000000

0x0

Uppermost USB address bits

ESDHC_UPRADR

0x0f000000

0x0

Uppermost ESDHC address bits
Register SDHCDCR
Description

SDHC debug control register

Reset value

0x00000000

Warm reset mask

0x80000000

Diagram
Field Mask Reset Description

CD_INV

0x80000000

0x0

Card-detect inversion
Register SRDSCR0
Description

SRDS control register 0

Reset value

0x00000030

Warm reset mask

0x000077f0

Diagram
Field Mask Reset Description

TXEQ0

0x00007000

0x0

Transmit equalization selection for lane 0

TXEQ1

0x00000700

0x0

Transmit equalization selection for lane 1

SDPD

0x000000f0

0x3

SerDes power down control
Register SRDSCR1
Description

SRDS control register 1

Reset value

0x00000000

Warm reset mask

0x00007700

Diagram
Field Mask Reset Description

TXEQ2

0x00007000

0x0

Transmit equalization selection for lane 2

TXEQ3

0x00000700

0x0

Transmit equalization selection for lane 3
Register SRDSCR2
Description

SRDS control register 2

Reset value

0x00000000

Warm reset mask

0xcc330000

Diagram
Field Mask Reset Description

PD0

0x80000000

0x0

Lane 0 power down

PD1

0x40000000

0x0

Lane 1 power down

PD2

0x08000000

0x0

Lane 2 power down

PD3

0x04000000

0x0

Lane 3 power down

X3S0

0x00200000

0x0

Lane 0 transmitter three-state

X3S1

0x00100000

0x0

Lane 1 transmitter three-state

X3S2

0x00020000

0x0

Lane 2 transmitter three-state

X3S3

0x00010000

0x0

Lane 3 transmitter three-state
Register SRDSCR4
Description

SRDS control register 4

Reset value

0x00000000

Warm reset mask

0x00001c1c

Diagram
Field Mask Reset Description

LSTS2

0x00001c00

0x0

Receiver electrical idle detection control for lane 2

LSTS3

0x0000001c

0x0

Receiver electrical idle detection control for lane 3
Register SRDSCR5
Description

SRDS control register 5

Reset value

0x00000000

Warm reset mask

0x00000707

Diagram
Field Mask Reset Description

SDTXL0

0x00000700

0x0

Lane 0 transmitter amplitude level

SDTXL1

0x00000007

0x0

Lane 1 transmitter amplitude level
Register SRDSCR6
Description

SRDS control register 6

Reset value

0x00000000

Warm reset mask

0x00000707

Diagram
Field Mask Reset Description

SDTXL2

0x00000700

0x0

Lane 2 transmitter amplitude level

SDTXL3

0x00000007

0x0

Lane 3 transmitter amplitude level

Commands

Name Description

delete

Dispose instance of GUTS

Limitations