P2020 PCIe Model

This section describes the P2020 PCIe controller model.

The PCI Express controller can function as either a root complex (RC) or an endpoint (EP) on the PCI Express link.

The PCI Express interface supports the following register types:

  • Memory-mapped registers-these registers control PCI Express address translation, PCI error management, PCI Express configuration register access.

  • PCI Express configuration registers contained within the PCI Express configuration space-these registers are specified by the PCI Express specification for every PCIExpress device.

PCIe Bus contains information about connected to it EP-devices and PCIe bridge (RC device). There are two configuration header types applicable to PCI Express. Type 0 headers are typically used by endpoints, Type 1 headers are used by root complexes and switches/bridges.

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import P2020

Configuration

Every RC or EP device should be connected to a bus PCIe devices array via PCIDevIface interface, buses should be connected via PCIeBusIface to PCIe model. All buses (exept the main upstream bus0) should have a pcie bridge as a parent device. Each PCIe device, including bridges, should point to the primary bus it is connected to, bridges should also point to the secondary bus immediately downstream of the bridge.

Setting PCIe buses and devices via API
// connect devices to buses
temu_connect(upstreamBus, "pcieDevices", pciebridge, "PCIDevIface");
temu_connect(downstreamBus, "pcieDevices", pciedev, "PCIDevIface");

// connect buses to the pcie model
temu_connect(pcie, "pcieBuses", upstreamBus, "PCIeBusIface");
temu_connect(pcie, "pcieBuses", downstreamBus, "PCIeBusIface");

// add upstream bridge to the bus model
temu_writeValue(downstreamBus, "parentBridge", temu_makePropObj(pciebridge), 0);

// set primary & secondary buses for devices
temu_writeValue(pciedev, "primaryBus", temu_makePropObj(downstreamBus), 0);
temu_writeValue(pciebridge, "primaryBus", temu_makePropObj(upstreamBus), 0);
temu_writeValue(pciebridge, "secondaryBus", temu_makePropObj(downstreamBus), 0);
Setting PCIe buses and devices via Command Line
# connect devices to buses
connect a=upstreamBus.pcieDevices b=pciebridge:PCIDevIface
connect a=downstreamBus.pcieDevices b=pciedev:PCIDevIface

# connect buses to the pcie model
connect a=pcie.pcieBuses b=upstreamBus:PCIeBusIface
connect a=pcie.pcieBuses b=downstreamBus:PCIeBusIface

# add upstream bridge to the bus model
downbus.parentBridge = pciebridge

# set primary & secondary buses for devices
pciedev.primaryBus = downstreamBus
pciebridge.primaryBus = upstreamBus
pciebridge.secondaryBus = downstreamBus

The PCIe programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. All the PCIe registers are 4-byte wide.

Setting registers via API
// Write Status & Command Register register from Configuration Space (device 0, bus 0, offset = 4) via CONFIG_ADDR/CONFIG_DATA registers
temu_writeValueU32(pcie, "PEX_CONFIG_ADDR", 0x80000004, 0);
temu_writeValueU32(pcie, "PEX_CONFIG_DATA", 0x02000000, 0);
// Value = 0x00000002 will be written to pcieConfigStatusCommand of the device0
Setting registers via Command Line
# Write Status & Command Register register from Configuration Space (device 0, bus 0, offset = 4) via CONFIG_ADDR/CONFIG_DATA registers
pcie.PEX_CONFIG_ADDR = 0x80000004
pcie.PEX_CONFIG_DATA = 0x02000000
# Value = 0x00000002 will be written to pcieConfigStatusCommand of the device0

@PCIe Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @PCIe

new

Create new instance of PCIe

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

PCIe Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

PEXITAR

[uint32_t; 3]

Inbound Translation Address Registers

PEXIWAR

[uint32_t; 3]

Inbound Window Attributes Registers

PEXIWBAR

[uint32_t; 3]

Inbound Window Base Address Registers

PEXIWBEAR

[uint32_t; 3]

Inbound Window Base Extended Address Registers

PEXOTAR

[uint32_t; 5]

Outbound Translation Address Registers

PEXOTEAR

[uint32_t; 5]

Outbound Translation Extended Address Registers

PEXOWAR

[uint32_t; 5]

Outbound Window Attributes Registers

PEXOWBAR

[uint32_t; 5]

Outbound Window Base Address Registers

PEX_CONFIG

uint32_t

Configuration Data Register

PEX_CONFIG_ADDR

uint32_t

Configuration Address Register

PEX_CONFIG_DATA

uint32_t

Configuration Data Register

PEX_CONF_RTY_TOR

uint32_t

Configuration Retry Timeout Register

PEX_ERR_CAP

[uint32_t; 4]

Error Capture Register

PEX_ERR_CAP_STAT

uint32_t

Error Capture Status Register

PEX_ERR_DISR

uint32_t

Error Disable Register

PEX_ERR_DR

uint32_t

Error Detect Register

PEX_ERR_EN

uint32_t

Error Interrupt Enable Register

PEX_IP_BLK_REV

[uint32_t; 2]

IP Block Revision Register

PEX_OTB_CPL_TOR

uint32_t

Outbound Completion Timeout Register

PEX_PMCR

uint32_t

Power Management Command Register

PEX_PME_MES_DISR

uint32_t

PME and Message Disable Register

PEX_PME_MES_DR

uint32_t

PME and Message Detect Register

PEX_PME_MES_IER

uint32_t

PME and Message Interrupt Enable Register

TimeSource

*void

Time source object

config.externalInterrupt

uint8_t

External interrupt (used as base by legacy PCI interrupts)

config.internalInterrupt

uint8_t

Internal interrupt

configSpace

[uint32_t; 1024]

Raw configuration space access

deviceIOAccess

temu_IfaceRef/ <unknown>

Access to the pcie’s io space from inbound windows

deviceMemAccess

temu_IfaceRef/ <unknown>

Access to the pcie’s memory space from inbound windows

extIrqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller (external interface)

ioMem

temu_IfaceRef/ <unknown>

PCIe i/o space object

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller (internal interface)

isEPMode

uint8_t

pciBridge

*void

PCIe rc bridge

pciMem

temu_IfaceRef/ <unknown>

PCIe memory space object

pcieBuses

temu_IfaceRefArray

PCI busses

processorMem

temu_IfaceRef/ <unknown>

Access to the processor’s memory space from inbound windows

Interfaces

Name Type Description

InboundAccessIface

MemAccessIface

PCIe inbound access interfaceinterface.

IrqIface

IrqCtrlIface

PCI IRQ interface

MemAccessIface

MemAccessIface

Memory access interface (registers)

OutboundMemAccessIface

MemAccessIface

PCIe outbound memory access interface.

PCIDevIface

temu::PCIDeviceIface

PCIe device interface

PCIExpressBridgeIface

temu::PCIExpressBridgeIface

PCIe bridge interface.

WindowsAccessIface

MemAccessIface

PCIe windows and configuration access interface.

Commands

Name Description

delete

Dispose instance of PCIe

inject-inbound

Send inbound transaction of 32 bit

Command inject-inbound Arguments

Name Type Required Description

addr

int

yes

Address to unmap.

value

int

yes

Value to inject.

Limitations

  • Target interface for inbound windows can be set to local memory space only, Serial Rapid IO is not implemented.