P2020 PCIe Model

This section describes the P2020 PCIe controller model.

The PCI Express controller can function as either a root complex (RC) or an endpoint (EP) on the PCI Express link.

The PCI Express interface supports the following register types:

Memory-mapped registers-these registers control PCI Express address translation, PCI error management, PCI Express configuration register access.
PCI Express configuration registers contained within the PCI Express configuration space-these registers are specified by the PCI Express specification for every PCIExpress device.

PCIe Bus contains information about connected to it EP-devices and PCIe bridge (RC device). There are two configuration header types applicable to PCI Express. Type 0 headers are typically used by endpoints, Type 1 headers are used by root complexes and switches/bridges.

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import P2020

Configuration

Every RC or EP device should be connected to a bus PCIe devices array via PCIDevIface interface, buses should be connected via PCIeBusIface to PCIe model. All buses (exept the main upstream bus0) should have a pcie bridge as a parent device. Each PCIe device, including bridges, should point to the primary bus it is connected to, bridges should also point to the secondary bus immediately downstream of the bridge.

Setting PCIe buses and devices via API

// connect devices to buses
temu_connect(upstreamBus, "pcieDevices", pciebridge, "PCIDevIface");
temu_connect(downstreamBus, "pcieDevices", pciedev, "PCIDevIface");

// connect buses to the pcie model
temu_connect(pcie, "pcieBuses", upstreamBus, "PCIeBusIface");
temu_connect(pcie, "pcieBuses", downstreamBus, "PCIeBusIface");

// add upstream bridge to the bus model
temu_writeValue(downstreamBus, "parentBridge", temu_makePropObj(pciebridge), 0);

// set primary & secondary buses for devices
temu_writeValue(pciedev, "primaryBus", temu_makePropObj(downstreamBus), 0);
temu_writeValue(pciebridge, "primaryBus", temu_makePropObj(upstreamBus), 0);
temu_writeValue(pciebridge, "secondaryBus", temu_makePropObj(downstreamBus), 0);

Setting PCIe buses and devices via Command Line

# connect devices to buses
connect a=upstreamBus.pcieDevices b=pciebridge:PCIDevIface
connect a=downstreamBus.pcieDevices b=pciedev:PCIDevIface

# connect buses to the pcie model
connect a=pcie.pcieBuses b=upstreamBus:PCIeBusIface
connect a=pcie.pcieBuses b=downstreamBus:PCIeBusIface

# add upstream bridge to the bus model
downbus.parentBridge = pciebridge

# set primary & secondary buses for devices
pciedev.primaryBus = downstreamBus
pciebridge.primaryBus = upstreamBus
pciebridge.secondaryBus = downstreamBus

The PCIe programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. All the PCIe registers are 4-byte wide.

Setting registers via API

// Write Status & Command Register register from Configuration Space (device 0, bus 0, offset = 4) via CONFIG_ADDR/CONFIG_DATA registers
temu_writeValueU32(pcie, "PEX_CONFIG_ADDR", 0x80000004, 0);
temu_writeValueU32(pcie, "PEX_CONFIG_DATA", 0x02000000, 0);
// Value = 0x00000002 will be written to pcieConfigStatusCommand of the device0

Setting registers via Command Line

# Write Status & Command Register register from Configuration Space (device 0, bus 0, offset = 4) via CONFIG_ADDR/CONFIG_DATA registers
pcie.PEX_CONFIG_ADDR = 0x80000004
pcie.PEX_CONFIG_DATA = 0x02000000
# Value = 0x00000002 will be written to pcieConfigStatusCommand of the device0

@PCIe Reference

Properties

Name	Type	Description
Class	*void	Class object
Component	*void	Pointer to component object if part of component
LocalName	*char	Local name (in component, if applicable)
LogMessageFlags	uint64_t	Per-object log message suppression flags
LoggingFlags	uint64_t	Flags for logging info
Name	*char	Object name
ObjectID	uint64_t	Unique ObjectID.
ReplayLoggingFlags	uint64_t	Replay-time category logging flags
TimeSource	*void	Time source object

Name

Type

Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name	Description
delete	Dispose instance of @PCIe
new	Create new instance of PCIe

Name

Description

delete

Dispose instance of @PCIe

new

Create new instance of PCIe

Command new Arguments

Name	Type	Required	Description
name	string	yes	Name of object to create

Name

Type

Required

Description

name

string

yes

Name of object to create

PCIe Reference

Properties

Name	Type	Description
Class	*void	Class object
Component	*void	Pointer to component object if part of component
LocalName	*char	Local name (in component, if applicable)
LogMessageFlags	uint64_t	Per-object log message suppression flags
LoggingFlags	uint64_t	Flags for logging info
Name	*char	Object name
ObjectID	uint64_t	Unique ObjectID.
PEXITAR	[uint32_t; 3]	PCI Express inbound translation address register
PEXIWAR	[uint32_t; 3]	PCI Express inbound window attributes register
PEXIWBAR	[uint32_t; 3]	PCI Express inbound window base address register
PEXIWBEAR	[uint32_t; 3]	PCI Express inbound window base extended address register
PEXOTAR	[uint32_t; 5]	PCI Express outbound translation address register
PEXOTEAR	[uint32_t; 5]	PCI Express outbound translation extended address register
PEXOWAR	[uint32_t; 5]	PCI Express outbound window attributes register
PEXOWBAR	[uint32_t; 5]	PCI Express outbound window base address register
PEX_CONFIG	uint32_t	PCI Express configuration register
PEX_CONFIGColdResetValue	uint32_t	PCI Express configuration register
PEX_CONFIGForcedBits	uint32_t	PCI Express configuration register
PEX_CONFIGForcedFlippedBits	uint32_t	PCI Express configuration register
PEX_CONFIGReadMask	uint32_t	PCI Express configuration register
PEX_CONFIGResetMask	uint32_t	PCI Express configuration register
PEX_CONFIGResetValue	uint32_t	PCI Express configuration register
PEX_CONFIGWriteMask	uint32_t	PCI Express configuration register
PEX_CONFIG_ADDR	uint32_t	PCI Express configuration address register
PEX_CONFIG_ADDRColdResetValue	uint32_t	PCI Express configuration address register
PEX_CONFIG_ADDRForcedBits	uint32_t	PCI Express configuration address register
PEX_CONFIG_ADDRForcedFlippedBits	uint32_t	PCI Express configuration address register
PEX_CONFIG_ADDRReadMask	uint32_t	PCI Express configuration address register
PEX_CONFIG_ADDRResetMask	uint32_t	PCI Express configuration address register
PEX_CONFIG_ADDRResetValue	uint32_t	PCI Express configuration address register
PEX_CONFIG_ADDRWriteMask	uint32_t	PCI Express configuration address register
PEX_CONFIG_DATA	uint32_t	PCI Express configuration data register
PEX_CONFIG_DATAColdResetValue	uint32_t	PCI Express configuration data register
PEX_CONFIG_DATAForcedBits	uint32_t	PCI Express configuration data register
PEX_CONFIG_DATAForcedFlippedBits	uint32_t	PCI Express configuration data register
PEX_CONFIG_DATAReadMask	uint32_t	PCI Express configuration data register
PEX_CONFIG_DATAResetMask	uint32_t	PCI Express configuration data register
PEX_CONFIG_DATAResetValue	uint32_t	PCI Express configuration data register
PEX_CONFIG_DATAWriteMask	uint32_t	PCI Express configuration data register
PEX_CONF_RTY_TOR	uint32_t	PCI Express configuration retry timeout register
PEX_CONF_RTY_TORColdResetValue	uint32_t	PCI Express configuration retry timeout register
PEX_CONF_RTY_TORForcedBits	uint32_t	PCI Express configuration retry timeout register
PEX_CONF_RTY_TORForcedFlippedBits	uint32_t	PCI Express configuration retry timeout register
PEX_CONF_RTY_TORReadMask	uint32_t	PCI Express configuration retry timeout register
PEX_CONF_RTY_TORResetMask	uint32_t	PCI Express configuration retry timeout register
PEX_CONF_RTY_TORResetValue	uint32_t	PCI Express configuration retry timeout register
PEX_CONF_RTY_TORWriteMask	uint32_t	PCI Express configuration retry timeout register
PEX_ERR_CAP	[uint32_t; 4]	PCI Express error capture register
PEX_ERR_CAP_STAT	uint32_t	PCI Express error capture status register
PEX_ERR_CAP_STATColdResetValue	uint32_t	PCI Express error capture status register
PEX_ERR_CAP_STATForcedBits	uint32_t	PCI Express error capture status register
PEX_ERR_CAP_STATForcedFlippedBits	uint32_t	PCI Express error capture status register
PEX_ERR_CAP_STATReadMask	uint32_t	PCI Express error capture status register
PEX_ERR_CAP_STATResetMask	uint32_t	PCI Express error capture status register
PEX_ERR_CAP_STATResetValue	uint32_t	PCI Express error capture status register
PEX_ERR_CAP_STATWriteMask	uint32_t	PCI Express error capture status register
PEX_ERR_DISR	uint32_t	PCI Express error disable register
PEX_ERR_DISRColdResetValue	uint32_t	PCI Express error disable register
PEX_ERR_DISRForcedBits	uint32_t	PCI Express error disable register
PEX_ERR_DISRForcedFlippedBits	uint32_t	PCI Express error disable register
PEX_ERR_DISRReadMask	uint32_t	PCI Express error disable register
PEX_ERR_DISRResetMask	uint32_t	PCI Express error disable register
PEX_ERR_DISRResetValue	uint32_t	PCI Express error disable register
PEX_ERR_DISRWriteMask	uint32_t	PCI Express error disable register
PEX_ERR_DR	uint32_t	PCI Express error detect register
PEX_ERR_DRColdResetValue	uint32_t	PCI Express error detect register
PEX_ERR_DRForcedBits	uint32_t	PCI Express error detect register
PEX_ERR_DRForcedFlippedBits	uint32_t	PCI Express error detect register
PEX_ERR_DRReadMask	uint32_t	PCI Express error detect register
PEX_ERR_DRResetMask	uint32_t	PCI Express error detect register
PEX_ERR_DRResetValue	uint32_t	PCI Express error detect register
PEX_ERR_DRWriteMask	uint32_t	PCI Express error detect register
PEX_ERR_EN	uint32_t	PCI Express error interrupt enable register
PEX_ERR_ENColdResetValue	uint32_t	PCI Express error interrupt enable register
PEX_ERR_ENForcedBits	uint32_t	PCI Express error interrupt enable register
PEX_ERR_ENForcedFlippedBits	uint32_t	PCI Express error interrupt enable register
PEX_ERR_ENReadMask	uint32_t	PCI Express error interrupt enable register
PEX_ERR_ENResetMask	uint32_t	PCI Express error interrupt enable register
PEX_ERR_ENResetValue	uint32_t	PCI Express error interrupt enable register
PEX_ERR_ENWriteMask	uint32_t	PCI Express error interrupt enable register
PEX_IP_BLK_REV	[uint32_t; 2]	IP block revision register 1
PEX_OTB_CPL_TOR	uint32_t	PCI Express outbound completion timeout register
PEX_OTB_CPL_TORColdResetValue	uint32_t	PCI Express outbound completion timeout register
PEX_OTB_CPL_TORForcedBits	uint32_t	PCI Express outbound completion timeout register
PEX_OTB_CPL_TORForcedFlippedBits	uint32_t	PCI Express outbound completion timeout register
PEX_OTB_CPL_TORReadMask	uint32_t	PCI Express outbound completion timeout register
PEX_OTB_CPL_TORResetMask	uint32_t	PCI Express outbound completion timeout register
PEX_OTB_CPL_TORResetValue	uint32_t	PCI Express outbound completion timeout register
PEX_OTB_CPL_TORWriteMask	uint32_t	PCI Express outbound completion timeout register
PEX_PMCR	uint32_t	PCI Express power management command register
PEX_PMCRColdResetValue	uint32_t	PCI Express power management command register
PEX_PMCRForcedBits	uint32_t	PCI Express power management command register
PEX_PMCRForcedFlippedBits	uint32_t	PCI Express power management command register
PEX_PMCRReadMask	uint32_t	PCI Express power management command register
PEX_PMCRResetMask	uint32_t	PCI Express power management command register
PEX_PMCRResetValue	uint32_t	PCI Express power management command register
PEX_PMCRWriteMask	uint32_t	PCI Express power management command register
PEX_PME_MES_DISR	uint32_t	PCI Express PME and message disable register
PEX_PME_MES_DISRColdResetValue	uint32_t	PCI Express PME and message disable register
PEX_PME_MES_DISRForcedBits	uint32_t	PCI Express PME and message disable register
PEX_PME_MES_DISRForcedFlippedBits	uint32_t	PCI Express PME and message disable register
PEX_PME_MES_DISRReadMask	uint32_t	PCI Express PME and message disable register
PEX_PME_MES_DISRResetMask	uint32_t	PCI Express PME and message disable register
PEX_PME_MES_DISRResetValue	uint32_t	PCI Express PME and message disable register
PEX_PME_MES_DISRWriteMask	uint32_t	PCI Express PME and message disable register
PEX_PME_MES_DR	uint32_t	PCI Express PME and message detect register
PEX_PME_MES_DRColdResetValue	uint32_t	PCI Express PME and message detect register
PEX_PME_MES_DRForcedBits	uint32_t	PCI Express PME and message detect register
PEX_PME_MES_DRForcedFlippedBits	uint32_t	PCI Express PME and message detect register
PEX_PME_MES_DRReadMask	uint32_t	PCI Express PME and message detect register
PEX_PME_MES_DRResetMask	uint32_t	PCI Express PME and message detect register
PEX_PME_MES_DRResetValue	uint32_t	PCI Express PME and message detect register
PEX_PME_MES_DRWriteMask	uint32_t	PCI Express PME and message detect register
PEX_PME_MES_IER	uint32_t	PCI Express PME and message interrupt enable register
PEX_PME_MES_IERColdResetValue	uint32_t	PCI Express PME and message interrupt enable register
PEX_PME_MES_IERForcedBits	uint32_t	PCI Express PME and message interrupt enable register
PEX_PME_MES_IERForcedFlippedBits	uint32_t	PCI Express PME and message interrupt enable register
PEX_PME_MES_IERReadMask	uint32_t	PCI Express PME and message interrupt enable register
PEX_PME_MES_IERResetMask	uint32_t	PCI Express PME and message interrupt enable register
PEX_PME_MES_IERResetValue	uint32_t	PCI Express PME and message interrupt enable register
PEX_PME_MES_IERWriteMask	uint32_t	PCI Express PME and message interrupt enable register
ReplayLoggingFlags	uint64_t	Replay-time category logging flags
TimeSource	*void	Time source object
config.externalInterrupt	uint8_t	External interrupt (used as base by legacy PCI interrupts)
config.internalInterrupt	uint8_t	Internal interrupt
configSpace	[uint32_t; 1024]	Raw configuration space access
deviceIOAccess	temu_IfaceRef/ <unknown>	Access to the pcie’s io space from inbound windows
deviceMemAccess	temu_IfaceRef/ <unknown>	Access to the pcie’s memory space from inbound windows
extIrqCtrl	temu_IfaceRef/ <unknown>	Interrupt controller (external interface)
ioMem	temu_IfaceRef/ <unknown>	PCIe i/o space object
irqCtrl	temu_IfaceRef/ <unknown>	Interrupt controller (internal interface)
isEPMode	uint8_t
pciBridge	*void	PCIe rc bridge
pciMem	temu_IfaceRef/ <unknown>	PCIe memory space object
pcieBuses	temu_IfaceRefArray	PCI busses
processorMem	temu_IfaceRef/ <unknown>	Access to the processor’s memory space from inbound windows

Name

Type

Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

PEXITAR

[uint32_t; 3]

PCI Express inbound translation address register

PEXIWAR

[uint32_t; 3]

PCI Express inbound window attributes register

PEXIWBAR

[uint32_t; 3]

PCI Express inbound window base address register

PEXIWBEAR

[uint32_t; 3]

PCI Express inbound window base extended address register

PEXOTAR

[uint32_t; 5]

PCI Express outbound translation address register

PEXOTEAR

[uint32_t; 5]

PCI Express outbound translation extended address register

PEXOWAR

[uint32_t; 5]

PCI Express outbound window attributes register

PEXOWBAR

[uint32_t; 5]

PCI Express outbound window base address register

PEX_CONFIG

uint32_t

PCI Express configuration register

PEX_CONFIGColdResetValue

uint32_t

PCI Express configuration register

PEX_CONFIGForcedBits

uint32_t

PCI Express configuration register

PEX_CONFIGForcedFlippedBits

uint32_t

PCI Express configuration register

PEX_CONFIGReadMask

uint32_t

PCI Express configuration register

PEX_CONFIGResetMask

uint32_t

PCI Express configuration register

PEX_CONFIGResetValue

uint32_t

PCI Express configuration register

PEX_CONFIGWriteMask

uint32_t

PCI Express configuration register

PEX_CONFIG_ADDR

uint32_t

PCI Express configuration address register

PEX_CONFIG_ADDRColdResetValue

uint32_t

PCI Express configuration address register

PEX_CONFIG_ADDRForcedBits

uint32_t

PCI Express configuration address register

PEX_CONFIG_ADDRForcedFlippedBits

uint32_t

PCI Express configuration address register

PEX_CONFIG_ADDRReadMask

uint32_t

PCI Express configuration address register

PEX_CONFIG_ADDRResetMask

uint32_t

PCI Express configuration address register

PEX_CONFIG_ADDRResetValue

uint32_t

PCI Express configuration address register

PEX_CONFIG_ADDRWriteMask

uint32_t

PCI Express configuration address register

PEX_CONFIG_DATA

uint32_t

PCI Express configuration data register

PEX_CONFIG_DATAColdResetValue

uint32_t

PCI Express configuration data register

PEX_CONFIG_DATAForcedBits

uint32_t

PCI Express configuration data register

PEX_CONFIG_DATAForcedFlippedBits

uint32_t

PCI Express configuration data register

PEX_CONFIG_DATAReadMask

uint32_t

PCI Express configuration data register

PEX_CONFIG_DATAResetMask

uint32_t

PCI Express configuration data register

PEX_CONFIG_DATAResetValue

uint32_t

PCI Express configuration data register

PEX_CONFIG_DATAWriteMask

uint32_t

PCI Express configuration data register

PEX_CONF_RTY_TOR

uint32_t