P2020 DUART Model
This section describes the P2020 serial port (DUART) model. The DUART model supports both FIFO simualtion and infinite speed UARTs. In infinite speed mode bytes are sent directly when they are written to the data register. FIFO mode for both transmitter and receiver provides 16-byte FIFOs.
Configuration
- config.infiniteUartSpeed
-
Enable/disable immediate UART.
- config.fifoSize
-
maximum UART FIFO size.
- config.clockDivider
-
Clock devider (default 1).
To receive transmitted data from DUART device can be connected via the serial interface it implements:
# Connect DUART transmitter to device model
connect a=duart.tx b=mydevice:SerialIface
// Connect DUART transmitter to device model
temu_connect(duart, "tx", mydevice, "SerialIface");
The DUART programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. All the DUART registers are one-byte wide.
To enables the transmitter and receiver FIFOs you need to set FIFO Control Register value as follows:
duart.UFCR = 0x01;
temu_writeValueU8(duart, "UFCR", 0x01, 0);
@DUART Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
DUART Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
UAFR |
uint8_t |
Alternate function register |
UAFRColdResetValue |
uint8_t |
Alternate function register |
UAFRForcedBits |
uint8_t |
Alternate function register |
UAFRForcedFlippedBits |
uint8_t |
Alternate function register |
UAFRReadMask |
uint8_t |
Alternate function register |
UAFRResetMask |
uint8_t |
Alternate function register |
UAFRResetValue |
uint8_t |
Alternate function register |
UAFRWriteMask |
uint8_t |
Alternate function register |
UDLB |
uint8_t |
Divisor least significant byte register |
UDLBColdResetValue |
uint8_t |
Divisor least significant byte register |
UDLBForcedBits |
uint8_t |
Divisor least significant byte register |
UDLBForcedFlippedBits |
uint8_t |
Divisor least significant byte register |
UDLBReadMask |
uint8_t |
Divisor least significant byte register |
UDLBResetMask |
uint8_t |
Divisor least significant byte register |
UDLBResetValue |
uint8_t |
Divisor least significant byte register |
UDLBWriteMask |
uint8_t |
Divisor least significant byte register |
UDMB |
uint8_t |
Divisor most significant byte register |
UDMBColdResetValue |
uint8_t |
Divisor most significant byte register |
UDMBForcedBits |
uint8_t |
Divisor most significant byte register |
UDMBForcedFlippedBits |
uint8_t |
Divisor most significant byte register |
UDMBReadMask |
uint8_t |
Divisor most significant byte register |
UDMBResetMask |
uint8_t |
Divisor most significant byte register |
UDMBResetValue |
uint8_t |
Divisor most significant byte register |
UDMBWriteMask |
uint8_t |
Divisor most significant byte register |
UDSR |
uint8_t |
DMA status register |
UDSRColdResetValue |
uint8_t |
DMA status register |
UDSRForcedBits |
uint8_t |
DMA status register |
UDSRForcedFlippedBits |
uint8_t |
DMA status register |
UDSRReadMask |
uint8_t |
DMA status register |
UDSRResetMask |
uint8_t |
DMA status register |
UDSRResetValue |
uint8_t |
DMA status register |
UDSRWriteMask |
uint8_t |
DMA status register |
UFCR |
uint8_t |
FIFO control register |
UFCRColdResetValue |
uint8_t |
FIFO control register |
UFCRForcedBits |
uint8_t |
FIFO control register |
UFCRForcedFlippedBits |
uint8_t |
FIFO control register |
UFCRReadMask |
uint8_t |
FIFO control register |
UFCRResetMask |
uint8_t |
FIFO control register |
UFCRResetValue |
uint8_t |
FIFO control register |
UFCRWriteMask |
uint8_t |
FIFO control register |
UIER |
uint8_t |
Interrupt enable register |
UIERColdResetValue |
uint8_t |
Interrupt enable register |
UIERForcedBits |
uint8_t |
Interrupt enable register |
UIERForcedFlippedBits |
uint8_t |
Interrupt enable register |
UIERReadMask |
uint8_t |
Interrupt enable register |
UIERResetMask |
uint8_t |
Interrupt enable register |
UIERResetValue |
uint8_t |
Interrupt enable register |
UIERWriteMask |
uint8_t |
Interrupt enable register |
UIIR |
uint8_t |
Interrupt ID register |
UIIRColdResetValue |
uint8_t |
Interrupt ID register |
UIIRForcedBits |
uint8_t |
Interrupt ID register |
UIIRForcedFlippedBits |
uint8_t |
Interrupt ID register |
UIIRReadMask |
uint8_t |
Interrupt ID register |
UIIRResetMask |
uint8_t |
Interrupt ID register |
UIIRResetValue |
uint8_t |
Interrupt ID register |
UIIRWriteMask |
uint8_t |
Interrupt ID register |
ULCR |
uint8_t |
Line control register |
ULCRColdResetValue |
uint8_t |
Line control register |
ULCRForcedBits |
uint8_t |
Line control register |
ULCRForcedFlippedBits |
uint8_t |
Line control register |
ULCRReadMask |
uint8_t |
Line control register |
ULCRResetMask |
uint8_t |
Line control register |
ULCRResetValue |
uint8_t |
Line control register |
ULCRWriteMask |
uint8_t |
Line control register |
ULSR |
uint8_t |
Line status register |
ULSRColdResetValue |
uint8_t |
Line status register |
ULSRForcedBits |
uint8_t |
Line status register |
ULSRForcedFlippedBits |
uint8_t |
Line status register |
ULSRReadMask |
uint8_t |
Line status register |
ULSRResetMask |
uint8_t |
Line status register |
ULSRResetValue |
uint8_t |
Line status register |
ULSRWriteMask |
uint8_t |
Line status register |
UMCR |
uint8_t |
Modem control register |
UMCRColdResetValue |
uint8_t |
Modem control register |
UMCRForcedBits |
uint8_t |
Modem control register |
UMCRForcedFlippedBits |
uint8_t |
Modem control register |
UMCRReadMask |
uint8_t |
Modem control register |
UMCRResetMask |
uint8_t |
Modem control register |
UMCRResetValue |
uint8_t |
Modem control register |
UMCRWriteMask |
uint8_t |
Modem control register |
UMSR |
uint8_t |
Modem status register |
UMSRColdResetValue |
uint8_t |
Modem status register |
UMSRForcedBits |
uint8_t |
Modem status register |
UMSRForcedFlippedBits |
uint8_t |
Modem status register |
UMSRReadMask |
uint8_t |
Modem status register |
UMSRResetMask |
uint8_t |
Modem status register |
UMSRResetValue |
uint8_t |
Modem status register |
UMSRWriteMask |
uint8_t |
Modem status register |
URBR |
uint8_t |
Receiver buffer register |
URBRColdResetValue |
uint8_t |
Receiver buffer register |
URBRForcedBits |
uint8_t |
Receiver buffer register |
URBRForcedFlippedBits |
uint8_t |
Receiver buffer register |
URBRReadMask |
uint8_t |
Receiver buffer register |
URBRResetMask |
uint8_t |
Receiver buffer register |
URBRResetValue |
uint8_t |
Receiver buffer register |
URBRWriteMask |
uint8_t |
Receiver buffer register |
USCR |
uint8_t |
Scratch register |
USCRColdResetValue |
uint8_t |
Scratch register |
USCRForcedBits |
uint8_t |
Scratch register |
USCRForcedFlippedBits |
uint8_t |
Scratch register |
USCRReadMask |
uint8_t |
Scratch register |
USCRResetMask |
uint8_t |
Scratch register |
USCRResetValue |
uint8_t |
Scratch register |
USCRWriteMask |
uint8_t |
Scratch register |
UTHR |
uint8_t |
Transmitter holding register |
UTHRColdResetValue |
uint8_t |
Transmitter holding register |
UTHRForcedBits |
uint8_t |
Transmitter holding register |
UTHRForcedFlippedBits |
uint8_t |
Transmitter holding register |
UTHRReadMask |
uint8_t |
Transmitter holding register |
UTHRResetMask |
uint8_t |
Transmitter holding register |
UTHRResetValue |
uint8_t |
Transmitter holding register |
UTHRWriteMask |
uint8_t |
Transmitter holding register |
config.clockDivider |
uint32_t |
Clock divider |
config.fifoSize |
uint8_t |
UART FIFO size |
config.infiniteUartSpeed |
uint8_t |
Set to 1 to enable immediate UARTs |
config.interrupt |
uint8_t |
Interrupt number |
dataArrivedSinceLastRead |
uint8_t |
Set to 1 if data has arrived on the serial port since the last read. |
irqCtrl |
temu_IfaceRef/ <unknown> |
Interrupt controller |
rxFifo.data |
[uint8_t; 32] |
RX FIFO data |
rxFifo.size |
uint8_t |
RX size |
rxFifo.start |
uint8_t |
RX start index |
rxFifo.usage |
uint8_t |
RX usage |
rxTriggerLevel |
uint8_t |
Internal state (rx trigger level). |
tx |
temu_IfaceRef/ <unknown> |
Transmit target |
txFifo.data |
[uint8_t; 32] |
TX FIFO data |
txFifo.size |
uint8_t |
TX size |
txFifo.start |
uint8_t |
TX start index |
txFifo.usage |
uint8_t |
TX usage |
txShift |
uint8_t |
UART shift register |