GRLIB CAN_OC Model
The CAN_OC device is part of the OpenCores and the GRLIB IP libraries.
It is available in libTEMUOpenCores.so
.
Configuration
There are two configuration parameters in the CAN device.
Firstly the config.interrupt
property can be set
to influence the interrupt that is raised with the IRQ controller.
Setting that property also updates the AHB PnP info.
The second configuration property is config.infiniteSpeed
.
If that property is set, messages will be sent immediately instead of being scheduled.
The device should be connected to an interrupt controller and a CAN bus, to work properly.
@CAN_OC Reference
CAN_OC Reference
Properties
Name | Type | Description |
---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
TimeSource |
*void |
Time source object |
basiccan.acceptCode |
uint8_t |
Accept Code register for BasicCAN mode. |
basiccan.acceptMask |
uint8_t |
Accept Mask register for BasicCAN mode. |
basiccan.ctrl |
uint8_t |
Control register for BasicCAN mode. |
basiccan.txID |
[uint8_t; 2] |
TxID registers for BasicCAN mode. |
bus |
temu_IfaceRef/ <unknown> |
CAN bus the device is connected to. |
busTiming |
[uint8_t; 2] |
Bus Timing registers. |
clockDivider |
uint8_t |
Clock Divider register. |
command |
uint8_t |
Command register. |
config.infiniteSpeed |
uint8_t |
Enable infinite speed mode (no delays when sending messages). |
config.interrupt |
uint8_t |
External interrupt raised with IRQ controller. |
fifo.data |
[uint8_t; 64] |
RX FIFO data buffer. |
fifo.start |
uint32_t |
RX FIFO buffer start location. |
fifo.usage |
uint32_t |
RX FIFO buffer usage. |
interrupt |
uint8_t |
Interrupt register. |
irqCtrl |
temu_IfaceRef/ <unknown> |
Interrupt controller. |
pelican.acceptCode |
[uint8_t; 4] |
Accept Code registers for PeliCAN mode. |
pelican.acceptMask |
[uint8_t; 4] |
Accept Mask registers for PeliCAN mode. |
pelican.arbLostCaputure |
uint8_t |
Arbitration Lost Capture register for PeliCAN mode. |
pelican.errCodeCapture |
uint8_t |
Error Code Capture register for PeliCAN mode. |
pelican.errWarnLimit |
uint8_t |
Error Warning Limit register for PeliCAN mode. |
pelican.interruptEnable |
uint8_t |
Interrupt Enable register for PeliCAN mode. |
pelican.mode |
uint8_t |
Mode register for PeliCAN mode. |
pelican.rxErrCounter |
uint8_t |
RX Error Counter register for PeliCAN mode. |
pelican.rxMsgCounter |
uint8_t |
RX Message Counter register for PeliCAN mode. |
pelican.txErrCounter |
uint8_t |
TX Error Counter register for PeliCAN mode. |
pelican.txFI |
uint8_t |
TX Frame Info register for PeliCAN mode. |
pelican.txID |
[uint8_t; 4] |
TxID registers for PeliCAN mode. |
status |
uint8_t |
Status register. |
txData |
[uint8_t; 8] |
TX data buffer (excluding TX FI and TX ID registers). |
Interfaces
Name | Type | Description |
---|---|---|
AhbIface |
AhbIface |
AHB interface |
CanDevIface |
CanDevIface |
CAN device interface. |
DeviceIface |
DeviceIface |
Device interface. |
MemAccessIface |
MemAccessIface |
Memory access interface for memory mapped registers. |
ResetIface |
ResetIface |
Registers
Register support is currently experimental! |
Register Bank BasicCAN
Register basiccan.acceptCode
- Description
-
Accept Code register for BasicCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register basiccan.acceptMask
- Description
-
Accept Mask register for BasicCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register Bank PeliCAN
Register pelican.acceptCode
- Description
-
Accept Code registers for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.acceptMask
- Description
-
Accept Mask registers for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.arbLostCaputure
- Description
-
Arbitration Lost Capture register for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.errCodeCapture
- Description
-
Error Code Capture register for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.errWarnLimit
- Description
-
Error Warning Limit register for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.interruptEnable
- Description
-
Interrupt Enable register for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.mode
- Description
-
Mode register for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.rxErrCounter
- Description
-
RX Error Counter register for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.rxMsgCounter
- Description
-
RX Message Counter register for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register pelican.txErrCounter
- Description
-
TX Error Counter register for PeliCAN mode.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register Bank default
Register busTiming
- Description
-
Bus Timing registers.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register clockDivider
- Description
-
Clock Divider register.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register command
- Description
-
Command register.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Register interrupt
- Description
-
Interrupt register.
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
Field | Mask | Reset | Description |
---|---|---|---|
- |
- |
- |
- |
Limitations
The following deviations from real hardware are known to exist with this model:
-
The controller clears the RX and TX buffers on reset. This is not the proper behavior and may have an impact on FDIR. Let us know if this is an issue.
-
There is no arbitration of messages in the simulated world and busses are not synchronised.
-
The model does at present not register filters with the CAN bus model.
-
The model currently ignores the error field in the CAN frame objects.
-
The model currently assumes the CAN bus is running at 1 Mb/s (this assumption is in non-infinite speed mode). This is arguably incorrect and the timing should be picked from the bus timing register Contact Terma if this is this is critical for your needs.