GRLIB CAN_OC Model

The CAN_OC device is part of the OpenCores and the GRLIB IP libraries. It is available in libTEMUOpenCores.so.

Loading the Plugin

import OpenCores

Configuration

There are two configuration parameters in the CAN device. Firstly the config.interrupt property can be set to influence the interrupt that is raised with the IRQ controller. Setting that property also updates the AHB PnP info.

The second configuration property is config.infiniteSpeed. If that property is set, messages will be sent immediately instead of being scheduled.

The device should be connected to an interrupt controller and a CAN bus, to work properly.

@CAN_OC Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @CAN_OC

new

Create new instance of CAN_OC

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

CAN_OC Reference

Properties

Name Type Description

BASIC_ACCEPT_CODEColdResetValue

uint8_t

Accept code register for BasicCAN mode

BASIC_ACCEPT_CODEForcedBits

uint8_t

Accept code register for BasicCAN mode

BASIC_ACCEPT_CODEForcedFlippedBits

uint8_t

Accept code register for BasicCAN mode

BASIC_ACCEPT_CODEReadMask

uint8_t

Accept code register for BasicCAN mode

BASIC_ACCEPT_CODEResetMask

uint8_t

Accept code register for BasicCAN mode

BASIC_ACCEPT_CODEResetValue

uint8_t

Accept code register for BasicCAN mode

BASIC_ACCEPT_CODEWriteMask

uint8_t

Accept code register for BasicCAN mode

BASIC_ACCEPT_MASKColdResetValue

uint8_t

Accept mask register for BasicCAN mode

BASIC_ACCEPT_MASKForcedBits

uint8_t

Accept mask register for BasicCAN mode

BASIC_ACCEPT_MASKForcedFlippedBits

uint8_t

Accept mask register for BasicCAN mode

BASIC_ACCEPT_MASKReadMask

uint8_t

Accept mask register for BasicCAN mode

BASIC_ACCEPT_MASKResetMask

uint8_t

Accept mask register for BasicCAN mode

BASIC_ACCEPT_MASKResetValue

uint8_t

Accept mask register for BasicCAN mode

BASIC_ACCEPT_MASKWriteMask

uint8_t

Accept mask register for BasicCAN mode

BASIC_CONTROLColdResetValue

uint8_t

Control register for BasicCAN mode

BASIC_CONTROLForcedBits

uint8_t

Control register for BasicCAN mode

BASIC_CONTROLForcedFlippedBits

uint8_t

Control register for BasicCAN mode

BASIC_CONTROLReadMask

uint8_t

Control register for BasicCAN mode

BASIC_CONTROLResetMask

uint8_t

Control register for BasicCAN mode

BASIC_CONTROLResetValue

uint8_t

Control register for BasicCAN mode

BASIC_CONTROLWriteMask

uint8_t

Control register for BasicCAN mode

CLOCKDIVIDERColdResetValue

uint8_t

Clock divider register

CLOCKDIVIDERForcedBits

uint8_t

Clock divider register

CLOCKDIVIDERForcedFlippedBits

uint8_t

Clock divider register

CLOCKDIVIDERReadMask

uint8_t

Clock divider register

CLOCKDIVIDERResetMask

uint8_t

Clock divider register

CLOCKDIVIDERResetValue

uint8_t

Clock divider register

CLOCKDIVIDERWriteMask

uint8_t

Clock divider register

COMMANDColdResetValue

uint8_t

Command register

COMMANDForcedBits

uint8_t

Command register

COMMANDForcedFlippedBits

uint8_t

Command register

COMMANDReadMask

uint8_t

Command register

COMMANDResetMask

uint8_t

Command register

COMMANDResetValue

uint8_t

Command register

COMMANDWriteMask

uint8_t

Command register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

INTERRUPTColdResetValue

uint8_t

Interrupt register

INTERRUPTForcedBits

uint8_t

Interrupt register

INTERRUPTForcedFlippedBits

uint8_t

Interrupt register

INTERRUPTReadMask

uint8_t

Interrupt register

INTERRUPTResetMask

uint8_t

Interrupt register

INTERRUPTResetValue

uint8_t

Interrupt register

INTERRUPTWriteMask

uint8_t

Interrupt register

LocalName

*char

Local name (in component, if applicable)

LogMessageFlags

uint64_t

Per-object log message suppression flags

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

ObjectID

uint64_t

Unique ObjectID.

PELICAN_ARB_LOST_CAPTUREColdResetValue

uint8_t

Arbitration lost capture register

PELICAN_ARB_LOST_CAPTUREForcedBits

uint8_t

Arbitration lost capture register

PELICAN_ARB_LOST_CAPTUREForcedFlippedBits

uint8_t

Arbitration lost capture register

PELICAN_ARB_LOST_CAPTUREReadMask

uint8_t

Arbitration lost capture register

PELICAN_ARB_LOST_CAPTUREResetMask

uint8_t

Arbitration lost capture register

PELICAN_ARB_LOST_CAPTUREResetValue

uint8_t

Arbitration lost capture register

PELICAN_ARB_LOST_CAPTUREWriteMask

uint8_t

Arbitration lost capture register

PELICAN_ERR_CODE_CAPTUREColdResetValue

uint8_t

Error code capture register

PELICAN_ERR_CODE_CAPTUREForcedBits

uint8_t

Error code capture register

PELICAN_ERR_CODE_CAPTUREForcedFlippedBits

uint8_t

Error code capture register

PELICAN_ERR_CODE_CAPTUREReadMask

uint8_t

Error code capture register

PELICAN_ERR_CODE_CAPTUREResetMask

uint8_t

Error code capture register

PELICAN_ERR_CODE_CAPTUREResetValue

uint8_t

Error code capture register

PELICAN_ERR_CODE_CAPTUREWriteMask

uint8_t

Error code capture register

PELICAN_ERR_WARN_LIMITColdResetValue

uint8_t

Error warning limit register

PELICAN_ERR_WARN_LIMITForcedBits

uint8_t

Error warning limit register

PELICAN_ERR_WARN_LIMITForcedFlippedBits

uint8_t

Error warning limit register

PELICAN_ERR_WARN_LIMITReadMask

uint8_t

Error warning limit register

PELICAN_ERR_WARN_LIMITResetMask

uint8_t

Error warning limit register

PELICAN_ERR_WARN_LIMITResetValue

uint8_t

Error warning limit register

PELICAN_ERR_WARN_LIMITWriteMask

uint8_t

Error warning limit register

PELICAN_INTERRUPT_ENABLEColdResetValue

uint8_t

Interrupt enable register for PeliCAN mode

PELICAN_INTERRUPT_ENABLEForcedBits

uint8_t

Interrupt enable register for PeliCAN mode

PELICAN_INTERRUPT_ENABLEForcedFlippedBits

uint8_t

Interrupt enable register for PeliCAN mode

PELICAN_INTERRUPT_ENABLEReadMask

uint8_t

Interrupt enable register for PeliCAN mode

PELICAN_INTERRUPT_ENABLEResetMask

uint8_t

Interrupt enable register for PeliCAN mode

PELICAN_INTERRUPT_ENABLEResetValue

uint8_t

Interrupt enable register for PeliCAN mode

PELICAN_INTERRUPT_ENABLEWriteMask

uint8_t

Interrupt enable register for PeliCAN mode

PELICAN_MODEColdResetValue

uint8_t

Mode register for PeliCAN mode

PELICAN_MODEForcedBits

uint8_t

Mode register for PeliCAN mode

PELICAN_MODEForcedFlippedBits

uint8_t

Mode register for PeliCAN mode

PELICAN_MODEReadMask

uint8_t

Mode register for PeliCAN mode

PELICAN_MODEResetMask

uint8_t

Mode register for PeliCAN mode

PELICAN_MODEResetValue

uint8_t

Mode register for PeliCAN mode

PELICAN_MODEWriteMask

uint8_t

Mode register for PeliCAN mode

PELICAN_RX_ERR_COUNTERColdResetValue

uint8_t

RX error counter register

PELICAN_RX_ERR_COUNTERForcedBits

uint8_t

RX error counter register

PELICAN_RX_ERR_COUNTERForcedFlippedBits

uint8_t

RX error counter register

PELICAN_RX_ERR_COUNTERReadMask

uint8_t

RX error counter register

PELICAN_RX_ERR_COUNTERResetMask

uint8_t

RX error counter register

PELICAN_RX_ERR_COUNTERResetValue

uint8_t

RX error counter register

PELICAN_RX_ERR_COUNTERWriteMask

uint8_t

RX error counter register

PELICAN_RX_MSG_COUNTERColdResetValue

uint8_t

RX message counter register

PELICAN_RX_MSG_COUNTERForcedBits

uint8_t

RX message counter register

PELICAN_RX_MSG_COUNTERForcedFlippedBits

uint8_t

RX message counter register

PELICAN_RX_MSG_COUNTERReadMask

uint8_t

RX message counter register

PELICAN_RX_MSG_COUNTERResetMask

uint8_t

RX message counter register

PELICAN_RX_MSG_COUNTERResetValue

uint8_t

RX message counter register

PELICAN_RX_MSG_COUNTERWriteMask

uint8_t

RX message counter register

PELICAN_TX_ERR_COUNTERColdResetValue

uint8_t

TX error counter register

PELICAN_TX_ERR_COUNTERForcedBits

uint8_t

TX error counter register

PELICAN_TX_ERR_COUNTERForcedFlippedBits

uint8_t

TX error counter register

PELICAN_TX_ERR_COUNTERReadMask

uint8_t

TX error counter register

PELICAN_TX_ERR_COUNTERResetMask

uint8_t

TX error counter register

PELICAN_TX_ERR_COUNTERResetValue

uint8_t

TX error counter register

PELICAN_TX_ERR_COUNTERWriteMask

uint8_t

TX error counter register

PELICAN_TX_FIColdResetValue

uint8_t

TX frame info register for PeliCAN mode

PELICAN_TX_FIForcedBits

uint8_t

TX frame info register for PeliCAN mode

PELICAN_TX_FIForcedFlippedBits

uint8_t

TX frame info register for PeliCAN mode

PELICAN_TX_FIReadMask

uint8_t

TX frame info register for PeliCAN mode

PELICAN_TX_FIResetMask

uint8_t

TX frame info register for PeliCAN mode

PELICAN_TX_FIResetValue

uint8_t

TX frame info register for PeliCAN mode

PELICAN_TX_FIWriteMask

uint8_t

TX frame info register for PeliCAN mode

ReplayLoggingFlags

uint64_t

Replay-time category logging flags

STATUSColdResetValue

uint8_t

Status register

STATUSForcedBits

uint8_t

Status register

STATUSForcedFlippedBits

uint8_t

Status register

STATUSReadMask

uint8_t

Status register

STATUSResetMask

uint8_t

Status register

STATUSResetValue

uint8_t

Status register

STATUSWriteMask

uint8_t

Status register

TimeSource

*void

Time source object

basiccan.acceptCode

uint8_t

Accept code register for BasicCAN mode

basiccan.acceptMask

uint8_t

Accept mask register for BasicCAN mode

basiccan.ctrl

uint8_t

Control register for BasicCAN mode

basiccan.txID

[uint8_t; 2]

TxID register for BasicCAN mode

bus

temu_IfaceRef/ <unknown>

CAN bus the device is connected to.

busTiming

[uint8_t; 2]

Bus timing register

clockDivider

uint8_t

Clock divider register

command

uint8_t

Command register

config.infiniteSpeed

uint8_t

Enable infinite speed mode (no delays when sending messages).

config.interrupt

uint8_t

External interrupt raised with IRQ controller.

fifo.data

[uint8_t; 64]

RX FIFO data buffer.

fifo.start

uint32_t

RX FIFO buffer start location.

fifo.usage

uint32_t

RX FIFO buffer usage.

interrupt

uint8_t

Interrupt register

irqCtrl

temu_IfaceRef/ <unknown>

Interrupt controller.

pelican.acceptCode

[uint8_t; 4]

Accept code register for PeliCAN mode

pelican.acceptMask

[uint8_t; 4]

Accept mask register for PeliCAN mode

pelican.arbLostCaputure

uint8_t

Arbitration lost capture register

pelican.errCodeCapture

uint8_t

Error code capture register

pelican.errWarnLimit

uint8_t

Error warning limit register

pelican.interruptEnable

uint8_t

Interrupt enable register for PeliCAN mode

pelican.mode

uint8_t

Mode register for PeliCAN mode

pelican.rxErrCounter

uint8_t

RX error counter register

pelican.rxMsgCounter

uint8_t

RX message counter register

pelican.txErrCounter

uint8_t

TX error counter register

pelican.txFI

uint8_t

TX frame info register for PeliCAN mode

pelican.txID

[uint8_t; 4]

TxID register for PeliCAN mode

status

uint8_t

Status register

txData

[uint8_t; 8]

TX data buffer

Interfaces

Name Type Description

AhbIface

AhbIface

AHB interface

CanDevIface

CanDevIface

CAN device interface.

DeviceIface

DeviceIface

Device interface.

MemAccessIface

MemAccessIface

Memory access interface for memory mapped registers.

RegisterIface

temu::RegisterIface

Auto-generated Register Interface Impl.

ResetIface

ResetIface

Registers

Register support is currently experimental!

Register Bank BasicCAN

Register BASIC_CONTROL
Description

Control register for BasicCAN mode

Reset value

0x00

Warm reset mask

0x1f

Diagram
Field Mask Reset Description

DOIE

0x10

0x0

Data overrun interrupt enable

EIE

0x08

0x0

Error interrupt enable

TIE

0x04

0x0

Transmit interrupt enable

RIE

0x02

0x0

Receive interrupt enable

RR

0x01

0x0

Reset request
Register BASIC_ACCEPT_CODE
Description

Accept code register for BasicCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register BASIC_ACCEPT_MASK
Description

Accept mask register for BasicCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register BASIC_TXID
Description

TxID register for BasicCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register BASIC_TXID
Description

TxID register for BasicCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0

Register Bank DefaultRegs

Register COMMAND
Description

Command register

Reset value

0x00

Warm reset mask

0x00

Diagram
Field Mask Reset Description

SRR

0x10

-

Self reception request

CDO

0x08

-

Clear data overrun

RRB

0x04

-

Release receive buffer

AT

0x02

-

Abort transmission

TR

0x01

-

Transmission request
Register STATUS
Description

Status register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

BS

0x80

0x0

Bus status

ES

0x40

0x0

Error status

TS

0x20

0x0

Transmit status

RS

0x10

0x0

Receive status

TCS

0x08

0x0

Transmission complete status

TBS

0x04

0x0

Transmit buffer status

DOS

0x02

0x0

Data overrun status

RBS

0x01

0x0

Receive buffer status
Register INTERRUPT
Description

Interrupt register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

BEI

0x80

0x0

Bus error interrupt

ALI

0x40

0x0

Arbitration lost interrupt

EPI

0x20

0x0

Error passive interrupt

WUI

0x10

0x0

Wake-up interrupt

DOI

0x08

0x0

Data overrun interrupt

EI

0x04

0x0

Error interrupt

TI

0x02

0x0

Transmit interrupt

RI

0x01

0x0

Receive interrupt
Register CLOCKDIVIDER
Description

Clock divider register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

CANMODE

0x80

0x0

CAN mode select

CD

0x7f

0x0

Clock divider
Register BUSTIMING
Description

Bus timing register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register BUSTIMING
Description

Bus timing register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register TXDATA
Description

TX data buffer

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register TXDATA
Description

TX data buffer

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register TXDATA
Description

TX data buffer

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register TXDATA
Description

TX data buffer

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register TXDATA
Description

TX data buffer

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register TXDATA
Description

TX data buffer

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register TXDATA
Description

TX data buffer

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register TXDATA
Description

TX data buffer

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0

Register Bank PeliCAN

Register PELICAN_MODE
Description

Mode register for PeliCAN mode

Reset value

0x00

Warm reset mask

0x1f

Diagram
Field Mask Reset Description

SM

0x10

0x0

Sleep mode

AFM

0x08

0x0

Acceptance filter mode

STM

0x04

0x0

Self test mode

LOM

0x02

0x0

Listen only mode

RM

0x01

0x0

Reset mode
Register PELICAN_INTERRUPT_ENABLE
Description

Interrupt enable register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

BEIE

0x80

0x0

Bus error interrupt enable

ALIE

0x40

0x0

Arbitration lost interrupt enable

EPIE

0x20

0x0

Error passive interrupt enable

WUIE

0x10

0x0

Wake-up interrupt enable

DOIE

0x08

0x0

Data overrun interrupt enable

EIE

0x04

0x0

Error interrupt enable

TIE

0x02

0x0

Transmit interrupt enable

RIE

0x01

0x0

Receive interrupt enable
Register PELICAN_ARB_LOST_CAPTURE
Description

Arbitration lost capture register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ERR_CODE_CAPTURE
Description

Error code capture register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ERR_WARN_LIMIT
Description

Error warning limit register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_RX_ERR_COUNTER
Description

RX error counter register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_TX_ERR_COUNTER
Description

TX error counter register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_TX_FI
Description

TX frame info register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xcf

Diagram
Field Mask Reset Description

FF

0x80

0x0

Frame format

RTR

0x40

0x0

Remote transmission request

DLC

0x0f

0x0

Data length code
Register PELICAN_RX_MSG_COUNTER
Description

RX message counter register

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ACCEPT_CODE
Description

Accept code register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ACCEPT_CODE
Description

Accept code register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ACCEPT_CODE
Description

Accept code register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ACCEPT_CODE
Description

Accept code register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_TX_ID
Description

TxID register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_TX_ID
Description

TxID register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_TX_ID
Description

TxID register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_TX_ID
Description

TxID register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ACCEPT_MASK
Description

Accept mask register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ACCEPT_MASK
Description

Accept mask register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ACCEPT_MASK
Description

Accept mask register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0
Register PELICAN_ACCEPT_MASK
Description

Accept mask register for PeliCAN mode

Reset value

0x00

Warm reset mask

0xff

Diagram
Field Mask Reset Description

VALUE

0xff

0x0

Commands

Name Description

delete

Dispose instance of CAN_OC

Limitations

The following deviations from real hardware are known to exist with this model:

  • The controller clears the RX and TX buffers on reset. This is not the proper behavior and may have an impact on FDIR. Let us know if this is an issue.

  • There is no arbitration of messages in the simulated world and busses are not synchronised.

  • The model does at present not register filters with the CAN bus model.

  • The model currently ignores the error field in the CAN frame objects.

  • The model currently assumes the CAN bus is running at 1 Mb/s (this assumption is in non-infinite speed mode). This is arguably incorrect and the timing should be picked from the bus timing register Contact Terma if this is this is critical for your needs.