P2020 PIC Model

This section describes the P2020 Programmable Interrupt Controller.

PIC implements two types of programmable interrupt outputs: critical interrupts (cint) and non-critical interrupts (int). Support for the following interrupt types:

  • External — Off-chip signals (12 interrupts);

  • Internal - On-chip sources from peripheral logic (64 interrupts);

  • Global timers A (4 interrupts) and B (4 interrupts) internal to the PIC;

  • Interprocessor interrupts (4 interrupts);

  • Message registers, used for interprocessor communication (8 interrupts);

  • Shared message signaled registers, used for cross-program communication (8 interrupts).

PIC has support for two processors, all interrups can be routed to processor core 0 or 1. Multi-cast delivery mode for interprocessor and global timer interrupts allowing these interrupts to be routed to either core 0 or 1, or both cores.

Each interrupt source routed to int is assigned a priority value (range from 0x00 to 0x0f. Therefore, setting int priority to zero inhibits that interrupt. Likewise, setting CTPR[TASKP] (task priority threshold) to 0x0f prevents the PIC from delivering interrupts to that core through the int signal. Note that this is the reset TASKP value, preventing the PIC from asserting int before the PIC is configured.

Loading the Plugin

import P2020

Configuration

config.nCpu

Number of processors supported (1 or 2).

config.CCBFrequency

CCB frequency in MHz (dafault 333 MHz), used for timer frequency reporting calculation.

config.RTCFrequency

RTC frequency in MHz (dafault 64 MHz), used for timer frequency reporting calculation.

config.logInterrupts

Additional logs with raised interrupts information.

The PIC programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. You can set resgisters value as follows:

Setting registers via Command Line
# Set mixed mode On. Interrupts are handled by the normal priority and delivery mechanisms of the PIC.
pic.GCR = 0x20000000

# Set min task priority = 1 (max = 0x0f) for processor core 0, interrupt priority must exceed this value for the interrupt request to be serviced
pic.CTPR[0]=0x00000001

# Allow interrupts from DUART (default internal interrupt number for DUART is 26), set its priority to max value = 0x0f
pic.IIVPR[26]=0x000F0000

# Mark DUART interrupts as non-critical(int) and set processor core 1 as a recipient
pic.IIDR[26]=0x00000001

# Mark DUART interrupts as critical(cint) and set processor core 1 as a recipient
pic.IIDR[26]=0x40000000
Setting registers via API
// Set mixed mode On. Interrupts are handled by the normal priority and delivery mechanisms of the PIC.
temu_writeValueU32(pic, "GCR", 0x20000000, 0);

// Mark DUART interrupts as critical(cint) and set processor core 1 as a recipient
temu_writeValueU32(pic, "IIDR", 0x40000000, 26);

@PIC Reference

Properties

Name Type Description

Class

*void

Class object

Component

*void

Pointer to component object if part of component

LocalName

*char

Local name (in component, if applicable)

LoggingFlags

uint64_t

Flags for logging info

Name

*char

Object name

TimeSource

*void

Time source object

Commands

Name Description

delete

Dispose instance of @PIC

new

Create new instance of PIC

Command new Arguments

Name Type Required Description

name

string

yes

Name of object to create

PIC Reference

Properties

Name Type Description

BRR1

uint32_t

PIC Block revision register 1

BRR2

uint32_t

PIC Block revision register 2

CISR0

uint32_t

PIC Critical interrupt summary register 0

CISR1

uint32_t

PIC Critical interrupt summary register 1

CISR2

uint32_t

PIC Critical interrupt summary register 2

CTPR

[uint32_t; 2]

PIC CoreCurrentTaskPriorityReg register

Class

*void

Class object

Component

*void

Pointer to component object if part of component

EIDR

[uint32_t; 12]

EIVPR

[uint32_t; 12]

EOI

[uint32_t; 2]

PIC End of interrupt register

ERQSR

uint32_t

PIC External interrupt summary register

FRR

uint32_t

PIC Feature reporting register

GCR

uint32_t

PIC GlobalConfiguration register

GTBCR

[uint32_t; 8]

GTCCR

[uint32_t; 8]

GTDR

[uint32_t; 8]

GTVPR

[uint32_t; 8]

IACK

[uint32_t; 2]

PIC Interrupt acknowledge register

IIDR

[uint32_t; 64]

IIVPR

[uint32_t; 64]

IPIDR

[uint32_t; 4]

IPIVPR

[uint32_t; 4]

IPR

[uint64_t; 4]

Internal IPR registers (128 bit registers split in two parts each)

IRQSR0

uint32_t

PIC IRQ_OUT_B summary register 0

IRQSR1

uint32_t

PIC IRQ_OUT_B summary register 1

IRQSR2

uint32_t

PIC IRQ_OUT_B summary register 2

IRR

[uint32_t; 2]

Interrupt request register with IRQ number of raised interrupt for each core

ISR

[uint64_t; 4]

Internal IPR registers (128 bit registers split in two parts each)

LocalName

*char

Local name (in component, if applicable)

LoggingFlags

uint64_t

Flags for logging info

MER

[uint32_t; 2]

MIDR

[uint32_t; 8]

MIVPR

[uint32_t; 8]

MSGR

[uint32_t; 8]

MSIDR

[uint32_t; 8]

MSIIR

uint32_t

MSIR

[uint32_t; 8]

MSIVPR

[uint32_t; 8]

MSR

[uint32_t; 2]

Name

*char

Object name

PIR

uint32_t

PIC Processor core initialization register

PMMR0

[uint32_t; 4]

Performance monitor n mask register 0

PMMR1

[uint32_t; 4]

Performance monitor n mask register 1

PMMR2

[uint32_t; 4]

Performance monitor n mask register 2

SVR

uint32_t

PIC Spurious vector register

TCR

[uint32_t; 2]

TFRR

[uint32_t; 2]

TimeSource

*void

Time source object

VIR

uint32_t

PIC Vendor identification register

config.CCBFrequency

uint32_t

CCB frequency in MHz

config.RTCFrequency

uint32_t

RTC frequency in MHz

config.logInterrupts

uint8_t

config.nCpu

uint8_t

config.traceReads

uint8_t

config.traceWrites

uint8_t

cpu

[temu_IfaceRef; 2]/ <unknown>

currentCrit

uint8_t

currentInt

uint8_t

irqCtrl

[temu_IfaceRef; 2]/ <unknown>

Interfaces

Name Type Description

DeviceIface

DeviceIface

ExternalIrqIface

IrqCtrlIface

InternalIrqIface

IrqCtrlIface

IrqClientIface

IrqClientIface

uptree interrupt handlers (e.g. CPUs)

MemAccessIface

MemAccessIface

ResetIface

ResetIface

Ports

Prop Iface Description

irqCtrl

IrqClientIface

irq port

Commands

Name Description

ackIrq

Acknowledge interrupt

delete

Dispose instance of PIC

endOfIrq

End current interrupt

lowerExternalIrq

Lower external interrupt

pstat

Print status

raiseExternalIrq

Raise external interrupt

raiseInternalIrq

Raise internally interrupt

Command ackIrq Arguments

Name Type Required Description

cpu

int

yes

Processor number

Command endOfIrq Arguments

Name Type Required Description

cpu

int

yes

Processor number

Command lowerExternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number

Command raiseExternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number

Command raiseInternalIrq Arguments

Name Type Required Description

irq

int

yes

Interrupt number

Limitations

  • External IRQ_OUT signal is not supported