P2020 PIC Model
This section describes the P2020 Programmable Interrupt Controller.
PIC implements two types of programmable interrupt outputs: critical interrupts (cint) and non-critical interrupts (int). Support for the following interrupt types:
-
External — Off-chip signals (12 interrupts);
-
Internal - On-chip sources from peripheral logic (64 interrupts);
-
Global timers A (4 interrupts) and B (4 interrupts) internal to the PIC;
-
Interprocessor interrupts (4 interrupts);
-
Message registers, used for interprocessor communication (8 interrupts);
-
Shared message signaled registers, used for cross-program communication (8 interrupts).
PIC has support for two processors, all interrups can be routed to processor core 0 or 1. Multi-cast delivery mode for interprocessor and global timer interrupts allowing these interrupts to be routed to either core 0 or 1, or both cores.
Each interrupt source routed to int is assigned a priority value (range from 0x00 to 0x0f. Therefore, setting int priority to zero inhibits that interrupt. Likewise, setting CTPR[TASKP] (task priority threshold) to 0x0f prevents the PIC from delivering interrupts to that core through the int signal. Note that this is the reset TASKP value, preventing the PIC from asserting int before the PIC is configured.
Configuration
- config.nCpu
-
Number of processors supported (1 or 2).
- config.CCBFrequency
-
CCB frequency in MHz (dafault 333 MHz), used for timer frequency reporting calculation.
- config.RTCFrequency
-
RTC frequency in MHz (dafault 64 MHz), used for timer frequency reporting calculation.
- config.logInterrupts
-
Additional logs with raised interrupts information.
The PIC programmable registers that occupy memory-mapped space are named according to P2020 QorIQ integrated processor reference manual. You can set resgisters value as follows:
# Set mixed mode On. Interrupts are handled by the normal priority and delivery mechanisms of the PIC.
pic.GCR = 0x20000000
# Set min task priority = 1 (max = 0x0f) for processor core 0, interrupt priority must exceed this value for the interrupt request to be serviced
pic.CTPR[0]=0x00000001
# Allow interrupts from DUART (default internal interrupt number for DUART is 26), set its priority to max value = 0x0f
pic.IIVPR[26]=0x000F0000
# Mark DUART interrupts as non-critical(int) and set processor core 1 as a recipient
pic.IIDR[26]=0x00000001
# Mark DUART interrupts as critical(cint) and set processor core 1 as a recipient
pic.IIDR[26]=0x40000000
// Set mixed mode On. Interrupts are handled by the normal priority and delivery mechanisms of the PIC.
temu_writeValueU32(pic, "GCR", 0x20000000, 0);
// Mark DUART interrupts as critical(cint) and set processor core 1 as a recipient
temu_writeValueU32(pic, "IIDR", 0x40000000, 26);
@PIC Reference
Properties
| Name | Type | Description |
|---|---|---|
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
TimeSource |
*void |
Time source object |
PIC Reference
Properties
| Name | Type | Description |
|---|---|---|
BRR1 |
uint32_t |
Block revision register 1 |
BRR1ColdResetValue |
uint32_t |
Block revision register 1 |
BRR1ForcedBits |
uint32_t |
Block revision register 1 |
BRR1ForcedFlippedBits |
uint32_t |
Block revision register 1 |
BRR1ReadMask |
uint32_t |
Block revision register 1 |
BRR1ResetMask |
uint32_t |
Block revision register 1 |
BRR1ResetValue |
uint32_t |
Block revision register 1 |
BRR1WriteMask |
uint32_t |
Block revision register 1 |
BRR2 |
uint32_t |
Block revision register 2 |
BRR2ColdResetValue |
uint32_t |
Block revision register 2 |
BRR2ForcedBits |
uint32_t |
Block revision register 2 |
BRR2ForcedFlippedBits |
uint32_t |
Block revision register 2 |
BRR2ReadMask |
uint32_t |
Block revision register 2 |
BRR2ResetMask |
uint32_t |
Block revision register 2 |
BRR2ResetValue |
uint32_t |
Block revision register 2 |
BRR2WriteMask |
uint32_t |
Block revision register 2 |
CISR0 |
uint32_t |
Critical interrupt summary register 0 |
CISR0ColdResetValue |
uint32_t |
Critical interrupt summary register 0 |
CISR0ForcedBits |
uint32_t |
Critical interrupt summary register 0 |
CISR0ForcedFlippedBits |
uint32_t |
Critical interrupt summary register 0 |
CISR0ReadMask |
uint32_t |
Critical interrupt summary register 0 |
CISR0ResetMask |
uint32_t |
Critical interrupt summary register 0 |
CISR0ResetValue |
uint32_t |
Critical interrupt summary register 0 |
CISR0WriteMask |
uint32_t |
Critical interrupt summary register 0 |
CISR1 |
uint32_t |
Critical interrupt summary register 1 |
CISR1ColdResetValue |
uint32_t |
Critical interrupt summary register 1 |
CISR1ForcedBits |
uint32_t |
Critical interrupt summary register 1 |
CISR1ForcedFlippedBits |
uint32_t |
Critical interrupt summary register 1 |
CISR1ReadMask |
uint32_t |
Critical interrupt summary register 1 |
CISR1ResetMask |
uint32_t |
Critical interrupt summary register 1 |
CISR1ResetValue |
uint32_t |
Critical interrupt summary register 1 |
CISR1WriteMask |
uint32_t |
Critical interrupt summary register 1 |
CISR2 |
uint32_t |
Critical interrupt summary register 2 |
CISR2ColdResetValue |
uint32_t |
Critical interrupt summary register 2 |
CISR2ForcedBits |
uint32_t |
Critical interrupt summary register 2 |
CISR2ForcedFlippedBits |
uint32_t |
Critical interrupt summary register 2 |
CISR2ReadMask |
uint32_t |
Critical interrupt summary register 2 |
CISR2ResetMask |
uint32_t |
Critical interrupt summary register 2 |
CISR2ResetValue |
uint32_t |
Critical interrupt summary register 2 |
CISR2WriteMask |
uint32_t |
Critical interrupt summary register 2 |
CTPR |
uint32_t |
Current task priority register |
CTPRColdResetValue |
uint32_t |
Current task priority register |
CTPRForcedBits |
uint32_t |
Current task priority register |
CTPRForcedFlippedBits |
uint32_t |
Current task priority register |
CTPRReadMask |
uint32_t |
Current task priority register |
CTPRResetMask |
uint32_t |
Current task priority register |
CTPRResetValue |
uint32_t |
Current task priority register |
CTPRWriteMask |
uint32_t |
Current task priority register |
CTPR_CPU |
[uint32_t; 2] |
Processor core current task priority register |
Class |
*void |
Class object |
Component |
*void |
Pointer to component object if part of component |
EIDR |
[uint32_t; 12] |
External interrupt destination register |
EIVPR |
[uint32_t; 12] |
External interrupt vector/priority register |
EOI |
uint32_t |
End of interrupt register |
EOIColdResetValue |
uint32_t |
End of interrupt register |
EOIForcedBits |
uint32_t |
End of interrupt register |
EOIForcedFlippedBits |
uint32_t |
End of interrupt register |
EOIReadMask |
uint32_t |
End of interrupt register |
EOIResetMask |
uint32_t |
End of interrupt register |
EOIResetValue |
uint32_t |
End of interrupt register |
EOIWriteMask |
uint32_t |
End of interrupt register |
EOI_CPU |
[uint32_t; 2] |
Processor core end of interrupt register |
ERQSR |
uint32_t |
External interrupt summary register |
ERQSRColdResetValue |
uint32_t |
External interrupt summary register |
ERQSRForcedBits |
uint32_t |
External interrupt summary register |
ERQSRForcedFlippedBits |
uint32_t |
External interrupt summary register |
ERQSRReadMask |
uint32_t |
External interrupt summary register |
ERQSRResetMask |
uint32_t |
External interrupt summary register |
ERQSRResetValue |
uint32_t |
External interrupt summary register |
ERQSRWriteMask |
uint32_t |
External interrupt summary register |
FRR |
uint32_t |
Feature reporting register |
FRRColdResetValue |
uint32_t |
Feature reporting register |
FRRForcedBits |
uint32_t |
Feature reporting register |
FRRForcedFlippedBits |
uint32_t |
Feature reporting register |
FRRReadMask |
uint32_t |
Feature reporting register |
FRRResetMask |
uint32_t |
Feature reporting register |
FRRResetValue |
uint32_t |
Feature reporting register |
FRRWriteMask |
uint32_t |
Feature reporting register |
GCR |
uint32_t |
Global configuration register |
GCRColdResetValue |
uint32_t |
Global configuration register |
GCRForcedBits |
uint32_t |
Global configuration register |
GCRForcedFlippedBits |
uint32_t |
Global configuration register |
GCRReadMask |
uint32_t |
Global configuration register |
GCRResetMask |
uint32_t |
Global configuration register |
GCRResetValue |
uint32_t |
Global configuration register |
GCRWriteMask |
uint32_t |
Global configuration register |
GTBCR |
[uint32_t; 8] |
Global timer base count register |
GTCCR |
[uint32_t; 8] |
Global timer current count register |
GTDR |
[uint32_t; 8] |
Global timer destination register |
GTVPR |
[uint32_t; 8] |
Global timer vector/priority register |
IACK |
uint32_t |
Interrupt acknowledge register |
IACKColdResetValue |
uint32_t |
Interrupt acknowledge register |
IACKForcedBits |
uint32_t |
Interrupt acknowledge register |
IACKForcedFlippedBits |
uint32_t |
Interrupt acknowledge register |
IACKReadMask |
uint32_t |
Interrupt acknowledge register |
IACKResetMask |
uint32_t |
Interrupt acknowledge register |
IACKResetValue |
uint32_t |
Interrupt acknowledge register |
IACKWriteMask |
uint32_t |
Interrupt acknowledge register |
IACK_CPU |
[uint32_t; 2] |
Processor core interrupt acknowledge register |
IIDR |
[uint32_t; 64] |
Internal interrupt destination register |
IIVPR |
[uint32_t; 64] |
Internal interrupt vector/priority register |
IPIDR |
[uint32_t; 4] |
Interprocessor interrupt dispatch register |
IPIDR_CPU |
[uint32_t; 8] |
Processor core interprocessor dispatch register |
IPIVPR |
[uint32_t; 4] |
Interprocessor interrupt vector/priority register |
IPR |
[uint64_t; 4] |
Internal IPR registers (128 bit registers split in two parts each) |
IRQSR0 |
uint32_t |
IRQ_OUT_B summary register 0 |
IRQSR0ColdResetValue |
uint32_t |
IRQ_OUT_B summary register 0 |
IRQSR0ForcedBits |
uint32_t |
IRQ_OUT_B summary register 0 |
IRQSR0ForcedFlippedBits |
uint32_t |
IRQ_OUT_B summary register 0 |
IRQSR0ReadMask |
uint32_t |
IRQ_OUT_B summary register 0 |
IRQSR0ResetMask |
uint32_t |
IRQ_OUT_B summary register 0 |
IRQSR0ResetValue |
uint32_t |
IRQ_OUT_B summary register 0 |
IRQSR0WriteMask |
uint32_t |
IRQ_OUT_B summary register 0 |
IRQSR1 |
uint32_t |
IRQ_OUT_B summary register 1 |
IRQSR1ColdResetValue |
uint32_t |
IRQ_OUT_B summary register 1 |
IRQSR1ForcedBits |
uint32_t |
IRQ_OUT_B summary register 1 |
IRQSR1ForcedFlippedBits |
uint32_t |
IRQ_OUT_B summary register 1 |
IRQSR1ReadMask |
uint32_t |
IRQ_OUT_B summary register 1 |
IRQSR1ResetMask |
uint32_t |
IRQ_OUT_B summary register 1 |
IRQSR1ResetValue |
uint32_t |
IRQ_OUT_B summary register 1 |
IRQSR1WriteMask |
uint32_t |
IRQ_OUT_B summary register 1 |
IRQSR2 |
uint32_t |
IRQ_OUT_B summary register 2 |
IRQSR2ColdResetValue |
uint32_t |
IRQ_OUT_B summary register 2 |
IRQSR2ForcedBits |
uint32_t |
IRQ_OUT_B summary register 2 |
IRQSR2ForcedFlippedBits |
uint32_t |
IRQ_OUT_B summary register 2 |
IRQSR2ReadMask |
uint32_t |
IRQ_OUT_B summary register 2 |
IRQSR2ResetMask |
uint32_t |
IRQ_OUT_B summary register 2 |
IRQSR2ResetValue |
uint32_t |
IRQ_OUT_B summary register 2 |
IRQSR2WriteMask |
uint32_t |
IRQ_OUT_B summary register 2 |
IRR |
[uint32_t; 2] |
Interrupt request register with IRQ number of raised interrupt for each core |
ISR |
[uint64_t; 4] |
Internal IPR registers (128 bit registers split in two parts each) |
LocalName |
*char |
Local name (in component, if applicable) |
LogMessageFlags |
uint64_t |
Per-object log message suppression flags |
LoggingFlags |
uint64_t |
Flags for logging info |
MER |
[uint32_t; 2] |
Message enable register |
MIDR |
[uint32_t; 8] |
Messaging interrupt destination register |
MIVPR |
[uint32_t; 8] |
Messaging interrupt vector/priority register |
MSGR |
[uint32_t; 8] |
Message register |
MSIDR |
[uint32_t; 8] |
Shared message signaled interrupt destination register |
MSIIR |
uint32_t |
Shared message signaled interrupt index register |
MSIIRColdResetValue |
uint32_t |
Shared message signaled interrupt index register |
MSIIRForcedBits |
uint32_t |
Shared message signaled interrupt index register |
MSIIRForcedFlippedBits |
uint32_t |
Shared message signaled interrupt index register |
MSIIRReadMask |
uint32_t |
Shared message signaled interrupt index register |
MSIIRResetMask |
uint32_t |
Shared message signaled interrupt index register |
MSIIRResetValue |
uint32_t |
Shared message signaled interrupt index register |
MSIIRWriteMask |
uint32_t |
Shared message signaled interrupt index register |
MSIR |
[uint32_t; 8] |
Shared message signaled interrupt register |
MSISR |
uint32_t |
Shared message signaled interrupt status register |
MSISRColdResetValue |
uint32_t |
Shared message signaled interrupt status register |
MSISRForcedBits |
uint32_t |
Shared message signaled interrupt status register |
MSISRForcedFlippedBits |
uint32_t |
Shared message signaled interrupt status register |
MSISRReadMask |
uint32_t |
Shared message signaled interrupt status register |
MSISRResetMask |
uint32_t |
Shared message signaled interrupt status register |
MSISRResetValue |
uint32_t |
Shared message signaled interrupt status register |
MSISRWriteMask |
uint32_t |
Shared message signaled interrupt status register |
MSIVPR |
[uint32_t; 8] |
Shared message signaled interrupt vector/priority register |
MSR |
[uint32_t; 2] |
Message status register |
Name |
*char |
Object name |
ObjectID |
uint64_t |
Unique ObjectID. |
PIR |
uint32_t |
Processor core initialization register |
PIRColdResetValue |
uint32_t |
Processor core initialization register |
PIRForcedBits |
uint32_t |
Processor core initialization register |
PIRForcedFlippedBits |
uint32_t |
Processor core initialization register |
PIRReadMask |
uint32_t |
Processor core initialization register |
PIRResetMask |
uint32_t |
Processor core initialization register |
PIRResetValue |
uint32_t |
Processor core initialization register |
PIRWriteMask |
uint32_t |
Processor core initialization register |
PMMR0 |
[uint32_t; 4] |
Performance monitor mask register 0 |
PMMR1 |
[uint32_t; 4] |
Performance monitor mask register 1 |
PMMR2 |
[uint32_t; 4] |
Performance monitor mask register 2 |
ReplayLoggingFlags |
uint64_t |
Replay-time category logging flags |
SVR |
uint32_t |
Spurious vector register |
SVRColdResetValue |
uint32_t |
Spurious vector register |
SVRForcedBits |
uint32_t |
Spurious vector register |
SVRForcedFlippedBits |
uint32_t |
Spurious vector register |
SVRReadMask |
uint32_t |
Spurious vector register |
SVRResetMask |
uint32_t |
Spurious vector register |
SVRResetValue |
uint32_t |
Spurious vector register |
SVRWriteMask |
uint32_t |
Spurious vector register |
TCR |
[uint32_t; 2] |
Timer control register |
TFRR |
[uint32_t; 2] |
Timer frequency reporting register |
TimeSource |
*void |
Time source object |
VIR |
uint32_t |
Vendor identification register |
VIRColdResetValue |
uint32_t |
Vendor identification register |
VIRForcedBits |
uint32_t |
Vendor identification register |
VIRForcedFlippedBits |
uint32_t |
Vendor identification register |
VIRReadMask |
uint32_t |
Vendor identification register |
VIRResetMask |
uint32_t |
Vendor identification register |
VIRResetValue |
uint32_t |
Vendor identification register |
VIRWriteMask |
uint32_t |
Vendor identification register |
WHOAMI |
uint32_t |
Who am I register |
WHOAMIColdResetValue |
uint32_t |
Who am I register |
WHOAMIForcedBits |
uint32_t |
Who am I register |
WHOAMIForcedFlippedBits |
uint32_t |
Who am I register |
WHOAMIReadMask |
uint32_t |
Who am I register |
WHOAMIResetMask |
uint32_t |
Who am I register |
WHOAMIResetValue |
uint32_t |
Who am I register |
WHOAMIWriteMask |
uint32_t |
Who am I register |
WHOAMI_CPU |
[uint32_t; 2] |
Processor core who am I register |
config.CCBFrequency |
uint32_t |
CCB frequency in MHz |
config.RTCFrequency |
uint32_t |
RTC frequency in MHz |
config.logInterrupts |
uint8_t |
|
config.nCpu |
uint8_t |
|
config.traceReads |
uint8_t |
|
config.traceWrites |
uint8_t |
|
cpu |
[temu_IfaceRef; 2]/ <unknown> |
|
currentCrit |
uint8_t |
|
currentInt |
uint8_t |
|
irqCtrl |
[temu_IfaceRef; 2]/ <unknown> |
Interfaces
| Name | Type | Description |
|---|---|---|
DeviceIface |
DeviceIface |
|
ExternalIrqIface |
IrqCtrlIface |
|
InternalIrqIface |
IrqCtrlIface |
|
IrqClientIface |
IrqClientIface |
uptree interrupt handlers (e.g. CPUs) |
MemAccessIface |
MemAccessIface |
|
RegisterIface |
temu::RegisterIface |
Auto-generated Register Interface Impl. |
ResetIface |
ResetIface |
Registers
| Register support is currently experimental! |
Register Bank Regs
Register BRR1
- Description
-
Block revision register 1
- Reset value
-
0x00400301
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
IPID |
|
|
IP block ID |
IPMJ |
|
|
Major revision of the IP block |
IPMN |
|
|
Minor revision of the IP block |
Register BRR2
- Description
-
Block revision register 2
- Reset value
-
0x00000001
- Warm reset mask
-
0x00ff00ff
| Field | Mask | Reset | Description |
|---|---|---|---|
IPINTO |
|
|
IP block integration options |
IPCFGO |
|
|
IP block configuration options |
Register CTPR
- Description
-
Current task priority register
- Reset value
-
0x0000000f
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
TASKP |
|
|
Current task priority |
Register WHOAMI
- Description
-
Who am I register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000001f
| Field | Mask | Reset | Description |
|---|---|---|---|
ID |
|
|
Processor core ID |
Register IACK
- Description
-
Interrupt acknowledge register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VECTOR |
|
|
Acknowledged interrupt vector |
Register EOI
- Description
-
End of interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
EOI_CODE |
|
|
End-of-interrupt code |
Register FRR
- Description
-
Feature reporting register
- Reset value
-
0x006b0102
- Warm reset mask
-
0x07ff1fff
| Field | Mask | Reset | Description |
|---|---|---|---|
NIRQ |
|
|
Number of interrupts minus one |
NCPU |
|
|
Number of CPUs minus one |
VID |
|
|
OpenPIC version ID |
Register GCR
- Description
-
Global configuration register
- Reset value
-
0x00000000
- Warm reset mask
-
0xa0000000
| Field | Mask | Reset | Description |
|---|---|---|---|
RST |
|
|
PIC reset |
M |
|
|
PIC operating mode |
Register VIR
- Description
-
Vendor identification register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00ffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
STEP |
|
|
Silicon revision |
DEVICE_ID |
|
|
Device identifier |
VENDOR_ID |
|
|
Vendor identifier |
Register PIR
- Description
-
Processor core initialization register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Processor core 1 reset |
P0 |
|
|
Processor core 0 reset |
Register SVR
- Description
-
Spurious vector register
- Reset value
-
0x0000ffff
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VECTOR |
|
|
Spurious interrupt vector |
Register ERQSR
- Description
-
External interrupt summary register
- Reset value
-
0x00000000
- Warm reset mask
-
0xfff00000
| Field | Mask | Reset | Description |
|---|---|---|---|
EINTn |
|
|
External interrupt signal status |
Register IRQSR0
- Description
-
IRQ_OUT_B summary register 0
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000fff
| Field | Mask | Reset | Description |
|---|---|---|---|
EXTn |
|
|
External interrupts routed to IRQ_OUT_B |
Register IRQSR1
- Description
-
IRQ_OUT_B summary register 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupts 0-31 routed to IRQ_OUT_B |
Register IRQSR2
- Description
-
IRQ_OUT_B summary register 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupts 32-63 routed to IRQ_OUT_B |
Register CISR0
- Description
-
Critical interrupt summary register 0
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000fff
| Field | Mask | Reset | Description |
|---|---|---|---|
EXTn |
|
|
Active external critical interrupts |
Register CISR1
- Description
-
Critical interrupt summary register 1
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Active internal critical interrupts 0-31 |
Register CISR2
- Description
-
Critical interrupt summary register 2
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Active internal critical interrupts 32-63 |
Register MSISR
- Description
-
Shared message signaled interrupt status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x000000ff
| Field | Mask | Reset | Description |
|---|---|---|---|
Sn |
|
|
Shared MSI status bits |
Register MSIIR
- Description
-
Shared message signaled interrupt index register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
SRS |
|
|
Shared interrupt register select |
IBS |
|
|
Interrupt bit select |
Register IPIDR
- Description
-
Interprocessor interrupt dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR
- Description
-
Interprocessor interrupt dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR
- Description
-
Interprocessor interrupt dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR
- Description
-
Interprocessor interrupt dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIVPR
- Description
-
Interprocessor interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IPIVPR
- Description
-
Interprocessor interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IPIVPR
- Description
-
Interprocessor interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IPIVPR
- Description
-
Interprocessor interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register TFRR
- Description
-
Timer frequency reporting register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FREQ |
|
|
Timer frequency in ticks per second |
Register TFRR
- Description
-
Timer frequency reporting register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
FREQ |
|
|
Timer frequency in ticks per second |
Register GTCCR
- Description
-
Global timer current count register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TOG |
|
|
Timer toggle |
COUNT |
|
|
Current timer count |
Register GTCCR
- Description
-
Global timer current count register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TOG |
|
|
Timer toggle |
COUNT |
|
|
Current timer count |
Register GTCCR
- Description
-
Global timer current count register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TOG |
|
|
Timer toggle |
COUNT |
|
|
Current timer count |
Register GTCCR
- Description
-
Global timer current count register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TOG |
|
|
Timer toggle |
COUNT |
|
|
Current timer count |
Register GTCCR
- Description
-
Global timer current count register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TOG |
|
|
Timer toggle |
COUNT |
|
|
Current timer count |
Register GTCCR
- Description
-
Global timer current count register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TOG |
|
|
Timer toggle |
COUNT |
|
|
Current timer count |
Register GTCCR
- Description
-
Global timer current count register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TOG |
|
|
Timer toggle |
COUNT |
|
|
Current timer count |
Register GTCCR
- Description
-
Global timer current count register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
TOG |
|
|
Timer toggle |
COUNT |
|
|
Current timer count |
Register GTBCR
- Description
-
Global timer base count register
- Reset value
-
0x80000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
CI |
|
|
Count inhibit |
BASE_CNT |
|
|
Base timer count |
Register GTBCR
- Description
-
Global timer base count register
- Reset value
-
0x80000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
CI |
|
|
Count inhibit |
BASE_CNT |
|
|
Base timer count |
Register GTBCR
- Description
-
Global timer base count register
- Reset value
-
0x80000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
CI |
|
|
Count inhibit |
BASE_CNT |
|
|
Base timer count |
Register GTBCR
- Description
-
Global timer base count register
- Reset value
-
0x80000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
CI |
|
|
Count inhibit |
BASE_CNT |
|
|
Base timer count |
Register GTBCR
- Description
-
Global timer base count register
- Reset value
-
0x80000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
CI |
|
|
Count inhibit |
BASE_CNT |
|
|
Base timer count |
Register GTBCR
- Description
-
Global timer base count register
- Reset value
-
0x80000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
CI |
|
|
Count inhibit |
BASE_CNT |
|
|
Base timer count |
Register GTBCR
- Description
-
Global timer base count register
- Reset value
-
0x80000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
CI |
|
|
Count inhibit |
BASE_CNT |
|
|
Base timer count |
Register GTBCR
- Description
-
Global timer base count register
- Reset value
-
0x80000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
CI |
|
|
Count inhibit |
BASE_CNT |
|
|
Base timer count |
Register GTVPR
- Description
-
Global timer vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register GTVPR
- Description
-
Global timer vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register GTVPR
- Description
-
Global timer vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register GTVPR
- Description
-
Global timer vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register GTVPR
- Description
-
Global timer vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register GTVPR
- Description
-
Global timer vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register GTVPR
- Description
-
Global timer vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register GTVPR
- Description
-
Global timer vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register GTDR
- Description
-
Global timer destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register GTDR
- Description
-
Global timer destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register GTDR
- Description
-
Global timer destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register GTDR
- Description
-
Global timer destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register GTDR
- Description
-
Global timer destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register GTDR
- Description
-
Global timer destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register GTDR
- Description
-
Global timer destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register GTDR
- Description
-
Global timer destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register TCR
- Description
-
Timer control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x07010307
| Field | Mask | Reset | Description |
|---|---|---|---|
ROVR |
|
|
Timer roll-over control |
RTM |
|
|
Real time mode |
CLKR |
|
|
Timer clock ratio |
CASC |
|
|
Timer cascade mode |
Register TCR
- Description
-
Timer control register
- Reset value
-
0x00000000
- Warm reset mask
-
0x07010307
| Field | Mask | Reset | Description |
|---|---|---|---|
ROVR |
|
|
Timer roll-over control |
RTM |
|
|
Real time mode |
CLKR |
|
|
Timer clock ratio |
CASC |
|
|
Timer cascade mode |
Register PMMR0
- Description
-
Performance monitor mask register 0
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MShI |
|
|
Shared message signaled interrupt masks |
IPI |
|
|
Interprocessor interrupt masks |
TIMER |
|
|
Timer interrupt masks |
MSG |
|
|
Messaging interrupt masks |
EXT |
|
|
External interrupt masks |
Register PMMR0
- Description
-
Performance monitor mask register 0
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MShI |
|
|
Shared message signaled interrupt masks |
IPI |
|
|
Interprocessor interrupt masks |
TIMER |
|
|
Timer interrupt masks |
MSG |
|
|
Messaging interrupt masks |
EXT |
|
|
External interrupt masks |
Register PMMR0
- Description
-
Performance monitor mask register 0
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MShI |
|
|
Shared message signaled interrupt masks |
IPI |
|
|
Interprocessor interrupt masks |
TIMER |
|
|
Timer interrupt masks |
MSG |
|
|
Messaging interrupt masks |
EXT |
|
|
External interrupt masks |
Register PMMR0
- Description
-
Performance monitor mask register 0
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MShI |
|
|
Shared message signaled interrupt masks |
IPI |
|
|
Interprocessor interrupt masks |
TIMER |
|
|
Timer interrupt masks |
MSG |
|
|
Messaging interrupt masks |
EXT |
|
|
External interrupt masks |
Register PMMR1
- Description
-
Performance monitor mask register 1
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupt masks 0-31 |
Register PMMR1
- Description
-
Performance monitor mask register 1
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupt masks 0-31 |
Register PMMR1
- Description
-
Performance monitor mask register 1
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupt masks 0-31 |
Register PMMR1
- Description
-
Performance monitor mask register 1
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupt masks 0-31 |
Register PMMR2
- Description
-
Performance monitor mask register 2
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupt masks 32-63 |
Register PMMR2
- Description
-
Performance monitor mask register 2
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupt masks 32-63 |
Register PMMR2
- Description
-
Performance monitor mask register 2
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupt masks 32-63 |
Register PMMR2
- Description
-
Performance monitor mask register 2
- Reset value
-
0xffffffff
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
INTn |
|
|
Internal interrupt masks 32-63 |
Register MSGR
- Description
-
Message register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSG |
|
|
Message data |
Register MSGR
- Description
-
Message register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSG |
|
|
Message data |
Register MSGR
- Description
-
Message register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSG |
|
|
Message data |
Register MSGR
- Description
-
Message register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSG |
|
|
Message data |
Register MSGR
- Description
-
Message register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSG |
|
|
Message data |
Register MSGR
- Description
-
Message register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSG |
|
|
Message data |
Register MSGR
- Description
-
Message register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSG |
|
|
Message data |
Register MSGR
- Description
-
Message register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSG |
|
|
Message data |
Register MER
- Description
-
Message enable register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
En |
|
|
Message enable bits |
Register MER
- Description
-
Message enable register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
En |
|
|
Message enable bits |
Register MSR
- Description
-
Message status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
Sn |
|
|
Message status bits |
Register MSR
- Description
-
Message status register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
Sn |
|
|
Message status bits |
Register MSIR
- Description
-
Shared message signaled interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
SHn |
|
|
Shared interrupt pending bits |
Register MSIR
- Description
-
Shared message signaled interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
SHn |
|
|
Shared interrupt pending bits |
Register MSIR
- Description
-
Shared message signaled interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
SHn |
|
|
Shared interrupt pending bits |
Register MSIR
- Description
-
Shared message signaled interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
SHn |
|
|
Shared interrupt pending bits |
Register MSIR
- Description
-
Shared message signaled interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
SHn |
|
|
Shared interrupt pending bits |
Register MSIR
- Description
-
Shared message signaled interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
SHn |
|
|
Shared interrupt pending bits |
Register MSIR
- Description
-
Shared message signaled interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
SHn |
|
|
Shared interrupt pending bits |
Register MSIR
- Description
-
Shared message signaled interrupt register
- Reset value
-
0x00000000
- Warm reset mask
-
0xffffffff
| Field | Mask | Reset | Description |
|---|---|---|---|
SHn |
|
|
Shared interrupt pending bits |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIVPR
- Description
-
External interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc0cfffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
S |
|
|
Interrupt sense |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register EIDR
- Description
-
External interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIVPR
- Description
-
Internal interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc08fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
P |
|
|
Interrupt polarity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IIDR
- Description
-
Internal interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0xe0000003
| Field | Mask | Reset | Description |
|---|---|---|---|
EP |
|
|
Route interrupt to IRQ_OUT_B |
CI0 |
|
|
Route interrupt to critical interrupt 0 |
CI1 |
|
|
Route interrupt to critical interrupt 1 |
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MIVPR
- Description
-
Messaging interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MIVPR
- Description
-
Messaging interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MIVPR
- Description
-
Messaging interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MIVPR
- Description
-
Messaging interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MIVPR
- Description
-
Messaging interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MIVPR
- Description
-
Messaging interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MIVPR
- Description
-
Messaging interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MIVPR
- Description
-
Messaging interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MIDR
- Description
-
Messaging interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MIDR
- Description
-
Messaging interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MIDR
- Description
-
Messaging interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MIDR
- Description
-
Messaging interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MIDR
- Description
-
Messaging interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MIDR
- Description
-
Messaging interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MIDR
- Description
-
Messaging interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MIDR
- Description
-
Messaging interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MSIVPR
- Description
-
Shared message signaled interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MSIVPR
- Description
-
Shared message signaled interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MSIVPR
- Description
-
Shared message signaled interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MSIVPR
- Description
-
Shared message signaled interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MSIVPR
- Description
-
Shared message signaled interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MSIVPR
- Description
-
Shared message signaled interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MSIVPR
- Description
-
Shared message signaled interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MSIVPR
- Description
-
Shared message signaled interrupt vector/priority register
- Reset value
-
0x80000000
- Warm reset mask
-
0xc00fffff
| Field | Mask | Reset | Description |
|---|---|---|---|
MSK |
|
|
Interrupt mask |
A |
|
|
Interrupt activity |
PRIORITY |
|
|
Interrupt priority |
VECTOR |
|
|
Interrupt vector |
Register MSIDR
- Description
-
Shared message signaled interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MSIDR
- Description
-
Shared message signaled interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MSIDR
- Description
-
Shared message signaled interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MSIDR
- Description
-
Shared message signaled interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MSIDR
- Description
-
Shared message signaled interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MSIDR
- Description
-
Shared message signaled interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MSIDR
- Description
-
Shared message signaled interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register MSIDR
- Description
-
Shared message signaled interrupt destination register
- Reset value
-
0x00000001
- Warm reset mask
-
0x00000003
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Route interrupt to processor core 1 |
P0 |
|
|
Route interrupt to processor core 0 |
Register IPIDR_CPU
- Description
-
Processor core interprocessor dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR_CPU
- Description
-
Processor core interprocessor dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR_CPU
- Description
-
Processor core interprocessor dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR_CPU
- Description
-
Processor core interprocessor dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR_CPU
- Description
-
Processor core interprocessor dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR_CPU
- Description
-
Processor core interprocessor dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR_CPU
- Description
-
Processor core interprocessor dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register IPIDR_CPU
- Description
-
Processor core interprocessor dispatch register
- Reset value
-
0x00000000
- Warm reset mask
-
0x00000000
| Field | Mask | Reset | Description |
|---|---|---|---|
P1 |
|
|
Dispatch interprocessor interrupt to processor core 1 |
P0 |
|
|
Dispatch interprocessor interrupt to processor core 0 |
Register CTPR_CPU
- Description
-
Processor core current task priority register
- Reset value
-
0x0000000f
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
TASKP |
|
|
Current task priority |
Register CTPR_CPU
- Description
-
Processor core current task priority register
- Reset value
-
0x0000000f
- Warm reset mask
-
0x0000000f
| Field | Mask | Reset | Description |
|---|---|---|---|
TASKP |
|
|
Current task priority |
Register WHOAMI_CPU
- Description
-
Processor core who am I register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000001f
| Field | Mask | Reset | Description |
|---|---|---|---|
ID |
|
|
Processor core ID |
Register WHOAMI_CPU
- Description
-
Processor core who am I register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000001f
| Field | Mask | Reset | Description |
|---|---|---|---|
ID |
|
|
Processor core ID |
Register IACK_CPU
- Description
-
Processor core interrupt acknowledge register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VECTOR |
|
|
Acknowledged interrupt vector |
Register IACK_CPU
- Description
-
Processor core interrupt acknowledge register
- Reset value
-
0x00000000
- Warm reset mask
-
0x0000ffff
| Field | Mask | Reset | Description |
|---|---|---|---|
VECTOR |
|
|
Acknowledged interrupt vector |